CN101035187A - Data buffer method, vertical zooming circuit and terminal - Google Patents
Data buffer method, vertical zooming circuit and terminal Download PDFInfo
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Abstract
The invention discloses a data buffering method, where buffer memory module is stored with the Nth row of data, and the method comprises: writing a basic data unit group in the (N+1)th row of data into the buffer memory module; after finishing the write operation, from the buffer memory module, outputting a basic data unit group in the (N+1)th row of data, lately written in the buffer, and the corresponding basic data unit group in the Nth row of data to the one lately written in the buffer memory module; after finishing the output operation, writing the next basic data unit group in the (N+1)th row of data into the space occupied by the outputted basic data unit group in the Nth row of data; so repeating the output and write operations until all basic data units in the (N+1)th row of data are written into the buffer memory module. And the invention effectively saves storage resources and raises storage resources unitization ratio. Besides, the invention provides a vertical scaling circuit and terminal.
Description
Technical field
The present invention relates to view data and handle, relate to a kind of data cache method, vertical zooming circuit and terminal particularly.
Background technology
In image processing techniques, utilize SOC chip (SOC (system on a chip)) to realize the processing of view data usually, for example carry out interpolation operation and realize convergent-divergent (dwindle, amplify) function image by the image that camera (Camera) is taken.Image zoom generally is divided into two classes: non real-time image zoom and realtime graphic convergent-divergent, non real-time Zoom method are earlier image to be stored in the outer cache module (Memory) of sheet, view data are read to carry out the interpolation zoom operations again to the SOC chip; The realtime graphic convergent-divergent then is earlier image to be finished zoom operations, scaled images is stored among the outer Memory of sheet again.
Typical realtime graphic convergent-divergent as shown in Figure 1, generally be divided into for two steps: horizontal line convergent-divergent and vertical row convergent-divergent, promptly earlier original image is carried out interpolation to every capable pixel in the horizontal direction, zoom to and require size, to carry out buffer memory through the picturedeep certificate of horizontal scaling again, interpolation is carried out vertically scale in vertical direction, thereby the image that obtains final size is the purpose image.
Particularly, when carrying out vertically scale, existing a kind of implementation processing procedure is as follows: will deposit in the sram cache district by row through the view data of horizontal scaling, the sram cache district is made up of a plurality of SRAM, every group of SRAM deposits the one-row pixels data, the size of every group of SRAM is decided by the data of the every row of input, after depositing two row pixel datas in, read two groups of pixel datas among the SRAM, utilize line scanning mechanism, carry out interpolation calculation by certain interpolation algorithm, for example: amplify 2 times and just come 2 line data of retaking of a year or grade, amplify 3 times and just come retaking of a year or grade 3 times, when continuous two row pixel datas had write the row interpolation of going forward side by side among the two groups of SRAM in front and calculate, the pixel data of the third line just write among the 3rd group of SRAM, like this when the interpolation zoom operations between one or the two row pixel datas is finished, just can carry out the interpolation zoom operations between two triplex rows, and then finish the convergent-divergent of whole sub-picture, the line scanning process as shown in Figure 2.
This implementation can adopt electrodeless convergent-divergent algorithm, does the convergent-divergent of arbitrary proportion within the specific limits, as 1.5 times, 2.3 times or the like.But because what adopt is a kind of mechanism of full line scanning, promptly when doing vertical direction interpolation, just can carry out interpolation operation after need waiting until the whole buffer memorys of pixel data of two row, therefore need a bigger sram cache district, bigger to resource consumption.
Summary of the invention
The embodiment of the invention provides a kind of data cache method, can reduce the taking of storage resources, and improve the utilance of storage resources.
The data cache method that the embodiment of the invention proposes comprises the steps:
After the N line data is stored in cache module, a primitive group in the N+1 line data is write cache module;
After described write operation is finished, from cache module, be written into a primitive group of cache module in the output N+1 line data recently, and the corresponding primitive group of primitive group that is written into cache module in the N line data with this recently;
After described output function is finished, the next primitive group in the N+1 line data is write the shared space of primitive group that has been output in the N line data;
Continue above-mentioned output function and write operation, until the whole primitives in the N+1 line data are write in the cache module.
The embodiment of the invention also provides a kind of vertical zooming circuit, comprises line data buffer and interpolation device, and wherein said line data buffer comprises:
Write interface module, be used to receive the line data of input, and the write address output signal, and export described line data with the form of primitive group, wherein said line data comprises a plurality of primitives, contains a primitive in the described primitive group at least;
Scanning monitor is used for determining the number of times of reading of adjacent two line data;
Cache module, be used to receive and describedly write the primitive group of interface module output and store according to described writing address signal, and read two corresponding primitive groups of number of times output according to what described scanning monitor was determined, described two corresponding primitive groups comprise: a primitive group that is written into cache module recently, corresponding with the described primitive group that is written into cache module recently, as to belong to the lastrow in described adjacent two row primitive group;
Wherein, according to reading after two corresponding primitive groups of number of times output that described scanning monitor is determined, described cache module is according to writing the primitive group that writing address signal that interface module newly receives will newly receive together and deposit the shared space of primitive group that is output in the described lastrow in from described;
Described interpolation device is used for described two corresponding primitive groups of described cache module output are carried out interpolation arithmetic.
The embodiment of the invention also provides a kind of terminal, and described terminal includes image processing module, and described image processing module includes aforementioned vertical zooming circuit.
The method that the embodiment of the invention provides is with after existing partial data is read in the cache module, give the data that newly write with the described shared allocation of space of data that is read out, effectively saved storage resources, and, improved the utilance of storage resources because memory space can be recycled.
Description of drawings
Fig. 1 is an image zoom process schematic diagram in the prior art;
Fig. 2 is line scanning schematic diagram during image zoom in the prior art;
Fig. 3 is the data cache method schematic diagram that the embodiment of the invention provides;
Fig. 4 is the storage node composition of data in the cache module in the embodiment of the invention;
Fig. 5 is the line data buffer structural representation that one embodiment of the invention provides;
Fig. 6 is the line data buffer structural representation that another embodiment of the present invention provides;
Fig. 7 is the line data buffer structural representation that another embodiment of the present invention provides;
Fig. 8 is the vertical zooming circuit structural representation that the embodiment of the invention provides.
Embodiment
The embodiment of the invention can be understood as, when line data is carried out buffer memory, because line data comprises a plurality of primitives, can be after cache module stores N (N 〉=1) line data, a primitive group in the N+1 line data is write cache module, comprise a primitive in the described primitive group at least; From cache module, read a primitive group that is written into cache module in the N+1 line data recently, and corresponding primitive group in the N line data; Next primitive group in the N+1 line data is write the shared space of primitive group that has been read out in the N line data; So carry out, until the whole primitives in the N+1 line data are write in the cache module.
Below in conjunction with accompanying drawing the specific implementation process of the embodiment of the invention is done further introduction.
See also shown in Figure 3ly, Fig. 3 has disclosed the line data caching method that the embodiment of the invention provides, in cache module, stored the N line data after, specifically can comprise the steps:
The N+1 line data is the next line of N line data, and the primitive group comprises a primitive at least.Present embodiment goes for view data and handles, when concrete the application, for example when transfer bus is ahb bus (Advanced High-performance Bus), consider that burst transfer of ahb bus is 16 words (word), size that can elementary cell is set to 16 words, can only comprise a primitive in the primitive group.
When described two the primitive groups of output, it can be a primitive group that is written into cache module in the output N+1 line data recently, and the corresponding primitive group of primitive group that is written into cache module in the N line data with this recently, for example the primitive group that can be saved the earliest in capable for N.
See also Fig. 4, Fig. 4 has disclosed the storage organization of data in the cache module.Only to comprise a primitive in the primitive group is example, equal at 2 o'clock at N, preserve each primitive 2.1, the 2.2......2.K (K 〉=1) of the 2nd line data in the cache module, the up-to-date primitive that is written into is 3.1 in the 3rd line data, the data of this output can be primitive 3.1 so, and and the 3.1 corresponding primitives 2.1 that are arranged in the 2nd row.
To adjacent two row, the output number of times may be once, also may be repeatedly, if the output outdegree for repeatedly, this adjacent two each primitive in capable all will be output repeatedly so.
In conjunction with Fig. 4, can learn after receiving write order, the primitive in the 3rd line data 3.2 is write primitive 2.1 original shared spaces.
Above step 102 to 104 disclosed one constantly read N capable in primitive, and constantly write N+1 capable in the process of primitive.As shown in Figure 4, after last primitive was written into cache module in the 3rd line data, the data of preserving in the cache module were 2.k, 3.1,3.2......3.k, and the 3rd line data all is stored in the cache module.
At this moment, because primitive 2.k also is kept in the cache module, can execution in step 105 further read primitive 2.k and primitive 3.k.
The rest may be inferred, can N+2 is capable, N+3 is capable ... data write in the cache module successively, and constantly read; And when writing the 1st line data, can be directly the whole primitives in the 1st row to be write cache module 202.
Above only made explanation to only comprising a this situation of primitive in the primitive group, also a plurality of primitives can be set flexibly in the primitive group as required in addition, only need to guarantee the shared space of primitive group that N is read out in capable can write N+1 capable in next primitive group get final product, to the those of ordinary skill realization of being not difficult.
The data cache method that present embodiment provides, can be applied in the view data processing scheme, also can be applied to other data cached occasion, particularly receive the inconsistent occasion of data and output data rate, because the embodiment of the invention only needs buffer memory data line and a primitive group, in prior art, need effectively to have saved memory space, improved the utilance of storage resources for line data distributes a plurality of SRAM groups.
See also shown in Figure 5ly, Fig. 5 has disclosed the line data buffer structure that one embodiment of the invention provides.Described line data buffer comprises writes interface module 201, cache module 202 and scanning monitor 203.
Wherein write interface module 201 and be used to receive line data, described line data comprises a plurality of primitives, and export described line data with the form of primitive group, and the write address output signal, a primitive contained in the described primitive group at least;
Cache module 202 is used to receive the described primitive group of writing interface module output and stores according to the writing address signal of writing interface module 201 and providing;
The number of times of reading that cache module 202 is determined according to scanning monitor 203 is exported two corresponding primitive groups, and described two one of corresponding primitive groups belong to the lastrow in described adjacent two row, and for example N is capable; Another belongs to the next line in described adjacent two row, and for example N+1 is capable;
These two corresponding primitive groups can be primitive groups that is written into cache module in the N+1 line data recently, and the corresponding primitive group of primitive group that is written into cache module in the N line data with this recently.
To adjacent two row, the output number of times may be once, also may be repeatedly, if the output outdegree for repeatedly, this adjacent two each primitive in capable all will be output repeatedly so.After the operation of described two the corresponding primitive groups of output was finished, the output function here when being one time, referred to once output at the output number of times,, referred to repeatedly and exported for repeatedly the time at the output number of times.
After output function is finished, described cache module 202 will from described write interface module 201 newly receive the primitive group, promptly N+1 in capable next primitive group deposit the shared space of primitive group that described N is output in capable in according to writing the writing address signal that interface module 201 provides together.
When writing the 1st line data, can be directly the whole primitives in the 1st row to be write cache module 202; After first line data all is written into, progressively write the primitive group in the 2nd line data again.
In the present embodiment, the memory that cache module 202 can utilize dual-port SRAM or other to have the dual-port function is realized.
See also shown in Figure 6ly, Fig. 5 has disclosed the line data buffer structure that another embodiment of the present invention provides.Compare with Fig. 5, cache module 202 is replaced by first buffer unit 2021 and second buffer unit 2022.Wherein first buffer unit 2021 is used to receive the described primitive group of writing interface module 201 outputs and stores according to the writing address signal of writing interface module 201 and providing, and can be single port SRAM or other one-port memory when specifically using; Second buffer unit 2022 is used for storing two corresponding primitive groups of described first buffer unit 2021 outputs, and described two corresponding primitive groups are read number of times output according to what scanning monitor 203 was determined, 1 buffer (buffer) or 2 buffer can be during concrete the application, other and the functionally similar memory of buffer can certainly be selected for use; Scanning monitor 203 is used for determining the number of times of reading of described adjacent two line data; Described two one of corresponding primitive groups belong to the lastrow in adjacent two row, and for example N is capable; Another belongs to the next line in described adjacent two row, and for example N+1 is capable.
Please consult Fig. 4 once more, still only comprising a primitive with a primitive group is example, suppose that the primitive of preserving in first buffer unit 2021 is 2.1,2.2......2.k and 3.1, then in second buffer unit 2022 storage for primitive be 2.1 and 3.1, when second buffer unit 2022 is 1 buffer, the primitive of this buffer storage is 2.1 and 3.1, when second buffer unit 2022 is 2 buffer, one is used to store primitive is 2.1, and another is used to store primitive is 3.1.
Correspondingly, after described two the corresponding primitive groups of second buffer unit, 2021 storages, writing interface module 201 continues to the i.e. next primitive 3.2 of N+1 in capable of the new primitive group of first buffer unit, 2021 outputs, first buffer unit 2021 receives described new primitive group 3.2, and according to the writing address signal that receives together with primitive group 3.2 write N capable in 2.1 groups of shared spaces of primitive.
After the operation of described two the corresponding primitive groups of output is finished in second buffer unit 2022, writing interface module 201 stops to first buffer unit, 2021 dateouts, this moment, first buffer unit 2021 was exported new primitive group 3.2 and corresponding primitive group 2.2, the second buffer units 2022 storage primitive group 3.2 and primitive groups 2.2 thereof to second buffer unit 2022.
See also shown in Figure 7ly, Fig. 7 has disclosed the line data buffer structure that another embodiment of the present invention provides.Compare with Fig. 6, increased Read Controller 204, and selector 205 (MUX).
Describedly write interface module 201 and give first buffer unit 2021 except that being used to export line data and writing address signal, also be further used for exporting control signal and give first buffer unit 2021, wherein said control signal is used to control first buffer unit 2021 and receives data or dateout.
Scanning monitor 203 is used for determining the number of times of reading of described adjacent two line data;
Scanning monitor 203 triggers described Read Controller 204 after described second buffer unit 2022 is finished described two the corresponding primitive groups of output.
Control signal for example can be set when high level 1, be read signal, be used to control first buffer unit, 2021 dateouts, control signal is write signal when low level 0, is used to control first buffer unit 2021 and receives data.Correspondingly, control signal is 0 o'clock, writes interface module write address output signal and data-signal, selector 205 these roads of strobe write address signal, and such first buffer unit 2021 just can receive the line data of writing interface module 201 outputs; Control signal is 1 o'clock, and address signal is read in Read Controller 204 outputs, and driver sweep controller 203, selector 205 gatings are read this road of address signal, such first buffer unit 2021 just can dateout, definite says two corresponding primitive groups, to second buffer unit 2022.
Scanning monitor 203 determine described two corresponding primitive group places adjacent two line data read number of times after, second buffer unit 2022 is exported described two corresponding primitive groups according to the described number of times of reading; After described second buffer unit 2022 was finished described two the corresponding primitive groups of output, scanning monitor 203 triggered described Read Controller 204.
See also shown in Figure 8ly, Fig. 8 has disclosed the vertical zooming circuit structure that the embodiment of the invention provides.Described vertical zooming circuit comprises line data buffer 20 and interpolation device 30.Wherein the same among line data buffer 20 and Fig. 7, comprise and write interface module 201, first buffer unit 2021, second buffer unit 2022, scanning monitor 203, Read Controller 204 and selector 205.
When carrying out vertically scale, compare with embodiment shown in Figure 3, cache module export the capable and N of N+1 capable in after two corresponding primitive groups, interpolation device will carry out vertical interpolation calculation to these two corresponding primitive groups, after primitive all writes cache module in N+1 is capable like this, cache module also exported the capable and N of N+1 capable in most of data, interpolation device has also been finished interpolation calculation to these dateouts accordingly, also need to export last the primitive group in the N+1 line data at last, and last primitive group in the N line data, and these two primitive groups are carried out vertical interpolation arithmetic, so just finish vertical interpolation arithmetic capable to N+1 and that N is capable, thereby realized vertically scale.
Concrete, each module work is as follows:
Write interface module 201 and give first buffer unit 2021 except that being used to export line data and writing address signal, also be further used for exporting control signal and give first buffer unit 2021, wherein said control signal is used to control first buffer unit 2021 and receives data or dateout.
Scanning monitor 203 is used for determining the number of times of reading of described adjacent two line data;
Scanning monitor 203 triggers described Read Controller 204 after described second buffer unit 2022 is finished output function and promptly exported described two corresponding primitive groups.
Described two corresponding primitive groups of 30 pairs second buffer units of interpolation device 2022 output are carried out interpolation operation, obtain the data behind the vertically scale.
The vertical zooming circuit that the embodiment of the invention provides can be applied to the zoom operations of image, belongs to the part of image processing module.The embodiment of the invention also provides a kind of terminal further, and described terminal can be portable electric appts, for example mobile phone, digital camera etc.With the mobile phone is example, and this mobile phone can comprise image processing module, and this image processing module further includes vertical zooming circuit, other structure that this vertical zooming circuit can adopt structure shown in Figure 8 or obtain according to the embodiment of the invention.
The scheme that the embodiment of the invention provides is with after original partial data is read in the cache module, give the data that newly write with the described shared allocation of space of data that is read out, effectively saved storage resources, and, improved the utilance of storage resources because memory space can be recycled.
The scheme that provides of the embodiment of the invention is carried out view data when handling in vertical direction in addition, because the reducing of memory space, can downscaled images process chip area, thereby have wide range of applications, and go for various terminals, for example mobile phone etc.
The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (10)
1, a kind of data cache method is characterized in that, stores the N line data in the cache module, and this method comprises:
A, a primitive group in the N+1 line data is write cache module, comprise a primitive in the described primitive group at least, wherein N is the positive integer more than or equal to 1;
After b, described write operation are finished, from cache module, read a primitive group that is written into cache module in the N+1 line data recently, and the corresponding primitive group of primitive group that is written into cache module in the N line data with this recently;
After c, described output function are finished, the next primitive group in the N+1 line data is write the shared space of primitive group that has been output in the N line data;
D, continuation execution in step b, c are until the whole primitives in the N+1 line data are write in the cache module.
2, the method for claim 1 is characterized in that, described whole primitives in the N+1 line data are write in the cache module also comprises afterwards:
From cache module, read last the primitive group in the N+1 line data, and last primitive group that is not read out as yet in the N line data.
3, a kind of data processing method is characterized in that, stores the N line data in the cache module, and this method comprises:
A, a primitive group in the N+1 line data is write cache module, comprise a primitive in the described primitive group at least;
After the described write operation of b is finished, from cache module, read a primitive group that is written into cache module in the N+1 line data recently, and the corresponding primitive group of primitive group that is written into cache module in the N line data with this recently;
And to the N+1 of described output capable and N capable in two primitive groups carry out vertical interpolation arithmetic;
After c, described output function are finished, the next primitive group in the N+1 line data is write the shared space of primitive group that has been output in the N line data;
D, continuation execution in step b, c are until the whole primitives in the N+1 line data are write in the cache module;
E, last the primitive group from cache module in the output N+1 line data, and last the primitive group in the N line data, and these two primitive groups are carried out vertical interpolation arithmetic.
4, a kind of vertical zooming circuit is characterized in that, comprising: line data buffer and interpolation device,
Wherein said line data buffer comprises:
Write interface module, be used to receive the line data of input, and the write address output signal, and export described line data with the form of primitive group, wherein said line data comprises a plurality of primitives, contains a primitive in the described primitive group at least;
Scanning monitor is used for determining the number of times of reading of adjacent two line data;
Cache module, be used to receive and describedly write the primitive group of interface module output and store according to described writing address signal, and read two corresponding primitive groups of number of times output according to what described scanning monitor was determined, described two corresponding primitive groups comprise: a primitive group that is written into cache module recently, corresponding with the described primitive group that is written into cache module recently, as to belong to the lastrow in described adjacent two row primitive group;
Wherein, according to reading after two corresponding primitive groups of number of times output that described scanning monitor is determined, described cache module is according to writing the primitive group that writing address signal that interface module newly receives will newly receive together and deposit the shared space of primitive group that is output in the described lastrow in from described;
Described interpolation device is used for described two corresponding primitive groups of described cache module output are carried out interpolation arithmetic.
5, vertical zooming circuit as claimed in claim 4 is characterized in that, described cache module is dual-port SRAM.
6, vertical zooming circuit as claimed in claim 4 is characterized in that,
Described cache module specifically comprises:
First buffer unit is used to receive and describedly writes the primitive group of interface module output and store according to described writing address signal;
Second buffer unit is used for storing two corresponding primitive groups that described first buffer unit is exported, and reads two corresponding primitive groups of number of times output to described interpolation device according to what described scanning monitor was determined;
Wherein, after described first buffer unit was exported described two corresponding primitive groups, described first buffer unit was according to writing the primitive group that writing address signal that interface module newly receives will newly receive together and deposit the shared space of primitive group that is output in the described lastrow in from described.
7, vertical zooming circuit as claimed in claim 6 is characterized in that, described first buffer unit is single port SRAM.
8, as claim 6 or 7 described vertical zooming circuits, it is characterized in that,
The described interface module of writing is further used for exporting control signal to described first buffer unit, and wherein said control signal is used to control described first buffer unit and receives data or dateout;
Described line data buffer also comprises:
Read Controller is used for output and reads address signal to first buffer unit, and trigger described scanning monitor when described control signal is controlled the first buffer unit dateout;
Selector is used for selecting to read address signal or writing address signal sends described first buffer unit to according to described control signal;
Described scanning monitor is further used for triggering described Read Controller after described second buffer unit is finished described two the corresponding primitive groups of output.
9, a kind of terminal is characterized in that, includes image processing module, and described image processing module includes vertical zooming circuit, and described vertical zooming circuit comprises:
Write interface module, be used to receive the line data of input, and the write address output signal, and export described line data with the form of primitive group, wherein said line data comprises a plurality of primitives, contains a primitive in the described primitive group at least;
Scanning monitor is used for determining the number of times of reading of adjacent two line data;
Cache module, be used to receive and describedly write the primitive group of interface module output and store according to described writing address signal, and read two corresponding primitive groups of number of times output according to what described scanning monitor was determined, described two corresponding primitive groups comprise: a primitive group that is written into cache module recently, corresponding with the described primitive group that is written into cache module recently, as to belong to the lastrow in described adjacent two row primitive group;
Wherein, according to reading after two corresponding primitive groups of number of times output that described scanning monitor is determined, described cache module is according to writing the primitive group that writing address signal that interface module newly receives will newly receive together and deposit the shared space of primitive group that is output in the described lastrow in from described;
Described interpolation device is used for described two corresponding primitive groups of described cache module output are carried out interpolation arithmetic.
10, terminal as claimed in claim 9 is characterized in that, described terminal is a portable electric appts.
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| CNB2007100739244A CN100571325C (en) | 2007-04-03 | 2007-04-03 | A kind of data cache method, vertical zooming circuit and terminal |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101582238B (en) * | 2009-06-10 | 2010-12-29 | 大连海事大学 | Method for reconstructing parallel data in LED display control system |
| CN102427537A (en) * | 2011-10-17 | 2012-04-25 | 天津天地伟业数码科技有限公司 | Video image space scale transformation system and method thereof |
| WO2019041264A1 (en) * | 2017-08-31 | 2019-03-07 | 深圳市大疆创新科技有限公司 | Image processing apparatus and method, and related circuit |
| CN113810644A (en) * | 2021-11-18 | 2021-12-17 | 南京熊猫电子制造有限公司 | Panel driving system for high-definition video signal processing and conversion |
| CN116233330A (en) * | 2021-12-02 | 2023-06-06 | 京瓷办公信息系统株式会社 | Image processing apparatus and method |
-
2007
- 2007-04-03 CN CNB2007100739244A patent/CN100571325C/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101582238B (en) * | 2009-06-10 | 2010-12-29 | 大连海事大学 | Method for reconstructing parallel data in LED display control system |
| CN102427537A (en) * | 2011-10-17 | 2012-04-25 | 天津天地伟业数码科技有限公司 | Video image space scale transformation system and method thereof |
| WO2019041264A1 (en) * | 2017-08-31 | 2019-03-07 | 深圳市大疆创新科技有限公司 | Image processing apparatus and method, and related circuit |
| CN113810644A (en) * | 2021-11-18 | 2021-12-17 | 南京熊猫电子制造有限公司 | Panel driving system for high-definition video signal processing and conversion |
| CN116233330A (en) * | 2021-12-02 | 2023-06-06 | 京瓷办公信息系统株式会社 | Image processing apparatus and method |
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|---|---|
| CN100571325C (en) | 2009-12-16 |
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