CN114785748B - DMA control system and method for image transmission - Google Patents
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- CN114785748B CN114785748B CN202210700709.7A CN202210700709A CN114785748B CN 114785748 B CN114785748 B CN 114785748B CN 202210700709 A CN202210700709 A CN 202210700709A CN 114785748 B CN114785748 B CN 114785748B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
- H04L49/9015—Buffering arrangements for supporting a linked list
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
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Abstract
The application discloses a DMA control system and method for image transmission. The system comprises: a CPU; the DMA unit is provided with a linked list address register, a pixel register and a data decompression module; the linked list memory is used for storing at least two linked lists, each linked list comprises a plurality of sub-lists, and the information of each sub-list comprises a source address, a destination address and a control word for image transmission; a source image data memory; a display device; a bus; the CPU establishes a linked list and sends a base address of the linked list to a linked list address register; and the DMA unit carries the source image data from the source image data storage according to the linked list, decompresses the source image data through the data decompression module, and sends the decompressed image to the display device for display. The invention records discontinuous addresses through the linked list of the memory, the consumed memory area expense is greatly reduced compared with the register area, and the direct image decompression in the DMA is supported, thereby saving the memory space required by the original image.
Description
Technical Field
The present invention relates to the field of image processing, and more particularly, to a DMA control system and method for image transmission.
Background
The general DMA control system can only carry out data transfer of continuous addresses between the peripheral equipment and the memory, between the peripheral equipment and between the memory and the memory, when discontinuous address transmission or source address and destination address switching is needed, a plurality of sets of register sets are needed to store different address ranges, data lengths and channel configurations, or a CPU is needed to frequently configure the register sets to change the address ranges, the data lengths and the channel configurations. Therefore, either the hardware overhead is increased or the CPU bandwidth is occupied, which is more limited for the application scene needing to transmit the dynamic image.
The DMA control system dedicated to image transfer performs efficient hardware acceleration processing for graphics data transfer, but cannot be used or is difficult to use in a general DMA transfer scenario.
Therefore, there is a need to develop a DMA control system and method for image transfer.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
Disclosure of Invention
The invention provides a DMA control system and method for image transmission, which can record discontinuous addresses through a linked list of an internal memory, greatly reduces the consumed internal memory area cost compared with the register area, supports the direct image decompression in the DMA and saves the internal memory space required by the original image.
In a first aspect, an embodiment of the present disclosure provides a DMA control system for image transfer, including:
the CPU is used for establishing a linked list;
the DMA unit is internally provided with a linked list address register, a plurality of pixel registers and a data decompression module;
the linked list memory is used for storing at least two linked lists, the linked list comprises a plurality of sub-lists, and the information of each sub-list comprises a source address, a destination address and a control word for image transmission;
the source image data memory is used for storing source image data;
display means for displaying the transmitted image;
the bus is used for respectively connecting the CPU, the DMA unit, the linked list memory, the source image data memory and the display device in a communication manner;
the CPU establishes the linked list and sends a base address of the linked list to the linked list address register; and the DMA unit carries the source image data from the source image data storage according to the linked list, decompresses the source image data through the data decompression module, and sends the decompressed image to the display device for display.
Preferably, the DMA unit sequentially acquires the information of the sub-tables in sequence, and then transports the source image data from the source image data storage according to the information of the sub-tables.
Preferably, when the DMA unit transfers source image data from the source image data storage according to the current linked list, the CPU establishes a new linked list and stores the new linked list in the linked list storage.
Preferably, after the DMA unit completes the tasks of all the sub-tables in the current linked list, the DMA unit sends a signal that the current linked list is completed to the CPU, and the CPU sends the base address of the new linked list to the linked list address register.
Preferably, the data decompression module decompresses by:
determining the compression ratio of source data to be transmitted by the current sub-table according to the control word;
when the compression ratio is 1:16, writing 2 pixel data into two pixel registers, and selecting one of the two pixel registers as the pixel data to be actually sent to a screen;
when the compression ratio is 1:8, writing 4 pixel data into 4 pixel registers, and selecting one pixel register as the pixel data to be actually sent to a screen;
when the compression ratio is 1:4, 8 kinds of pixel data are written into 8 pixel registers, and one of the pixel registers is selected as pixel data to be actually sent to the screen.
Preferably, the source image data memory comprises a Flash memory and a QSPIFlash memory.
In a second aspect, an embodiment of the present disclosure provides a DMA control method for image transfer, including:
the method comprises the steps that a CPU establishes a linked list and sends a base address of the linked list to a linked list address register of a DMA unit, wherein the linked list comprises a plurality of sub-tables, and information of each sub-table comprises a source address, a destination address and a control word of image transmission;
the DMA unit carries source image data from a source image data storage according to the linked list;
decompressing through a data decompression module in the DMA unit, and sending the decompressed image to a display device for displaying.
Preferably, the DMA unit sequentially acquires the information of the sub-tables in sequence, and then transports the source image data from the source image data storage according to the information of the sub-tables.
Preferably, the CPU establishes a new linked list and stores the new linked list to the linked list memory while the DMA unit transfers source image data from the source image data memory according to the current linked list.
Preferably, after the DMA unit completes the tasks of all the sub-tables in the current linked list, the DMA unit sends a signal that the current linked list is completed to the CPU, and the CPU sends the base address of the new linked list to the linked list address register.
Preferably, the data decompression module decompresses by:
determining the compression ratio of source data to be transmitted by the current sub-table according to the control word;
when the compression ratio is 1:16, writing 2 pixel data into two pixel registers, and selecting one of the two pixel registers as the pixel data to be actually sent to a screen;
when the compression ratio is 1:8, writing 4 pixel data into 4 pixel registers, and selecting one pixel register as the pixel data to be actually sent to a screen;
when the compression ratio is 1:4, 8 kinds of pixel data are written into 8 pixel registers, and one of the pixel registers is selected as pixel data to be actually sent to the screen.
The method and apparatus of the present invention have other features and advantages which will be apparent from or are set forth in detail in the accompanying drawings and the following detailed description, which are incorporated herein, and which together serve to explain certain principles of the invention.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent by describing in more detail exemplary embodiments thereof with reference to the attached drawings, in which like reference numerals generally represent like parts.
Fig. 1 shows a schematic diagram of a DMA control system for image transfer according to an embodiment of the present invention.
Fig. 2 shows a flow chart of the steps of a DMA control method for image transfer according to the present invention.
Detailed Description
Preferred embodiments of the present invention will be described in more detail below. While the following describes preferred embodiments of the present invention, it should be understood that the present invention may be embodied in various forms and should not be limited by the embodiments set forth herein.
To facilitate understanding of the aspects of the embodiments of the present invention and their effects, two specific application examples are given below. It will be understood by those skilled in the art that this example is merely for the purpose of facilitating an understanding of the present invention and that any specific details thereof are not intended to limit the invention in any way.
Example 1
A DMA control system for image transfer, comprising:
CPU, is used for setting up the linked list;
the DMA unit is internally provided with a linked list address register, a plurality of pixel registers and a data decompression module;
the linked list memory is used for storing at least two linked lists, each linked list comprises a plurality of sub-lists, and the information of each sub-list comprises a source address, a destination address and a control word for image transmission;
the source image data memory is used for storing source image data;
display means for displaying the transmitted image;
the bus is used for respectively connecting the CPU, the DMA unit, the linked list memory, the source image data memory and the display device in a communication way;
the CPU establishes a linked list and sends a base address of the linked list to a linked list address register; and the DMA unit carries the source image data from the source image data storage according to the linked list, decompresses the data through the data decompression module, and sends the decompressed image to the display device for display.
In one example, the DMA unit sequentially obtains the information of the sub-tables in order, and then transports the source image data from the source image data storage according to the information of the sub-tables.
In one example, the CPU builds and saves a new linked list to the linked list memory while the DMA unit is transferring source image data from the source image data memory according to the current linked list.
In one example, after the DMA unit completes all sub-table tasks in the current linked list, it sends a signal that the current linked list is completed to the CPU, and the CPU sends the base address of the new linked list to the linked list address register.
In one example, the data decompression module decompresses by:
determining the compression ratio of source data to be transmitted by the current sub-table according to the control word;
when the compression ratio is 1:16, writing 2 pixel data into two pixel registers, and selecting one of the two pixel registers as the pixel data to be actually sent to a screen;
when the compression ratio is 1:8, writing 4 pixel data into 4 pixel registers, and selecting one pixel register as the pixel data to be actually sent to a screen;
when the compression ratio is 1:4, 8 kinds of pixel data are written into 8 pixel registers, and one of the pixel registers is selected as pixel data to be actually sent to the screen.
In one example, the source image data memory includes Flash memory and QSPIFlash memory.
Fig. 1 shows a schematic diagram of a DMA control system for image transfer according to an embodiment of the present invention.
Specifically, the architecture of the DMA image transfer system is as shown in fig. 1, and the system includes an M0 CPU core as a central processing unit. The memory comprises an sram interface, a Flash interface, a QSPI interface, an off-chip QSPI Flash interface and various peripherals such as an SPI interface. The Sram stores a linked list, and each sub-table in the linked list specifies a source address, a destination address and a control word of each batch of transmission, so that the source address and the destination address in each sub-table are independent, and discontinuous multi-block data transmission can be realized by setting different address spaces of each sub-table. The DMA sequentially reads a source address, a destination address and a control word from each sub-table, and according to the information, data can be directly read from the QSPI, the Flash and the SRAM and written into the SPI to be sent to an external display module. A data decompression module is arranged in the DMA, so that original compressed image data can be decompressed and then sent to a display, and the data storage space is saved.
The linked lists are stored in the SRAM, a user can store one or more linked lists, and ping-pong operation can be realized by storing at most two linked lists to meet most application requirements. The CPU writes the BASE address of the linked LIST to be serviced to a register called LIST _ BASE _ POINTER. The basic elements of a linked list are sub-tables, and a linked list may contain one or more sub-tables as long as the capacity of the SRAM allows. The structure of one sub-table is shown in table 1.
TABLE 1
The format of the control words in table 1 is shown in table 2.
TABLE 2
The CPU needs to write the start address of the linked LIST to the register LIST BASE POINTER. After the DMAEN is enabled in the mode, the DMA reads the content of the first sub-table of the linked LIST according to the value of LIST _ BASE _ POINTER by the SRAM, reads the content of the second sub-table after the DMA transmission number specified by the first sub-table is executed, completes the DMA transmission number specified by the second sub-table, and so on, and sequentially completes the DMA requests of all the sub-tables. Until the last sub-table is executed (which can be judged according to the end mark of the chain table of the CFG configuration word), the DMA reads the first sub-table content of the chain table again according to the value of LIST _ BASE _ POINTER, and a new cycle is started.
The user can open up two linked list spaces in SRAM, linked list 0 and linked list 1, and the two linked lists can contain any number of sub-lists.
In the process of executing the linked LIST 0, the CPU may update the content of the linked LIST 1, or may change LIST _ BASE _ POINTER to point to a new linked LIST 1 or continue to point to the linked LIST 0. Note that when the linked LIST 0 is executed, the linked LIST 0 cannot be updated, and the LIST _ BASE _ POINTER needs to be updated after the linked LIST 0 has been started to be executed, otherwise, the result is unpredictable, and whether the linked LIST 0 has been started to be executed can be determined by judging that BUSY is 1. After the linked list 0 is executed, a traversal completion interrupt flag is generated, and DMAEN enables automatic closing. If DMA transfer is to continue, DMAEN is turned on again, DMA reads the first sub-table content of the linked LIST again according to the value of LIST _ BASE _ POINTER, and a new round of circulation is started. The same applies to link 1.
It is also possible to update linked LIST 0 or 1 when DMAEN is enabled off, and to update LIST BASE POINTER. DMAEN enable may be written to 0 to terminate the executing linked list.
The control word of each sub-table has a bit field indicating the request mode of the sub-table, and if the request mode of the control word is configured to be the software request mode, the DMA continuously completes the transmission according to the number specified by the data transmission quantity bit field without external request; if the request mode of the control word is configured as a hardware request, the peripheral hardware request needing to be enabled (the hardware request source of the system is generally from an SPIctrl module) carries one data (8 bits, 16 bits or 32 bits) once comes, the DMA can feed back an ACK response when receiving the hardware request REQ once, the peripheral pulls down the hardware request REQ after receiving the ACK, the DMA immediately pulls down the ACK when seeing that the REQ of the peripheral is pulled down, and thus, one-time handshake is completed, and the DMA also simultaneously transmits one data from a source address to a destination. After waiting for the next REQ pending, the DMA and the peripheral continue with the next handshake and the next DMA transfer. Until the number specified in the data transfer amount bit field is transferred.
And each sub-table also has enablement of sub-table transfer completion and sub-table transfer error, and can generate corresponding flag bits and interrupts. But all the sub-tables share a completion flag register and an error flag register, so the DMA has a sub-table count register (LIST _ UNIT _ CNT) to indicate that the current flag belongs to the second sub-table, and the sub-table count register automatically adds 1 when each sub-table is completed until the sub-table count register is clear 0 after DMAEN is started after the linked LIST is completely completed.
When one linked list is completed, a linked list completion flag is generated, and if the linked list completion interrupt is enabled, the interrupt is also generated. The user may use the flag or interrupt to determine whether a linked list execution is complete.
Except that the linked list structure is used for realizing image transmission, a data decompression module in the DMA is used for decompressing data in the memory and then sending the data out through a DMA write bus, so that the storage space of image data can be saved. The control word bit field bit12:11 of each sub-table determines the compression ratio of the source data to be transmitted by the current sub-table, and the formats of the source data are different according to different compression ratios. Taking 8-bit source data as an example, similarly, 16 bits are composed of 2 8 bits below, and 32 bits are composed of 4 8 bits below.
When the compression ratio is 1:16, the source data of 1bit corresponds to one pixel point; when the compression ratio is 1:8, the source data of 2 bits corresponds to a pixel point; when the compression ratio is 1:4, the source data of 4 bits corresponds to one pixel point. When source data is manufactured, it is necessary to closely arrange pixel points in a storage medium (Flash, qspifar, SRAM, or the like).
1bit source data can correspond to 2 kinds of 16-bit pixel data; 2-bit source data can correspond to 4 kinds of 16-bit pixel data; the 4-bit source data may correspond to 8 types of 16-bit pixel data (since bit4 is a reserved bit, only the lower 3 bits are valid). Therefore, when the compression ratio is 1:16, 2 pixel data are required to be written into two 16-bit pixel registers in advance, and one pixel register is selected as the pixel data to be actually sent to a screen according to the content of each 1-bit source data; when the compression ratio is 1:8, 4 pixel data are required to be written into 4 pixel 16-bit registers in advance, and one pixel register is selected as the pixel data actually sent to a screen according to the content of each 2-bit source data; when the compression ratio is 1:4, 8 kinds of pixel data need to be written into 8 16-bit pixel registers in advance, and one pixel register is selected as the pixel data to be actually sent to the screen according to the content of every 4 bits of source data.
The bit number of the pixel data is 16 bits, and may be defined as other bit widths according to the requirement.
The decoded data needs to be configured to a state machine according to the source and the destination, and the state machine sends the decoded data to a destination address through a bus in a plurality of cycles. Taking the data width of the destination address as 16 bits and the pixel data width as 16 bits as an example, each time 8-bit data is read from the source address, when the compression ratio is 1:16, 8 cycles are needed to decompress 8bit source data and then send the data to a destination address; when the compression ratio is 1: when 8, 8bit source data is decompressed and sent to a destination address in 4 periods; when the compression ratio is 1:4, 2 periods are needed to decompress 8-bit source data and then send the 8-bit source data to a destination address.
The method can also be expanded to support that each DMA channel corresponds to a linked list, a plurality of channels simultaneously initiate DMA requests, the DMA controller arbitrates the plurality of DMA requests, the DMA firstly executes the first sub-list in the linked list corresponding to the channel with the highest priority, arbitrates the plurality of DMA requests again after the sub-list is transmitted, judges the channel with the highest priority again and transmits the first sub-list of the rest sub-lists in the linked list, and so on until the transmission of all the linked lists is completed or no DMA request is initiated. And before each arbitration, the pointer of the last executed channel sub-table is saved, so that after the channel obtains the priority again, the DMA can continuously carry out the transportation from the position of the remaining sub-table of the linked list corresponding to the channel.
Example 2
Fig. 2 shows a flow chart of the steps of a DMA control method for image transfer according to the present invention.
As shown in fig. 2, the DMA control method for image transfer includes:
102, carrying source image data from a source image data storage by a DMA unit according to a linked list;
and 103, decompressing by a data decompression module in the DMA unit, and sending the decompressed image to a display device for display.
In one example, the DMA unit sequentially obtains the information of the sub-tables in order, and then transports the source image data from the source image data storage according to the information of the sub-tables.
In one example, the CPU builds and saves a new linked list to the linked list memory while the DMA unit is transferring source image data from the source image data memory according to the current linked list.
In one example, after the DMA unit completes the tasks of all the sub-tables in the current linked list, the CPU sends a signal that the current linked list is completed to the CPU, and the CPU sends the base address of the new linked list to the linked list address register.
In one example, the data decompression module decompresses by:
determining the compression ratio of source data to be transmitted by the current sub-table according to the control word;
when the compression ratio is 1:16, writing 2 pixel data into two pixel registers, and selecting one pixel register as the pixel data to be actually sent to a screen;
when the compression ratio is 1:8, writing 4 pixel data into 4 pixel registers, and selecting one pixel register as the pixel data to be actually sent to a screen;
when the compression ratio is 1:4, 8 kinds of pixel data are written into 8 pixel registers, and one of the pixel registers is selected as pixel data to be actually sent to the screen.
It will be appreciated by persons skilled in the art that the above description of embodiments of the invention is for the purpose of illustrating the benefits of embodiments of the invention only, and is not intended to limit embodiments of the invention to any examples given.
While embodiments of the present invention have been described above, the above description is illustrative, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments.
Claims (8)
1. A DMA control system for image transfer, comprising:
CPU, is used for setting up the linked list;
the DMA unit is internally provided with a linked list address register, a plurality of pixel registers and a data decompression module;
the linked list memory is used for storing at least two linked lists, the linked list comprises a plurality of sub-lists, and the information of each sub-list comprises a source address, a destination address and a control word for image transmission;
the source image data memory is used for storing source image data;
display means for displaying the transmitted image;
the bus is used for respectively connecting the CPU, the DMA unit, the linked list memory, the source image data memory and the display device in a communication manner;
the CPU establishes the linked list and sends a base address of the linked list to the linked list address register; the DMA unit carries source image data from the source image data storage according to the linked list, decompresses the source image data through the data decompression module, and sends the decompressed image to the display device for display;
the DMA unit sequentially acquires the information of the sub-tables according to the sequence, and then carries source image data from the source image data storage according to the information of the sub-tables;
the CPU writes the initial address of the linked LIST into a register LIST _ BASE _ POINTER, after the DMA EN is enabled, the DMA reads the content of a first sub-table of the linked LIST from the SRAM according to the value of the LIST _ BASE _ POINTER, reads the content of a second sub-table after the DMA transmission number specified by the first sub-table is executed, completes the DMA transmission number specified by the second sub-table, and so on, completes the DMA requests of all the sub-tables in sequence until the last sub-table is executed, and then the DMA reads the content of the first sub-table of the linked LIST from the SRAM again according to the value of the LIST _ BASE _ POINTER and starts a new cycle.
2. The DMA control system for image transfer according to claim 1, wherein the CPU creates and saves a new linked list to the linked list memory while the DMA unit transfers source image data from the source image data memory according to a current linked list.
3. The DMA control system for image transfer according to claim 2, wherein the DMA unit sends a signal that the current linked list is completed to the CPU after completing the tasks of all the sub-tables in the current linked list, and the CPU sends the base address of the new linked list to the linked list address register.
4. The DMA control system for image transfer according to claim 1, wherein the data decompression module decompresses by:
determining the compression ratio of source data to be transmitted by the current sub-table according to the control word;
when the compression ratio is 1:16, writing 2 pixel data into two pixel registers, and selecting one of the two pixel registers as the pixel data to be actually sent to a screen;
when the compression ratio is 1:8, writing 4 pixel data into 4 pixel registers, and selecting one pixel register as the pixel data to be actually sent to a screen;
when the compression ratio is 1:4, 8 kinds of pixel data are written into 8 pixel registers, and one of the pixel registers is selected as pixel data to be actually sent to the screen.
5. The DMA control system for image transfer according to claim 1, wherein the source image data memory comprises a Flash memory and a QSPI Flash memory.
6. A DMA control method for image transfer using the DMA control system for image transfer of any one of claims 1 to 5, characterized by comprising:
the method comprises the steps that a CPU establishes a linked list and sends a base address of the linked list to a linked list address register of a DMA unit, wherein the linked list comprises a plurality of sub-tables, and information of each sub-table comprises a source address, a destination address and a control word of image transmission;
the DMA unit carries source image data from a source image data storage according to the linked list;
decompressing through a data decompression module in the DMA unit, and sending the decompressed image to a display device for display;
and the DMA unit sequentially acquires the information of the sub-tables according to the sequence, and then carries the source image data from the source image data storage according to the information of the sub-tables.
7. The DMA control method for image transfer according to claim 6, wherein the CPU creates a new linked list and saves it to the linked list memory while the DMA unit transfers source image data from the source image data memory according to the current linked list.
8. The DMA control method for image transfer according to claim 7, wherein, after the DMA unit completes tasks of all sub-tables in the current linked list, the DMA unit sends a signal that the current linked list is completed to the CPU, and the CPU sends the base address of the new linked list to the linked list address register.
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