CN113660493A - Real-time multi-channel H.265 video real-time decompression display method - Google Patents
Real-time multi-channel H.265 video real-time decompression display method Download PDFInfo
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- CN113660493A CN113660493A CN202110948570.3A CN202110948570A CN113660493A CN 113660493 A CN113660493 A CN 113660493A CN 202110948570 A CN202110948570 A CN 202110948570A CN 113660493 A CN113660493 A CN 113660493A
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- 238000000034 method Methods 0.000 title claims abstract description 26
- 230000006837 decompression Effects 0.000 title claims abstract description 22
- 238000012545 processing Methods 0.000 claims abstract description 22
- 230000005540 biological transmission Effects 0.000 claims description 12
- 238000012546 transfer Methods 0.000 claims description 7
- 239000003999 initiator Substances 0.000 claims description 3
- 230000002093 peripheral effect Effects 0.000 claims description 2
- 238000013461 design Methods 0.000 description 3
- 230000000977 initiatory effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/40—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using video transcoding, i.e. partial or full decoding of a coded input stream followed by re-encoding of the decoded output stream
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L65/00—Network arrangements, protocols or services for supporting real-time applications in data packet communication
- H04L65/60—Network streaming of media packets
- H04L65/75—Media network packet handling
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L65/00—Network arrangements, protocols or services for supporting real-time applications in data packet communication
- H04L65/80—Responding to QoS
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/44—Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
Abstract
The invention relates to a real-time multi-channel H.265 video real-time decompression display method, belonging to the field of image processing. The invention adopts Haisi Hi3559x series media processing chips to receive and decode H.265 video code stream; running a VxWorks operating system on an Intel I7 processor to finish video transcoding and display output; data are transmitted between the Haisi Hi3559x chip and the Intel I7 processor through a PCIe bus DMA channel. When the invention processes multi-path H.265 code stream, the whole receiver can receive the compressed video from the Ethernet to decompress and transcode to complete the video display output, the single-path time does not exceed 30ms, and the processing efficiency of the receiver is optimized. The invention can effectively reduce the pressure of single chip work when multi-path video streams are input, and improve the efficiency of video decoding, transcoding and displaying, thereby reducing the processing time of the link.
Description
Technical Field
The invention belongs to the field of image processing, and particularly relates to a real-time multi-channel H.265 video real-time decompression display method.
Background
The H.265 standard is developed on the basis of the H.264 standard, and compared with the H.264 standard, the H.265 standard improves the coding efficiency, reduces the code stream, reduces the channel delay, improves the error recovery capability and reduces the algorithm complexity.
With the rapid development of the digital video application industry chain, video applications are continuously developing in the directions of high definition, high frame rate, high compression rate, high real-time performance and the like. Under the trend, as a new generation video coding standard, h.265 is more and more widely applied, and the related fields include IPTV, security monitoring, streaming media screen projection, video display terminals, and the like.
In practical application, when the multi-channel H.265 video code stream is processed, most of the processing delay of a receiver is more than 100ms, and the technology is limited to play in scenes with high real-time requirements, and the sensory experience of the user is also influenced.
Disclosure of Invention
Technical problem to be solved
The technical problem to be solved by the invention is how to provide a real-time multi-channel H.265 video real-time decompression display method, so as to solve the problem that an H.265 video receiver is large in time delay when processing multi-channel code streams.
(II) technical scheme
In order to solve the above technical problem, the present invention provides a real-time decompression display method for real-time multiple h.265 videos, which comprises the following steps:
s1, adopting Haisi Hi3559x series media processing chips to receive and decode H.265 video code stream;
s2, operating a VxWorks operating system on the Intel I7 processor to complete video transcoding and display output;
and data are transmitted among the S3 chip, the Haisi Hi3559x chip and the Intel I7 processor through a PCIe bus DMA channel.
Furthermore, the haisi Hi3559x chip and the Intel I7 processor are connected to the same PCIe bus in a hanging manner through a bridge, and after the system is powered on, the host bridge completes enumeration and configuration of devices on the bus, so that the two chips realize establishment of a transmission channel.
Further, the Haisi Hi3559x chip operates in rc mode as a PCIe controller, creates DMA channels and initiates each DMA transfer and notifies the Intel I7 processor in the form of an interrupt.
Further, the step S1 specifically includes:
s11, running a Linux operating system on the Haisi Hi3559x chip;
s12, compiling several functional software modules, including creating a DMA channel, creating a network Socket, receiving an H.265 video code stream, distributing the H.265 video code stream to several decoders of Hi3559x, inquiring YUV format images output by the decoders and writing the YUV format images into the DMA; the PCIe interrupt Notification EP is initiated.
Further, the decoder is a decoder of the Haisi Hi3559x chip.
Further, the step S2 specifically includes: the VxWorks operating system loads PCIe drivers and works in an ep mode, receives YUV code streams decoded by a Haisia Hi3559x chip, converts the YUV code streams into code streams with required formats, and writes the code streams into a freebuffer respectively according to channel information and drives and displays the code streams.
Further, the code stream of the required format is an RGB code stream.
Further, the step S2 specifically includes the following steps:
s21, loading a PCIe (peripheral component interface express) drive by the VxWorks operating system, and initializing the PCIe drive to be ep;
s22, creating a PCIe interrupt service program and receiving and processing an interrupt;
s23, compiling or transplanting a YUV transcoding module;
and S24, adding a display driving module and supporting video multi-path output.
Further, the step S3 specifically includes:
s31, creating and initializing a DMA controller by using Haisi Hi3559x chips, wherein the Haisi Hi3559x chips are used as an initiator of DMA transmission;
and S32, appointing a DMA channel transmission protocol.
Further, the DMA channel transfer protocol provides for a write data address, a write data length, a read data address, a read data length, and a flag bit.
(III) advantageous effects
The invention provides a real-time multi-channel H.265 video real-time decompression display method, which can ensure that the whole receiver receives the compressed video from the Ethernet when processing multi-channel (not more than 4 channels) H.265 code streams, and the single-channel time is not more than 30ms when the decompression transcoding completes the video display output, thereby optimizing the processing efficiency of the receiver. The invention can effectively reduce the pressure of single chip work when multi-path video streams are input, and improve the efficiency of video decoding, transcoding and displaying, thereby reducing the processing time of the link.
Drawings
FIG. 1 is a schematic diagram of a real-time multi-channel H.265 video real-time decompression display method according to the present invention.
Detailed Description
In order to make the objects, contents and advantages of the present invention clearer, the following detailed description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples.
The invention belongs to a real-time decompression display method for real-time multi-channel H.265 videos. The H.265 code stream receiver is the last link of the whole video transmission link, reflects the quality characteristic of a code stream channel, determines the quality of video transmission quality according to the quality of the processing of the link, and directly influences the visual perception of people. The invention provides a solution of a whole set of H.265 video set code stream receiver, aiming at improving the efficiency of decoding, transcoding and display output, reducing time delay and controlling the processing time of the whole receiver within 30 ms.
The invention aims to solve the problem that an H.265 video receiver is large in time delay of processing multi-path code streams based on the current mainstream Ethernet interface.
In order to achieve the purpose, the invention adopts the following technical measures:
s1, adopting Haisi Hi3559x series media processing chips to receive and decode H.265 video code stream;
s2, operating a VxWorks operating system on the Intel I7 low-power-consumption processor to complete video transcoding and display output;
and data are transmitted among the S3 chip, the Haisi Hi3559x chip and the Intel I7 low-power-consumption processor through a PCIe bus DMA channel.
In combination with the illustration, in order to implement the receiver design for decoding and displaying the low-latency multi-channel h.265 video code stream, we complete the scheme design to meet the requirements by introducing the techniques of hardware decompression, DMA transmission, transcoding output of a real-time operating system, and the like, and the contents of the present invention are further described below.
1. Video receiving and decoding by adopting Haisi Hi3559x series media processing chips
The Haisi Hi3559x chip and the Intel I7 processor are hung on the same PCIe bus through a bridge chip, and after the system is powered on, the host bridge completes enumeration and configuration of devices on the bus, so that the two chips realize establishment of a transmission channel.
The Haisi Hi3559x chip operates in rc mode, as a PCIe controller, is responsible for creating DMA channels and initiating each DMA transfer, and notifies the Intel I7 processor in the form of an interrupt. The following work needs to be done:
s11, running a Linux operating system on the Haisi Hi3559x chip;
s12, compiling several functional software modules, including creating a DMA channel, creating a network Socket, receiving an H.265 video code stream, distributing the H.265 video code stream to several decoders of Hi3559x, inquiring YUV format images output by the decoders and writing the YUV format images into the DMA; initiating a PCIe interrupt notification EP;
the decoding work is completed by a decoder carried by Haisi Hi3559x chip, and software is used for managing and scheduling the whole process.
2. The VxWorks operating system is operated on the Intel I7 low-power-consumption processor to complete video transcoding and display output
The VxWorks operating system is an embedded real-time multi-task operating system, and compared with other embedded operating systems, the VxWorks operating system has the advantages that input can be responded in real time, task output can be controlled accurately, and operating time can be effectively guaranteed.
The approximate workflow of the Intel I7 low power processor is as follows: the VxWorks operating system loads PCIe drivers and works in an ep mode, the running software receives YUV code streams decoded by a Haisia Hi3559x chip and converts the YUV code streams into code streams in a required format (RGB), and the code streams are written into a freebuffer and driven to display according to channel information, and the method specifically comprises the following work:
s21, the VxWorks operating system loads PCIe drivers and initializes the PCIe drivers to ep.
S22, creating PCIe interrupt service program and receiving the processing interrupt.
And S23, writing (transplanting) a YUV transcoding module.
And S24, adding a display driving module and supporting video multi-path output.
3. DMA data transmission between Haisi Hi3559x chip and Intel I7 low-power consumption processor through PCIe bus
This process is mainly completed by Haisi Hi3559x chip, which mainly includes the following operations:
s31, Haisi Hi3559x chip creates and initializes a DMA controller, Haisi Hi3559x chip as the initiator of DMA transfer
S32, appointing a DMA channel transmission protocol, specifying items such as a starting address, a data length and the like, wherein the specific protocol is shown as the following table:
note: n is the channel number, starting with 0.
By utilizing the technical scheme, the H.265 multi-channel video code stream receiver completed according to the operation method can effectively reduce the pressure of single chip work when multi-channel video streams are input, and improve the efficiency of video decoding, transcoding and displaying, thereby reducing the processing time of the link.
The key points of the invention are as follows:
a system design scheme for real-time multi-path H.265 video real-time decompression display is implemented by the following processes:
(1) h.265 video code stream is received from a network by adopting Haisi Hi3559x series media processing chips for decoding;
(2) haisi Hi3559x runs software to create PCIe DMA channels and initiate DMA transfers;
(3) running a VxWorks operating system on an Intel I7 low-power-consumption processor, acquiring a video stream from a DMA channel to complete transcoding and display output
Further, H.265 video decoding and transcoding display are accomplished using two CPUs.
Further, decoding is completed by using a Haisi Hi3559x chip with a decoder.
And further, the solved YUV video is sent to a transcoding display CPU in a PCIe DMA mode.
And further, acquiring a video stream from the DMA channel to complete transcoding and display output, wherein an Intel low-power-consumption processor is adopted for transcoding display, and a VxWorks real-time operating system is operated.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A method for real-time decompression display of multi-channel H.265 video in real time is characterized by comprising the following steps:
s1, adopting Haisi Hi3559x series media processing chips to receive and decode H.265 video code stream;
s2, operating a VxWorks operating system on the Intel I7 processor to complete video transcoding and display output;
and data are transmitted among the S3 chip, the Haisi Hi3559x chip and the Intel I7 processor through a PCIe bus DMA channel.
2. The method for real-time decompression and display of multiple h.265 videos in real-time according to claim 1, wherein the haisi Hi3559x chip and the Intel I7 processor are connected to a PCIe bus through a bridge, and after the system is powered on, the host bridge completes enumeration and configuration of devices on the bus, so that the two chips implement establishment of the transmission channel.
3. The method for real-time multi-channel H.265 video real-time decompression display according to claim 2, wherein the Haisi Hi3559x chip operating in rc mode, as PCIe controller, creates DMA channels and initiates each DMA transfer and notifies the Intel I7 processor in interrupt form.
4. The method for real-time decompression and display of multi-channel h.265 video in real time according to claim 3, wherein the step S1 specifically comprises:
s11, running a Linux operating system on the Haisi Hi3559x chip;
s12, compiling several functional software modules, including creating a DMA channel, creating a network Socket, receiving an H.265 video code stream, distributing the H.265 video code stream to several decoders of Hi3559x, inquiring YUV format images output by the decoders and writing the YUV format images into the DMA; the PCIe interrupt Notification EP is initiated.
5. The method for real-time decompression and display of multi-channel H.265 video according to claim 4, wherein the decoder is a Haisi Hi3559x chip-owned decoder.
6. The method for real-time decompression and display of multi-channel h.265 video in real time according to claim 4, wherein the step S2 specifically comprises: the VxWorks operating system loads PCIe drivers and works in an ep mode, receives YUV code streams decoded by a Haisia Hi3559x chip, converts the YUV code streams into code streams with required formats, and writes the code streams into a freebuffer respectively according to channel information and drives and displays the code streams.
7. The method for real-time decompression and display of multi-channel H.265 video in real-time according to claim 6, wherein the code stream of the desired format is an RGB code stream.
8. The method for real-time decompression and display of multi-channel H.265 video in real time according to claim 4, wherein the step S2 comprises the following steps:
s21, loading a PCIe (peripheral component interface express) drive by the VxWorks operating system, and initializing the PCIe drive to be ep;
s22, creating a PCIe interrupt service program and receiving and processing an interrupt;
s23, compiling or transplanting a YUV transcoding module;
and S24, adding a display driving module and supporting video multi-path output.
9. The method for real-time decompression and display of multi-channel h.265 video according to any one of claims 6 to 8, wherein the step S3 specifically comprises:
s31, creating and initializing a DMA controller by using Haisi Hi3559x chips, wherein the Haisi Hi3559x chips are used as an initiator of DMA transmission;
and S32, appointing a DMA channel transmission protocol.
10. The method for real-time decompression display of multi-channel h.265 video in real-time as claimed in claim 9 wherein said DMA channel transfer protocol specifies a write data address, a write data length, a read data address, a read data length and flag bits.
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| CN114785748A (en) * | 2022-06-21 | 2022-07-22 | 苏州领慧立芯科技有限公司 | DMA control system and method for image transmission |
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