CN108804356A - Data transmission device and method - Google Patents
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- CN108804356A CN108804356A CN201711177552.XA CN201711177552A CN108804356A CN 108804356 A CN108804356 A CN 108804356A CN 201711177552 A CN201711177552 A CN 201711177552A CN 108804356 A CN108804356 A CN 108804356A
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- 230000005540 biological transmission Effects 0.000 title claims abstract description 79
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- 230000015654 memory Effects 0.000 claims abstract description 143
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- 239000000872 buffer Substances 0.000 claims description 17
- 238000006243 chemical reaction Methods 0.000 claims description 14
- 230000008569 process Effects 0.000 claims description 7
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- 238000013501 data transformation Methods 0.000 claims description 4
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- 238000013507 mapping Methods 0.000 claims description 4
- 238000013500 data storage Methods 0.000 claims description 3
- 238000007667 floating Methods 0.000 claims description 2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
- G06F13/282—Cycle stealing DMA
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
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Abstract
Present disclose provides a kind of data transmission device and methods, wherein the device includes：Register module and direct memory access control module.Although existing simple one-dimensional direct memory access instruction is widely used, use bigger is then two-dimentional direct memory access instruction, especially in the applications such as image, video.By the device and method of the disclosure, can solve the problems, such as to lack when 2-D data transmission efficiency existing in the prior art is low, multi-group data alternately transmits excessive.
Description
Technical field
The present invention relates to computer science and technology field more particularly to a kind of data transmission device and methods.
Background technology
Direct memory access (Direct Memory Access, DMA) is a kind of internal storage access skill in computer science
Art.It allows certain hardware subsystems (external memory) independently direct read/write Installed System Memory, is handled without CPU interventions.?
Under the processor burden of equal extent, DMA is a kind of quick data mode.Sometimes, data in addition to contact processor and
Except between external memory, it is also necessary to be shifted between multiple memory spaces.We are not intended to allow processor in such case
Under be also busy with data copy, and DMA can afford such work, reduce the occupancy of system resource.In addition, the biography of DMA
It send ability to be not always used for mobile data, can be used for be stored in sending code to be run in advance in external memory
Enter memory, accelerates execution efficiency.
Dma controller, which needs to instruct, to be supported, the multiple-task of processor arrangement could be correctly executed.For any kind of
DMA transfer is required for the size of regulation source address, destination address and data to be transmitted.Such affairs represent
The transmission of simple one-dimensional (" 1D ") unified " span " (unity stride).But, although 1D DMA have obtained widely answering
With, but that use bigger is then two dimension (2D) DMA, especially in the applications such as image, video.2DDMA can simply understand
For a nested cycle, that is, the row and column of a matrix is operated respectively, is finally completed traversal, each layer of cycle is all suitable
In a 1D DMA.
And more complicated DMA device often simultaneously be connected with multiple external memorys, in a period of time CPU need replace from
Multi-group data is obtained in these external memorys, these data switch frequently according to required by task, but are to connect again in same group
Continuous.At this moment DMA device needs correct identification dependent instruction, it is ensured that the caching with group data is hit as far as possible, not by other groups
Data transmission influence.
Invention content
A kind of data transmission device provided in an embodiment of the present invention and method, under the application scenarios that image, video are handled
The efficiency and standardized degree for greatly improving data transmission compensate for the I/O short slabs of Data-intensive computing task.
In a first aspect, the embodiment of the present application provides a kind of data transmission device, including：
Register module, for storing source address, the 2-D data that 2-D data stores in source memory in mesh
Memory in the destination address that stores and parameters such as data volume of transmission 2-D data every time；
DMA control modules, for receiving DMA command；
The DMA control modules are additionally operable to, according to the DMA command, obtain out from the register module to be transmitted
The destination address of the source address of 2-D data and 2-D data to be transmitted；
The DMA control modules are additionally operable to the source address according to the 2-D data to be transmitted from the source memory
The 2-D data to be transmitted is obtained, and the 2-D data to be transmitted is transmitted to destination described in the purpose memory
The corresponding memory space in location.
Wherein, the source memory is the memory space of the 2-D data, and the purpose memory is transmitted for storing
2-D data afterwards.
It is wherein, described that the 2-D data to be transmitted is transmitted to destination address described in the purpose memory is corresponding
Memory space includes：
The DMA control modules obtain the data volume of each transmission 2-D data from the register module；
The 2-D data to be transmitted the purpose is transmitted to according to the data volume of each transmission 2-D data to deposit
The corresponding memory space of destination address described in reservoir.
In a kind of feasible embodiment, above-mentioned DMA control modules obtain the two-dimemsional number to be transmitted from the DMA command
According to source address, 2-D data to be transmitted destination address and every time transmission 2-D data data volume.
Optionally, the DMA command is the instruction of loading/storage organization.
Optionally, the DMA command is fixed length instructions.
Optionally, the register module includes：
Scalar register heap, for storing data scale, the source address of 2-D data, the destination address of 2-D data, two
The in situ location of dimension data put gap size, 2-D data puts gap size, memory access number and data destination address
Transformation scale；
The wherein described data scale is the data volume of 2-D data transmitted every time, and data transformation scale, which is 2-D data, to be needed
Carry out the data volume of data transformation.
Optionally, the source address and destination address also mark the type of affiliated memory space；If the memory space is
External memory, then raw address and destination address also mark affiliated stream；If the memory space is built-in storage, raw address and mesh
Address also mark belonging to built-in storage submodule；
Wherein, the stream is grouping when multi-group data alternately transmits.
Optionally, the DMA command includes but is not limited to data transmission (Data Transfer, DTT) instruction and address
Redirect (Address Jump, ADJ) instruction.
Optionally, the DMA command includes that an operation code and five operation domains, the operation code are used to indicate the DMA
The function of instruction；Five operation domains be respectively the first operation domain, the second operation domain, third operation domain, the 4th operation domain and
5th operation domain；
Wherein, first operation domain is used to indicate the memory space belonging to the source address of 2-D data, second behaviour
The source address of 2-D data is used to indicate as domain, the third operation domain is used to indicate depositing belonging to the destination address of 2-D data
Space is stored up, the 4th operation domain is used to indicate the destination address of 2-D data, and the 5th operation domain is used to indicate two-dimemsional number
According to the data volume transmitted every time；
Optionally, the ADJ instructions include two operation domains, respectively the 6th operation domain and the 7th operation domain；Institute
The number that the 6th operation domain is used to indicate address register is stated, the 7th operation domain is used to indicate the volume for redirecting value register
Number.
Wherein, described address register is for storing the source address, and the value register that redirects is for storing source address
Redirect value.
Optionally, the data transmission device further includes：
Data buffer storage unit, the 2-D data read from source memory according to the source address for interim storage.
Optionally, the data buffer storage unit includes：
Scratchpad, the transmission for supporting different size of 2-D data, and the purpose memory is written
Described in the corresponding memory space of destination address.
Optionally, the DMA control modules include：
Command unit, for handling the original DMA command, with the DMA command that obtains that treated；
Addition unit, source address and 2-D data for 2-D data according to treated DMA command, to be calculated
Destination address；
Read-write cell, for reading the 2-D data from the source memory according to the source address, and will be described
2-D data is sent to the corresponding memory space of destination address described in purpose memory.
Optionally, the addition unit and read-write cell are multithread water level structure, and the addition unit is in first-class
Water grade, the read-write cell are in the second pipelining-stage.
Optionally, described instruction unit includes：
Instruction expansion unit, for the DMA command to be expanded into system DMA instruction；
Instruction cache unit, for storing the system DMA instruction；
Instruction process unit, for handling the instruction of the system DMA in described instruction buffer unit.
Optionally, described instruction buffer unit includes：
Reorder caching, for storing the system DMA instruction.
Optionally, after the system DMA instruction execution is complete, if system DMA instruction while and instruction buffer
System DMA instruction earliest in instruction is not submitted in unit, then system DMA instruction will be submitted, which refers to
The operation carried out is enabled to will be unable to cancel to the change of data transmission device state.
Optionally, described instruction processing unit includes：
Fetch unit, for obtaining the system DMA instruction from described instruction buffer unit；
Decoding unit, for instructing the system DMA into row decoding；
Instruction queue, for carrying out sequential storage to the system DMA instruction after decoding.
Second aspect, the embodiment of the present application also provides a kind of data transmission methods, including：
The source address and destination address of 2-D data to be transmitted are obtained from register module according to the DMA command received
Or the source address and destination address of the 2-D data to be transmitted are directly acquired from the DMA command；
The 2-D data to be transmitted is obtained from source memory according to the source address of the 2-D data to be transmitted；
By the destination address pair of 2-D data to be transmitted described in the two-dimensional data storage to be transmitted to purpose memory
The memory space answered；
Wherein, the data to be transmitted is 2-D data, such as image data, video data.
Optionally, the source address of above-mentioned 2-D data, destination address and the data volume for transmitting 2-D data every time can also be
It is obtained in above-mentioned DMA command.
It should be noted that above-mentioned source memory is the memory space of above-mentioned 2-D data, above-mentioned purpose memory is used for
2-D data after storage transmission.
Wherein, the method further includes：
Obtain from the register module data volume of transmission 2-D data every time according to the DMA command, and according to
The 2-D data to be transmitted is transmitted to the corresponding space of the destination address by the data volume of transmission 2-D data every time.
Optionally, the DMA command includes data transfer instruction and address jump instruction；
The data transfer instruction is used to indicate read-write cell in DMA control modules according to source address from source memory
Middle a certain size number of reading is written in purpose memory in the corresponding memory space of destination address, and the scales of data can be from
It is obtained in register module or above-mentioned DMA command；
Described address jump instruction is used to indicate addition unit in DMA control modules by wantonly two in register module
Value in a register (including an address register and one redirect value register) is added, and is then write back on one of them
It states in address register, to complete the operation of the line feed in the DMA command.
Described address register is for storing the source address, and the value register that redirects is for storing redirecting for source address
Value.
Optionally, after the system DMA instruction execution is complete, if system DMA instruction while and DMA controls
In molding instruction cache unit in the block, it is not submitted system DMA instruction earliest in instruction, then the system DMA instructs
It will be submitted, the operation that system DMA instruction carries out will be unable to cancel to the change for the state that 2-D data transmits.
The device for the DMA command transmission 2-D data that the disclosure provides, can support two-dimentional DMA command, in image, video
The efficiency and standardized degree that data transmission is greatly improved under the application scenarios of processing, compensate for Data-intensive computing task
I/O short slabs.Meanwhile the device also supports multi-group data alternately to transmit independently of each other, improves parallel data processing task
In cache hit rate.
The aspects of the invention or other aspects can more straightforwards in the following description.
Description of the drawings
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
Obtain other attached drawings according to these attached drawings.
Fig. 1 is a kind of structural schematic diagram of data transmission device provided in an embodiment of the present invention；
Fig. 2 is the concrete structure schematic diagram of one embodiment of the present invention；
Fig. 3 is the step flow chart of the embodiment of the present invention；
Fig. 4 is the form schematic diagram of the instruction set of the embodiment of the present invention；
Fig. 5 is that the DMA control modules of the embodiment of the present invention execute the assembly line space-time diagram of 2D command dmas.
Specific implementation mode
Based on above-mentioned technical problem, this application provides a kind of data transmission devices, solve existing in the prior art two
Excessive problem is lacked when dimension data transmission efficiency is low, multi-group data alternately transmits, so that 2D DMA are more extensively, efficiently
It applies in the applications such as image, video on ground.
To make the purpose, technical scheme and advantage of the application be more clearly understood, below in conjunction with specific embodiment, and reference
Attached drawing is described in further detail the application.
Referring to Fig. 1, Fig. 1 is a kind of structural schematic diagram of data transmission device provided by the embodiments of the present application.Such as Fig. 1 institutes
Show, which includes register module and DMA control modules.
Wherein, above-mentioned register module, for store the source address of 2-D data, the destination address of 2-D data and every time
Transmit the parameters such as the data volume of 2-D data.
Wherein, above-mentioned 2-D data can be image data or video data.
Specifically, the source address of above-mentioned 2-D data is storage address of the 2-D data in source memory, above-mentioned
The destination address of 2-D data is the corresponding address of memory space for indicating the 2-D data and being transferred to.Above-mentioned 2-D data
Transmission quantity is that above-mentioned data transmission device transmits the data volume transmitted every time when above-mentioned 2-D data.
It should be noted that above-mentioned source memory is the memory space of above-mentioned 2-D data, above-mentioned purpose memory is used for
2-D data after storage transmission.Above-mentioned source memory can be interior register or external register, and above-mentioned purpose memory can
For interior register or external register, and the source memory and purpose memory can be same memory space, or different
Memory space.
Above-mentioned register module includes：
Scalar register heap includes providing address register needed for 2-D data transmission process, storage 2-D data rule
The register of the parameters such as the register of mould and storage data quantity.Scalar register heap can be used for storing 2-D data address, two
The information such as dimension data scale.
Wherein, 2-D data address is the address that data store in memory or external memory, i.e., above-mentioned 2-D data
Source address and destination address；2-D data scale is the row, column size that 2-D data stores in memory or external memory；May be used also
Byte number, bit number for being stored in a computer for above-mentioned 2-D data etc..
It should be noted that above-mentioned 2-D data is image data or video data, but finally with image data
Form is stored in source memory.Image data is stored in the pixel that the least unit in source memory is image data
Point, in the form of RGB.For image data, the pixel of M rows N row can be regarded as.
Above-mentioned DMA control modules for receiving DMA command, and according to DMA command, are obtained from above-mentioned register module
The source address of 2-D data, destination address and the every time data volume of transmission 2-D data；Or from above-mentioned DMA command obtain on
State the source address of 2-D data, destination address and the every time data volume of transmission 2-D data；
According to the source address of above-mentioned 2-D data, above-mentioned 2-D data is obtained from above-mentioned source memory；
Above-mentioned 2-D data is transmitted to according to the data volume of above-mentioned each transmission 2-D data above-mentioned in purpose memory
Destination address corresponds to memory space.
As shown in Fig. 2, above-mentioned DMA control modules include：
Command unit, for handling original DMA command, the DMA command that obtains that treated；
Addition unit, for according to treated DMA command, the source address and two-dimemsional number of 2-D data to be calculated
According to destination address；
Read-write cell, for reading above-mentioned 2-D data from above-mentioned source memory according to the source address, and according to upper
Above-mentioned 2-D data is written in above-mentioned purpose memory the destination address for stating 2-D data.
Further, according to treated, DMA command obtains each biography to above-mentioned reading unit from above-mentioned register module
The data volume of defeated 2-D data, and be several times transmitted to above-mentioned 2-D data according to the data volume of each transmission 2-D data
In above-mentioned purpose memory.
Wherein, above-mentioned addition unit and above-mentioned read-write cell are multithread water level structure, and above-mentioned addition unit is in first
Pipelining-stage, above-mentioned read-write cell is in the second pipelining-stage.It, can be more efficiently when a plurality of DMA command of sequential serial reaches
Realize the operation required by this succession of DMA command.DMA control modules are responsible for all dma operations of above-mentioned data transmission device,
Including but not limited to one-dimensional read operation, one-dimensional write operation, two-dimentional read operation and two-dimentional write operation.
Further, command unit includes：
Instruction expansion unit, for original DMA command to be expanded into system DMA instruction, system DMA instruction is DMA controls
The control instruction of molding block.
When needing DMA to transmit 2-D data, then above-mentioned DMA control modules receive DMA command order, the DMA command table
The source address of 2-D data, the destination address of 2-D data and size needed for bright.Wherein, the source address and destination address also need to
Memory space belonging to label, is memory or external memory, if it is external memory, it is also necessary to mark affiliated stream.Here
Grouping of " stream " i.e. aforementioned multi-group data when alternately transmitting, demand of the processor to total data may be discontinuous, but
For some specific stream, it is likely that be continuous.
Instruction cache unit is used for storage system DMA command, i.e., during executing DMA command, while being also buffered in
In instruction cache unit.After an instruction execution is complete, if the instruction is also not to be submitted in instruction cache unit simultaneously
Earliest one instruction, the instruction will be submitted in instruction, once submitting, this instructs the operation carried out to change unit state
Change will be unable to cancel.
In one embodiment, above-metioned instruction buffer unit can be the caching that reorders, and can also be that other cachings are single
Member.
Instruction process unit, for the system DMA instruction in process instruction buffer unit.
Wherein, instruction process unit may include：
Fetch unit, for obtaining system DMA instruction from instruction cache unit；
Decoding unit, for instructing system DMA into row decoding；
Instruction queue, for carrying out sequential storage to the system direct memory access instruction after decoding.
In addition, DMA control modules can be also used for, according to DMA command, obtaining from processor die initial data in the block
2-D data is sent to the position for not storing the 2-D data in memory module, or from processor die processing data in the block
Middle acquisition 2-D data is simultaneously transmitted to memory module.
It should be noted that above-mentioned processor module can be source memory, the two dimension is not stored in above-mentioned memory module
The position of data is purpose memory or above-mentioned memory module is purpose memory.
Above-mentioned data transmission device can also include data buffer storage unit, for the memory of source address memory space and
DMA control modules carry out data transmission, and data buffer storage unit can be scratchpad, can support different size data
Transmission, the data being written into are temporarily stored in scratchpad, are later used to veritably be written in memory module.
Above-mentioned data transmission device can also include Date Conversion Unit, for making to the data taken out from source memory
Data conversion, wherein data conversion include but not limited to data precision conversion, fixed and floating is mutually converted, data array turns
It changes, the conversion of data volume size.
In a kind of feasible embodiment, above-mentioned read-write cell obtains the destination of above-mentioned 2-D data and the 2-D data
Behind location, directly 2-D data is written in purpose memory according to the destination address of 2-D data.
In a kind of feasible embodiment, above-mentioned read-write cell obtains the destination of above-mentioned 2-D data and the 2-D data
Behind location, the 2-D data and its destination address are transmitted to above-mentioned Date Conversion Unit, the Date Conversion Unit is by the two-dimemsional number
After being handled, directly 2-D data is written in purpose memory according to the destination address of 2-D data.
In a kind of feasible embodiment, above-mentioned read-write cell obtains the destination of above-mentioned 2-D data and the 2-D data
Behind location, the 2-D data and its destination address are transmitted to above-mentioned Date Conversion Unit, the Date Conversion Unit is by the two-dimemsional number
After being handled, transformed 2-D data and its destination address are stored in above-mentioned data buffer storage unit.The data are slow
2-D data is written in purpose memory according to the destination address of 2-D data for memory cell.
Above-mentioned data transmission device can also include address mapping unit, be used for when source address is virtual address, to source
Address of cache is made in address, and source address is converted to the corresponding physical address of source address；When destination address is virtual address, to mesh
Address make address of cache, destination address is converted into the corresponding physical address of destination address.
The DMA instruction set of device provided by the embodiments of the present application uses loading/storage (Load/Store) structure, read-write single
Member will not operate the data in memory.Preferably, DMA instruction set uses fixed length instructions.
The another aspect of the embodiment of the present application additionally provides a kind of data transmission method, is obtained simultaneously for DMA control modules
2-D data is stored, Fig. 3 is the step flow chart of the embodiment of the present disclosure, as shown in figure 3, including step：
S301, data transmission device obtain the source address and destination address of 2-D data according to the DMA command received.
Specifically, above-mentioned data transmission device receives DMA command, above-mentioned from register module acquisition according to the DMA command
2-D data source address and destination address, or obtain from DMA command the source address and destination address of the 2-D data.
It should be noted that above-mentioned register module be stored with the source address of above-mentioned two-dimensional data storage, destination address and
The data volume of transmission 2-D data every time.
Optionally, above-mentioned data transmission device obtains transmission every time according to above-mentioned DMA command from above-mentioned register module
The data volume of 2-D data.
S302, data transmission device obtain the 2-D data according to the source address of the 2-D data.
Specifically, all data are stored in advance in specific source memory, which may include in chip
Each memory module in portion and external memory module.Above-mentioned data transmission device is according to the source of the 2-D data got
Location obtains the 2-D data from above-mentioned source memory.
In a kind of feasible embodiment, before obtaining the 2-D data according to the source address of the 2-D data,
When it is virtual address to determine the source address of above-mentioned 2-D data, above-mentioned data transmission device to the source address of the 2-D data into
Row address maps, and obtains the physical address of above-mentioned source address.Above-mentioned data transmission device is according to the physical address of above-mentioned source address
Above-mentioned 2-D data is obtained from above-mentioned source memory.
The 2-D data is transmitted to purpose storage by S303, data transmission device according to the destination address of 2-D data
Device.
Specifically, 2-D data is obtained in field of the above-mentioned data transmission device from register module or from DMA command
After destination address, above-mentioned 2-D data is transmitted to by purpose memory according to the destination address of 2-D data.Wherein, which deposits
Reservoir may include each memory module of chip interior and external memory module.
Wherein, above-mentioned source memory and above-mentioned purpose memory are not same register.
In a kind of feasible embodiment, above-mentioned data transmission device is according to above-mentioned each data volume for transmitting 2-D data
Above-mentioned 2-D data is transmitted in above-mentioned purpose memory in the corresponding memory space in above-mentioned purpose address several times.
In a kind of feasible embodiment, the 2-D data is being transmitted to by purpose according to the destination address of 2-D data
Before memory, when determining that the destination address of above-mentioned 2-D data is virtual address, above-mentioned data transmission device is to above-mentioned purpose
Address carries out address of cache, which is converted into the corresponding physical address of the destination address.Above-mentioned data transmission device
Above-mentioned 2-D data is transmitted in above-mentioned purpose memory according to the corresponding physical address in above-mentioned purpose address.
In a kind of feasible implementation, above-mentioned data transmission device divides according to the data volume of above-mentioned each transmission 2-D data
Above-mentioned 2-D data is repeatedly transmitted to the corresponding storage of the corresponding physical address in above-mentioned purpose address in above-mentioned purpose memory
In space.
Fig. 4 diagrammatically illustrates the form schematic diagram of the instruction set of the embodiment of the present disclosure, as shown in figure 4, every instruction packet
Include an operation code and five operation domains, wherein operation code is used to indicate the function of the instruction, and DMA control modules pass through identification
The operation code can be operated accordingly, and operation domain is used to indicate the data address information of the instruction.Instruction set includes difference
The DMA command of function：
DTT is instructed：According to the instruction, read-write cell reads a word from source address, destination address is written, while being also written
Data buffer storage unit.Data movement instruction includes five operation domains, respectively the first operation domain, the second operation domain, third operation
Domain, the 4th operation domain and the 5th operation domain.Wherein, above-mentioned first operation domain is used to indicate depositing belonging to the source address of 2-D data
Space is stored up, above-mentioned second operation domain is used to indicate the source address of 2-D data, and above-mentioned third operation domain is used to indicate 2-D data
Destination address belonging to memory space, above-mentioned 4th operation domain is used to indicate the destination address of 2-D data, above-mentioned 5th behaviour
The data volume of each transmission 2-D data of 2-D data is used to indicate as domain.The data of a word size are completed in every instruction
Transmission.
ADJ is instructed：According to the instruction, above-mentioned addition unit by above-mentioned register module any two registers (including
One address register and one redirect value register) in value be added, then write back to one of address above mentioned register
In, to complete the operation of the line feed in 2D DMA tasks.
Address above mentioned register is for storing the source address, and the above-mentioned value register that redirects is for storing redirecting for source address
Value.
Above-mentioned ADJ instruction includes two operation domains, respectively the 6th operation domain and the 7th operation domain.Wherein, the 6th operation
Domain is used to indicate the number of address register, and the 7th operation domain is used to indicate the number for redirecting value register.Above-mentioned ADJ instructions
After value in address register is added the value redirected in value register, and result back into address above mentioned register.
Fig. 5 diagrammatically illustrates the assembly line space-time diagram of the DMA control modules execution 2D command dmas of the embodiment of the present disclosure,
As shown in Figure 3, it is assumed that the 2D command dmas need to transmit the data that a block size is 3 × 3, then whole process needs altogether 9 to clap.
If that is, the data block size of 2D command dmas transmission is m × n, wherein m, n are positive integer, at this point, the disclosure
The data transmission procedure of embodiment needs altogether m × n to clap.
It should be noted that above-mentioned one claps a clock cycle for above-mentioned data transmission device.
Particular embodiments described above has carried out further in detail the purpose, technical solution and advantageous effect of the disclosure
Describe in detail bright, it should be understood that the foregoing is merely the specific embodiment of the disclosure, be not limited to the disclosure, it is all
Within the spirit and principle of the disclosure, any modification, equivalent substitution, improvement and etc. done should be included in the protection of the disclosure
Within the scope of.
Claims (23)
1. a kind of data transmission device, which is characterized in that including：
Register module is deposited for storing source address, the 2-D data that 2-D data stores in source memory in purpose
The data volume of the destination address and each transmission 2-D data that are stored in reservoir；
Direct memory access DMA control modules, for receiving DMA command, and according to the DMA command from the register module
Or the DMA command obtains the source address and destination address of 2-D data to be transmitted；
The DMA control modules are additionally operable to be obtained from the source memory according to the source address of the 2-D data to be transmitted
The 2-D data to be transmitted, and the 2-D data to be transmitted is transmitted to two dimension to be transmitted described in the purpose memory
The corresponding memory space of destination address of data；
Wherein, the source memory is the memory space of the 2-D data, after the purpose memory is for storing transmission
2-D data.
2. the apparatus according to claim 1, which is characterized in that the DMA control modules are specifically used for：
It is two-dimentional from each transmission is obtained in the register module or from the DMA command according to the DMA command
The data volume of data；
The 2-D data to be transmitted is transmitted to the purpose memory according to the data volume of each transmission 2-D data
Described in 2-D data to be transmitted the corresponding memory space of destination address.
3. the apparatus according to claim 1, which is characterized in that the source memory and purpose memory are including outside
Each storage device and internal each memory module.
4. according to claim 1-3 any one of them devices, which is characterized in that the DMA command is loading/storage organization
Instruction.
5. according to claim 1-4 any one of them devices, which is characterized in that the DMA command is fixed length instructions.
6. device according to claim 1 or 2, which is characterized in that the register module includes：
Scalar register heap, for storing data destination address of scale, the source address of 2-D data and 2-D data, two-dimemsional number
According to the source address put gap size, 2-D data the destination address put gap size, access times and
Data convert scale；
The wherein described data scale is the data volume of the 2-D data transmitted every time, data transformation scale is described two
Dimension data carries out the data volume of data transformation.
7. according to claim 1-6 any one of them devices, which is characterized in that the source address of the 2-D data and destination
Location also marks the type of affiliated memory space, if the memory space is external memory, the source address of the 2-D data
Affiliated stream is also marked with destination address；If the memory space is built-in storage, the source address and mesh of the 2-D data
Address also mark belonging to built-in storage submodule；
Wherein, the stream is grouping when multi-group data alternately transmits.
8. according to claim 1-5 any one of them devices, which is characterized in that the DMA command include operation code and
At least one operation domain, operation code are used to indicate the function of the instruction, and operation domain is used to indicate the data address of the instruction；It is described
DMA command includes data movement instruction and address jump instruction；
The data movement instruction includes five operation domains, respectively the first operation domain, the second operation domain, third operation domain, the
Four operation domains and the 5th operation domain, first operation domain are used to indicate the memory space belonging to the source address of 2-D data, institute
The source address that the second operation domain is used to indicate 2-D data is stated, the third operation domain is used to indicate the destination address of 2-D data
Affiliated memory space, the 4th operation domain are used to indicate the destination address of 2-D data, and the 5th operation domain is for referring to
Show the data volume of 2-D data transmitted every time；
Described address jump instruction includes two operation domains, respectively the 6th operation domain and the 7th operation domain, the 6th operation
Domain is used to indicate the number of address register, and the 7th operation domain is used to indicate the number for redirecting value register；
Wherein, described address register is used for the source address, and the value register that redirects redirects value for store source address.
9. according to the device described in any one of claim 1-8, which is characterized in that the data transmission device further includes：
Data buffer storage unit, the 2-D data read from source memory according to the source address for interim storage.
10. device according to claim 9, which is characterized in that the data buffer storage unit includes：
Scratchpad, the transmission for supporting different size of 2-D data, and institute in the target memory is written
State the corresponding memory space of destination address.
11. device according to claim 1 or 2, which is characterized in that the DMA control modules include：
Command unit, for handling the original direct memory access instruction, with the DMA command that obtains that treated；
Addition unit, for according to treated the DMA command, the source address and described two of the 2-D data to be calculated
The destination address of dimension data；
Read-write cell, for reading the 2-D data from the source memory according to the source address of the 2-D data, and
The 2-D data is sent to the corresponding memory space of destination address of 2-D data described in the purpose memory.
12. according to claim 1-11 any one of them devices, which is characterized in that the data transmission device further includes：
Date Conversion Unit, for making data conversion to the 2-D data read from source memory；
The wherein described data conversion includes but not limited to data precision conversion, fixed and floating is mutually converted, data array is converted,
Data volume size is converted.
13. device according to claim 8, which is characterized in that the DMA command further includes being used to indicate to 2-D data
Carry out the operation domain of the mode of data conversion.
14. according to claim 1-13 any one of them devices, which is characterized in that the data transmission device further includes：
Address mapping unit, the mapping for making address to source address or destination address, with the address after mapping to corresponding
It fetches in memory space evidence.
15. according to the devices described in claim 11, which is characterized in that the addition unit and read-write cell are more pipelining-stage knots
Structure, the addition unit are in the first pipelining-stage, and the read-write cell is in the second pipelining-stage.
16. according to the devices described in claim 11, which is characterized in that described instruction unit includes：
Instruction expansion unit, for the DMA command to be expanded into system DMA instruction；
Instruction cache unit, for storing the system DMA instruction；
Instruction process unit, for handling the instruction of the system DMA in described instruction buffer unit.
17. device according to claim 16, which is characterized in that described instruction buffer unit includes:
Reorder caching, for storing the system DMA instruction.
18. device according to claim 16 or 17, which is characterized in that after the system DMA instruction execution is complete, such as
The fruit system DMA instructs while being also not to be submitted system DMA instruction earliest in instruction in described instruction buffer unit,
Then system DMA instruction will be submitted, once submitting, the operation that system DMA instruction carries out is to the data transmission device shape
The change of state will be unable to cancel.
19. according to the device described in claim 16 to 17, which is characterized in that described instruction processing unit includes：
Fetch unit, for obtaining the system DMA instruction from described instruction buffer unit；
Decoding unit, for instructing the system DMA into row decoding；
Instruction queue, for carrying out sequential storage to the system DMA instruction after decoding.
20. a kind of data transmission method, which is characterized in that including step：
According to the DMA command received from obtaining 2-D data to be transmitted in register module or from the DMA command
Source address and destination address or source address and the destination that the 2-D data to be transmitted is directly acquired from the DMA command
Location；
The 2-D data to be transmitted is obtained from source memory according to the source address of the 2-D data to be transmitted；
The destination address of 2-D data to be transmitted described in the two-dimensional data storage to be transmitted to purpose memory is corresponding
Memory space；
Wherein, the source memory is the memory space of the 2-D data, after the purpose memory is for storing transmission
2-D data.
21. according to the method for claim 20, which is characterized in that the method further includes：
The data volume of transmission 2-D data every time is obtained from the register module according to the DMA command, and according to each
The 2-D data to be transmitted is transmitted to the corresponding space of the destination address by the data volume of transmission 2-D data.
22. the method according to claim 20 or 21, which is characterized in that the original direct memory access instruction includes number
According to process instruction and address jump instruction；
The data processing instructions, the read-write cell being used to indicate in DMA control modules are read according to source address from source memory
A certain size number is taken, is written in purpose memory in the corresponding memory space of destination address, data scale can be from register
It is obtained in module or above-mentioned DMA command；
Described address jump instruction, the addition unit being used to indicate in DMA control modules post any two in register module
Value in storage (including an address register and one redirect value register) is added, and then writes back to one of them above-mentionedly
In the register of location, to complete the operation of the line feed in the DMA command；
Wherein, described address register is for storing the source address, the jump for redirecting value register for storing source address
Turn value.
23. according to claim 20 to 22 any one of them method, which is characterized in that after system DMA instruction execution is complete,
If the system DMA instructs while being also not to be submitted one in instruction earliest in the instruction cache unit in DMA control modules
The instruction of system DMA, then system DMA instruction will be submitted, once submitting, the operation that system DMA instruction carries out is to two dimension
The change of the state of data transmission will be unable to cancel.
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