CN101196860A - Optimized two-dimension DMA transmission method especially for access to image block - Google Patents

Optimized two-dimension DMA transmission method especially for access to image block Download PDF

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CN101196860A
CN101196860A CNA2006101574403A CN200610157440A CN101196860A CN 101196860 A CN101196860 A CN 101196860A CN A2006101574403 A CNA2006101574403 A CN A2006101574403A CN 200610157440 A CN200610157440 A CN 200610157440A CN 101196860 A CN101196860 A CN 101196860A
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data
image
sub
edge
access
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CN100552654C (en
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方应龙
汤加跃
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Wuxi Xiang Xiang Computer Technology Co Ltd
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Arkmicro Technologies Inc
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Abstract

The invention discloses a two-dimensional DMA method special for data optimization of MAE access image block, which can obviously accelerate the transmission speed of the image block when processing byte alignment and automatically fill up the subimage block data beyond the image boundary. The method mainly comprises the following steps: (1) gaining the initial work address of the actual poke and access of poke edge and access edge according to the leading byte addresses of the poke edge and the access edge; (2) gaining poke times of the poke edge and access times of the access edge according to the leading byte addresses of poke edge and access edge and transmit data in each row; (3) initializing the row counting value and line counting value of the poke edge and access edge; (4) reading data of poke edge and writing in adaptive FIFO; (5) writing data in the adaptive FIFO; (6) continuing to transmit the data in next row if the adaptive FIFO is not full. The method can increase the transmission speed by four times and ensure the accuracy of data access.

Description

Two-dimensional DMA transmission method specially optimized for accessing image block
Technical Field
The invention relates to a two-dimensional DMA transmission method which can be specially optimized for accessing image blocks on a hardware MAE (media access operator engine) of video communication. And more particularly, to a transmission method when MAE accesses sub-picture block data having byte alignment and sub-block data boundaries of a picture transcend picture boundaries at high speed.
Background
In the conventional DMA transfer, the DMA can process data in parallel with the main processor, reducing the load of the processor, and because the DMA is a direct memory access, the transfer speed is faster than the speed of the CPU to access data, so the DMA is generally used for transferring when a large amount of data access is required.
However, the conventional DMA data transmission speed does not gradually meet the requirements of high bandwidth and high transmission rate image video data transmission, under the ordinary two-dimensional DMA transmission, the data transmission method for processing byte alignment is to perform single byte transmission, which wastes a large amount of bandwidth, and in multimedia applications, the image video data is very large data because the image is two-dimensional. U.S. Pat. No. 3, 6292853, 1 discloses a two-dimensional DMA transfer mode in which an image to be transferred can be specified by configuring the two-dimensional size of the image, and the number of configurations can be reduced while facilitating the configuration, and the transfer speed can be increased. However, in the image access of the multimedia acceleration engine, since it is often necessary to take the sub-image blocks to process or store the processed sub-image blocks into the memory, and the sub-image blocks are somewhat byte-aligned, if the ordinary two-dimensional DMA is used, the transmission speed will be greatly reduced, and in some processing cases, the boundary of the sub-image block is not within the boundary of the original image, such as the ordinary two-dimensional DMA transmission, the number taking error will be caused.
Disclosure of Invention
The invention aims to provide a two-dimensional DMA method specially optimized for MAE access image block data, which aims to improve the image block data transmission speed when processing byte alignment and automatically complement sub-image block data which are not in the image boundary.
A two-dimensional DMA transfer method optimized for accessing image blocks, the method comprising the steps of:
step 1: according to the initial byte addresses of the storage side and the access side, the actual storage number of the storage side and the access side and the initial word address of the access are obtained;
step 2: obtaining the number of times of storing the data in each row and the number of times of fetching the data in each row according to the initial byte addresses of the storing edge and the fetching edge and the number of bytes of each row (one-dimensional) of transmitted data;
and step 3: initializing a row count value and a column count value of a storage side and a fetch side;
and 4, step 4: reading data of the storage side according to the initial word address of the storage side and the state of the self-adaptive FIFO and writing the data into the self-adaptive FIFO;
and 5: when data is written into the self-adaptive FIFO in the step (4), reading the data in the self-adaptive FIFO by a reading pointer according to the word address of the fetching edge and the state of the self-adaptive FIFO when the number of bytes of the effective data to be read is larger than or equal to the number of bytes of the stored effective data;
step 6: after the data of one line is stored while the number is stored, if the adaptive FIFO is not full, the data of the next line is continuously transmitted, the line transmission number counting is restarted, the row counter is counted once, and the reading is continuously carried out while the reading is carried out;
the actual memory and fetch start WORD addresses in step (1) of the method are obtained by removing the lower two bits from the respective byte addresses.
The step 3 further comprises the following steps:
and initializing a read-write pointer of the self-adaptive FIFO according to the number of the effective data stored by the storage edge and the number of bytes of the effective data required to be fetched by the fetch edge.
The step 4 further comprises the following steps:
and counting the number of times of writing one data register every time, and updating the adaptive FIFO write pointer.
The step 5 further comprises the following steps:
and after the data is read, updating the number of times of fetching, the adaptive FIFO read pointer and the adaptive FIFO state.
The step 6 further comprises the following steps:
if reading a row, restarting the row transmission counting, and counting the row counter once until all data transmission is completed.
When the MAE processes an image, sub image blocks in the image need to be taken for processing, however, some sub image blocks exceed the image boundary, and the data exceeding the image boundary can only take wrong data according to the conventional two-dimensional DMA taking method.
A two-dimensional DMA transfer method optimized specifically for accessing image blocks, comprising: the method adopts an automatic filling technology to fetch the sub image blocks which exceed the image boundary, and comprises the following specific steps:
step 1: determining an image using the plane coordinates, and representing the position of each point on the image by the plane coordinates;
step 2: determining the sub-image block to be transmitted by using the coordinates of the starting point, the width and the height of the sub-image;
and step 3: determining the area of the sub-image block point according to the coordinates of the point to be transmitted of the sub-image block, and adopting different filling methods according to the area of the sub-image block point;
and 4, step 4: repeating the step (3) for all the points to be transmitted of the sub-image block, and processing four points each time until the sub-image block data is completely taken.
The step (3) of determining the area where the sub-image block point is located according to the coordinates of the point to be transmitted of the sub-image block, and then adopting different filling methods according to the area where the sub-image block point is located, is characterized in that: the method specifically comprises the following steps: if the coordinates of the sub-image block point are not in the image area, taking the four bytes of data closest to the image boundary of the point; wherein,
if the sub-image block point is in the left or right area of the image, only one byte near the image boundary is used as the complement number for the four bytes of data;
if the sub-image block point is right above or right below the image, the four bytes of data are all taken as the padding number, i.e. the four bytes of data stored in the FIFO are the taken number.
The invention has the following significant meaning:
the invention discloses a two-dimensional DMA transmission method special for MAE high-speed access image block data, which meets the requirement of MAE high-speed access data, uses a self-adaptive FIFO counting to automatically complement sub-image block data which are not in the image boundary, can effectively improve the transmission speed when the byte-aligned data is transmitted, and can improve the transmission speed by four times when the byte-aligned data is transmitted to the maximum. The automatic filling method when the sub-image block point is not in the image area when the sub-image block reference frame is used in MAE processing can ensure the correctness of data access and MAE processing.
Drawings
FIG. 1 is a block diagram of a system with MAE two-dimensional DMA;
FIG. 2 is a schematic diagram of four different byte-aligned block data accesses and stores in memory;
FIG. 3 is a schematic diagram of an automatic compare FIFO, where the write pointer is marked on the left and the read pointer is marked on the right;
fig. 4 is an abstract view of the image and sub-image blocks in memory.
Detailed Description
The process of the present invention is described in more detail below with reference to the accompanying drawings.
FIG. 1 is a system diagram of the method of the present invention in which a DMA controls data access through an intermediate FIFO after being configured with register parameters.
When the data to be transmitted is byte-aligned, i.e. the lower two bits of its address are not 0, an adaptive FIFO of 16 bytes is used to handle the transmission of the data. Fig. 3 is a schematic diagram of a 16-byte adaptive FIFO, and fig. 2 shows different cases of typical four byte alignments, and the specific byte alignment processing manner is as follows:
first, it is assumed that the lower two bits of the start address of the fetch edge are g, the lower two bits of the line width of the two-dimensional data to be fetched are g1, the other upper bits are g2, the fetch number is g3, the lower two bits of the start address of the memory edge are s, the lower two bits of the line width of the two-dimensional data to be stored are s1, the other upper bits are s2, and the memory number is s 3. The high-speed transmission using adaptive FIFO for processing byte alignment comprises the following steps:
step 1: and according to the initial byte addresses of the storage side and the access side, the actual storage number and the access initial word address of the storage side and the access side are obtained. They are respectively obtained by removing the lower two bits of the respective byte addresses;
step 2: obtaining the number of times of storing the data in each row and the number of times of fetching the data in each row according to the initial byte addresses of the storing edge and the fetching edge and the number of bytes of each row (one-dimensional) transmission data; wherein
Determination of the number of times of storage: if s is equal to 0, s1 is equal to 0, the number of times of deposit s3 is s2, if s is not equal to 0, s1 is not equal to 0, and s + s1 is greater than 4, the number of times of deposit s3 is s2+2, otherwise the number of times of deposit s3 is s2+ 1;
and (3) determining the number of times of fetching: if g is equal to 0, g1 is equal to 0, the number of fetches g3 is g2, if g is not equal to 0, g1 is not equal to 0, and g + g1 is greater than 4, the number of fetches g3 is g2+2, otherwise the number of fetches g3 is g2+ 1.
Fig. 2 shows the different cases of the typical four byte alignments, and the storage times and the fetching times in the four cases are respectively described as follows:
FIG. 2 is a drawing: (a) the number of times of deposit and the number of times of access in the case of (a) are both 3 times, (b) the number of times of deposit and the number of times of access in the case of (b) are both 4 times, (c) the number of times of deposit is 3 and the number of times of access is 4, and (d) the number of times of deposit is 4 and the number of times of access is 3.
And step 3: initializing a row count value and a column count value of a storage side and a fetch side; the read and write pointers of the adaptive FIFO are initialized, as shown in fig. 3, the read and write pointers do not point to the same place, which ensures that the redundant data does not affect the effective data access. Wherein
Step 3.1: the initial line count values of the storage side and the fetching side are equal to the line storage times and the line fetching times in the step (2), and the initial column values are equal to the column number of the data to be transmitted;
step 3.2: initialization of the write pointer: before the first transfer, the write pointer points to 0000;
step 3.3: initialization of the read pointer: if s is greater than or equal to g, the pointer is (g-s) when the FIFO data is read for the first time, and if s is less than g, the pointer is (16+ g-s);
the specific initialization process described in step 3 is described below with reference to fig. 2. In fig. 2: in case a, the initial write pointer is 0000, the initial read pointer is 0000, the first byte of the data stored for the first time is redundant invalid data, and the first byte read out is also redundant invalid; under the condition of b, the pointer of the number storing edge is 0000, the first three bytes of the number stored for the first time are all redundant data, and the pointer of the number fetching edge is 0001, so that the first two bytes of the number fetching for the first time are all redundant data; c, when the initial pointer of the storage side is 0000 and the initial pointer of the reading side is 1110, two valid data can be read and stored into the required word address; in case d the initial write pointer is 0000 and the initial read pointer is 0011, so that the read can start from valid data.
And 4, step 4: reading data of the storage side according to the storage side initial word address and the state of the self-adaptive FIFO and writing the data into the self-adaptive FIFO, if the FIFO has a vacant position of at least four bytes, reading the data and writing the data into the FIFO according to the storage side initial address, otherwise, waiting. The number of data pairs is counted once, i.e. 1 is subtracted, and the adaptive FIFO write pointer is updated, i.e. 4 is added.
And 5: when data is written into the self-adaptive FIFO, according to the initial word address of the fetching edge and the state of the self-adaptive FIFO, when the number of bytes of the effective data to be read is less than or equal to the number of bytes of the stored effective data, the data is read by the read enabling signal, and after the data is read, the fetching times, the reading pointer of the self-adaptive FIFO and the state of the self-adaptive FIFO are updated. Then the update of the read pointer is directly increased by 4.
The following describes specific how the read is enabled, i.e. when the read enable signal is enabled, and how the read pointer changes, with reference to fig. 2. In fig. 2: in case a, writing and reading can be performed synchronously, because the conditions of both sides are completely the same; under the condition of b, two effective data must be taken for the first time, the first stored number can only be stored into one effective number, so the stored number must be equal to the number of the two stored numbers and then taken, namely, the number of bytes of the effective data to be taken must be ensured to be smaller than the number of bytes of the effective data already stored, and the next number must be equal to the number written into one number again to be taken until the last number is written into, and two times of reading enables are continuously sent again to ensure that all the effective data are read out, certainly; in case c, data can be read by writing data once; and d, waiting for the number to be stored, storing the second number, reading the second number, storing the third number until the last number is stored, and continuously transmitting the read enable signal twice to ensure that the data can be completely read.
Step 6: after the data of one line is stored while the number is stored, as long as the adaptive FIFO is not full, the data transmission of the next line is started, the line transmission number counting is restarted, the line counter is counted once, the reading is continued while the reading is carried out, if the line is read, the line transmission counting is restarted, the line counter is counted once, and the line counter is counted once until all the data transmission is finished. In addition, the read and write pointers to the adaptive FIFO must be relocated. The specific repositioning method is as follows:
if the number of storage s3 is equal to the number of fetching g3, the relocation of the read-write pointer is the same as the change of the data transmission in the row, namely, the relocation is increased by 4; if the number of the stores s3 is greater than the number of the fetches g3, the read pointer of the fetches needs to be increased by 8 bytes when being relocated, and the pointer of the store edge is still increased by 4; if the number of stores s3 is less than the number of fetches g3, the write pointer of the store needs to be incremented by 8 when it is relocated, and the read pointer of the fetch is incremented by 4.
When the range of the transmitted sub-image exceeds the image boundary, the automatic filling technique is adopted, as shown in fig. 4, and the specific steps are as follows:
step 1: an image is defined using the coordinate pattern, the first point of the image is defined as the origin of coordinates, the row direction of the image is defined as the x-axis, the column direction is defined as the y-axis, and each point on the image is represented by coordinates (x, y), the x-axis and the y-axis being labeled in fig. 4.
Step 2: for the sub-picture block to be transmitted, after the picture is determined, the start point coordinates and the sub-picture width and height are used to determine the sub-picture block to be transmitted. The area 6 in fig. 4 is an area of the picture whose addresses are consecutive, the end-of-line address of each line being consecutive to the head-of-line address of the next line, and the sub-picture blocks are not necessarily.
And step 3: determining the area of the point of the sub-image block according to the coordinates of the point to be transmitted of the sub-image block, and using different filling methods according to the area of the point of the sub-image block, wherein
(a) While the image is in region 1: taking the lower left point value of the image to fill up the values of the points in all the areas 1, namely the coordinate point is the value of the (0, 0) point;
(b) while the image is in region 2: taking the point value of the lower boundary of the image to fill up the corresponding value, and taking the values of the four points of the coordinate points (x, 0), (x +1, 0), (x +2, 0), (x +3, 0);
(c) while the image is in region 3: the lower right point value of the image is taken to fill up the point value in the area 3, that is, the coordinate point (x line width, 0);
(d) while the image is in region 4: the point value of the left boundary of the image is taken to be filled in the point value in the region 4, that is, the point value of the coordinate point (0, y);
(e) while the image is in region 5: the point value of the upper left boundary of the image is taken to fill up the point value in the area 5, that is, the point value of the coordinate point (0, y-direction image width);
(f) while the image is in region 6: the filling is not required;
(g) while the image is in region 7: taking the point values of the upper boundary of the image to fill up the point values in the region 7, i.e. the coordinate points (x, y image width), (x +1, y image width), (x +2, y image width), (x +3, y image width);
(h) while the image is in region 8: taking the right boundary point value of the image to fill in the point value in the area 8, namely filling in the point value of the coordinate point (x line width, y);
(i) while the image is in region 9: the upper right-hand point of the image is taken to fill in the point values in the region 9, i.e. the coordinate points (x line width, y image width) are taken to fill in the data point values of all regions 9.
And (4) repeating the step (3) for all the points to be transmitted of the sub-image block until the sub-image block data is completely acquired, wherein four points are processed each time.
The examples used herein are intended to be illustrative of the methods of the present invention and are not intended to limit the scope of the invention thereto, and it will be understood by those skilled in the art that any method described herein or substitution of certain steps within the method of the present invention may be used within the scope of the invention as claimed.

Claims (8)

1. A two-dimensional DMA transfer method optimized for accessing image blocks, the method comprising the steps of:
step 1: according to the initial byte addresses of the storage side and the access side, the actual storage number of the storage side and the access side and the initial word address of the access are obtained;
step 2: obtaining the number of times of storing the data in each row and the number of times of fetching the data in each row according to the initial byte addresses of the storing edge and the fetching edge and the number of bytes of each row (one-dimensional) of transmitted data;
and step 3: initializing a row count value and a column count value of a storage side and a fetch side;
and 4, step 4: reading data of the storage side according to the initial word address of the storage side and the state of the self-adaptive FIFO and writing the data into the self-adaptive FIFO;
and 5: when data is written into the self-adaptive FIFO in the step (4), reading the data in the self-adaptive FIFO by a reading pointer according to the word address of the counting edge and the state of the self-adaptive FIFO when the number of bytes of the effective data to be read is more than or equal to the number of bytes of the stored effective data;
step 6: after the data of one line is stored while the number is stored, if the adaptive FIFO is not full, continuing to transmit the data of the next line, restarting to count the number transmitted by the line, counting the row counter once, and continuing to read while reading;
2. a two-dimensional DMA transfer method optimized for accessing blocks of images as claimed in claim 1, wherein: the actual memory and fetch start WORD addresses in step (1) of the method are obtained by removing the lower two bits from the respective byte addresses.
3. A two-dimensional DMA transfer method optimized specifically for accessing image blocks as claimed in claim 1, characterized by the steps of: the method also comprises the following steps in the step (3):
and initializing a read-write pointer of the self-adaptive FIFO according to the number of the effective data stored by the storage edge and the number of bytes of the effective data required to be fetched by the fetch edge.
4. A two-dimensional DMA transfer method optimized for accessing blocks of images as claimed in claim 1, wherein: the method also comprises the following steps in the step (4):
and counting the number of times of writing one data register every time, and updating the adaptive FIFO write pointer.
5. A two-dimensional DMA transfer method optimized for accessing blocks of images as claimed in claim 1, wherein: the method also comprises the following steps in the step (5):
and after the data is read, updating the number of times of fetching, the adaptive FIFO read pointer and the adaptive FIFO state.
6. A two-dimensional DMA transfer method optimized for accessing blocks of images as claimed in claim 1, wherein: the method also comprises the following steps in the step (6):
if reading a row, restarting the row transmission counting, and counting the row counter once until all data transmission is completed.
7. A two-dimensional DMA transfer method optimized specifically for accessing image blocks, comprising: the method adopts an automatic filling technology to fetch the sub image blocks which exceed the image boundary, and comprises the following specific steps:
step 1: determining an image using the plane coordinates, and representing the position of each point on the image by the plane coordinates;
step 2: determining the sub-image block to be transmitted by using the coordinates of the starting point, the width and the height of the sub-image;
and step 3: determining the area of the sub-image block point according to the coordinates of the point to be transmitted of the sub-image block, and adopting different filling methods according to the area of the sub-image block point;
and 4, step 4: repeating the step (3) for all the points to be transmitted of the sub-image block, and processing four points each time until the sub-image block data is completely taken.
8. A two-dimensional DMA transfer method optimized for accessing blocks of images as claimed in claim 7, wherein in step (3) the area of the points of the sub-blocks is determined based on the coordinates of the points to be transferred of the sub-blocks, and different padding methods are used based on the area of the points of the sub-blocks, characterized in that: the method specifically comprises the following steps: if the coordinates of the sub-image block point are not in the image area, taking the four bytes of data closest to the image boundary of the point; wherein,
if the sub-image block point is in the left or right area of the image, only one byte near the image boundary is used as the complement number for the four bytes of data;
if the sub-image block point is right above or right below the image, the four bytes of data are all taken as the padding number, i.e. the four bytes of data stored in the FIFO are the taken number.
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CN102129663A (en) * 2010-12-20 2011-07-20 福州瑞芯微电子有限公司 Processing method for image with unaligned reading address and width and circuit structure
CN102508800A (en) * 2011-09-30 2012-06-20 北京君正集成电路股份有限公司 Transmission method and transmission system for two-dimension data block
CN102567258A (en) * 2011-12-29 2012-07-11 中国科学院自动化研究所 Multi-dimensional DMA (direct memory access) transmitting device and method
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CN108804356A (en) * 2017-04-26 2018-11-13 上海寒武纪信息科技有限公司 Data transmission device and method
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CN101504632B (en) * 2009-01-21 2012-12-05 北京红旗胜利科技发展有限责任公司 DMA data transmission method and system, DMA controller
CN102129663A (en) * 2010-12-20 2011-07-20 福州瑞芯微电子有限公司 Processing method for image with unaligned reading address and width and circuit structure
CN102129663B (en) * 2010-12-20 2012-11-21 福州瑞芯微电子有限公司 Processing method for image with unaligned reading address and width and circuit structure
CN102508800A (en) * 2011-09-30 2012-06-20 北京君正集成电路股份有限公司 Transmission method and transmission system for two-dimension data block
CN102567258A (en) * 2011-12-29 2012-07-11 中国科学院自动化研究所 Multi-dimensional DMA (direct memory access) transmitting device and method
CN102567258B (en) * 2011-12-29 2014-08-27 中国科学院自动化研究所 Multi-dimensional DMA (direct memory access) transmitting device and method
CN105653378A (en) * 2014-11-11 2016-06-08 上海华虹集成电路有限责任公司 Method of microprocessor asynchronously reading peripheral equipment FIFO length
CN105653378B (en) * 2014-11-11 2019-08-13 上海华虹集成电路有限责任公司 The asynchronous method for reading peripheral hardware FIFO length of microprocessor
CN108804356A (en) * 2017-04-26 2018-11-13 上海寒武纪信息科技有限公司 Data transmission device and method
CN108885596A (en) * 2017-12-29 2018-11-23 深圳市大疆创新科技有限公司 Data processing method, equipment, dma controller and computer readable storage medium
CN111208713A (en) * 2020-03-17 2020-05-29 合肥芯碁微电子装备股份有限公司 Method for processing exposure pattern data, exposure control unit and direct-write exposure machine
CN111208713B (en) * 2020-03-17 2022-08-16 合肥芯碁微电子装备股份有限公司 Method for processing exposure pattern data, exposure control unit and direct-write exposure machine

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