CN116775524A - Lli dynamic writing method of dma linked list mode - Google Patents
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Abstract
The application relates to the technical field of data transmission and storage, and discloses a lli dynamic writing method of a dma linked list mode, which increases the decoding function of peripheral read/write signal access dma through a protocol conversion module 2, realizes that any peripheral can send a command for writing lli, the command is given to dma through the protocol conversion module 2, and then the dma writes lli information into a certain memory, and the process is realized by updating lli information by the peripheral so as to liberate cpu. In the traditional dma linked list transmission mode, updating the linked list information of the dma can only be read and written by the cpu, and all lli needs to be configured before transmission starts, if the transmission data volume is relatively large, the memory unit for storing lli information is also quite considerable, the application can solve the problems, and does not need a large memory for storing lli information, and in the process of transferring data of the dma, the peripheral equipment initiates writing or reading operation to the dma through the bus module, and the dma updates lli information without participation of the cpu, so that the cpu is released to improve the cpu efficiency.
Description
Technical Field
The application relates to the technical field of data transmission and storage, in particular to a lli dynamic writing method of a dma linked list mode.
Background
The dma (direct memory access, i.e. direct memory access) module is used for data handling, i.e. copying data from one address space to another address space, so as to realize high-speed data transmission between the peripheral device and the memory, and the dma has the advantages that after the cpu configures the transmission parameters of the dma (such as the transmission data amount, the data source address, the data destination address, the transmission mode and the like), the transmission process is controlled by the dma, and before the set data amount is transmitted, the transmission process does not need to be participated by the cpu at all, and the cpu can perform other operations, so that the efficiency of the cpu can be greatly improved.
There are generally four transmission modes, one of which is a linked list mode, and this mode is based on the data structure of fig. 1, and such a data structure is called a linked list element (lli), and it can be seen that all information necessary for transmission, such as source address, destination address, transmission data amount, other configuration of transmission and next lli of the transmission are included, such a block of data is generally placed in a continuous memory space for dmas to read, and dmas begin transmission work after obtaining all the information of transmission, and carry the data of the source address to the destination address in an orderly manner according to the configuration.
As can be seen in fig. 1, the 0xc address of lli stores the next lli instruction fetch address, the 0x8 address stores the data volume of this transmission, and after dma processes the data volume of this request, it will automatically go to the next lli address to obtain the next lli information, so that the data transmission can be performed all the time without the participation of cpu, although the storage of one lli block is generally placed in a continuous physical address, the storage addresses of each lli are not necessarily continuous, that is, the instruction fetch address of the next lli block is not necessarily next to the end address of the previous lli block, because the value fetch address of the next lli is recorded in the linked list element, and dma will jump to the corresponding address to read the next lli information.
In practical application, the linked list mode work process is as follows: the CPU configures a next working mode of the dma as a linked list mode, and configures the dma to acquire the address of the first lli; cpu writes all lli contents in memory to determine the configuration of the transfer; the CPU configures the peripheral so that the peripheral can initiate a data carrying request signal to dma after a certain waiting time is passed and corresponding conditions are met; the first lli is automatically read to start transmission after the dma receives the transmission request signal, for example, the data is carried from per1 to mem1; after the transmission is completed, the next lli information is acquired and the transmission is continued according to the configuration, for example, data is carried from per1 to mem until all data are transmitted, whether the transmission is the last transmission or not is stored in a ctrl field of lli, if the ctrl.last flag bit is 1, the transmission is the last transmission, and the dma channel is closed after the transmission is completed and no more transmission is performed.
It can be seen that in the above-mentioned existing linked list mode, after one transmission is completed, dma will automatically acquire next lli information to continue to carry data until the last carrying is completed, and the source address, destination address and data amount of each carrying data exist in lli, which can correspond to the application scenario of carrying data with discontinuous physical addresses, cpu only needs to be configured with lli in advance, the remaining carrying work is handed over to dma, the cpu is no longer involved, the dma is equivalent to one cpu at this time, and the transmission flow is controlled, but when carrying data are more, the storage space occupied by lli is very huge, one lli occupies 32 bytes of space (the lli occupied space of each dma controller is not necessarily so large, and is determined according to the dmalli design code), and the method for saving lli space is considered, namely several lli storage space circulation writing, so that cpu needs to continuously write lli, which is contrary to the initial task of using dma to liberate the cpu, based on this, the application proposes a lli dynamic writing method for the linked list.
Disclosure of Invention
(one) solving the technical problems
Aiming at the defects of the prior art, the application provides a lli dynamic writing method of a dma linked list mode to solve the problems, and the lli dynamic writing method of the dma linked list mode can circularly utilize less memory space, update lli by peripheral equipment while carrying data, does not need to update lli of cpu, and can effectively improve the efficiency of cpu.
(II) technical scheme
In order to achieve the above purpose, the present application provides the following technical solutions: a method of dynamically writing lli in a dma linked list mode, comprising the steps of:
1) CPU configures dma as a linked list transmission mode, and configures the address of the first lli in the dma;
2) The CPU configures a plurality of lli, particularly sends an AXI writing instruction through the CPU port, routes the writing instruction to the mem AXI port through the protocol conversion module 1, and writes lli information into a plurality of lli addresses respectively;
3) The CPU configures the condition that the peripheral device per1 sends out a transmission request signal req, specifically sends out an AXI writing instruction through the CPU, and converts the AXI writing instruction into an APB signal configuration per1 through the protocol conversion module 1;
4) Waiting for per1 to send a transmission request signal req to dma, dma confirming that data is ready for transfer, returning an ack signal to per1, then dma starting data transfer, recognizing that the transmission is configured in a linked list mode, obtaining first lli information, starting transmission according to the information, copying 16 bytes of data from a source address, indicating that there is a subsequent transmission when last=0, thus obtaining second lli information, starting transmission according to the information, copying 16 bytes of data from the source address, starting third data transfer by dma, and the like;
5) In step 4), after the transmission of the first lli data amount is completed, the valid signal is rewritten to 0 by dma to indicate that lli is invalid, at this time, dma generates a lli _req interrupt by synthesizing the signals of all parties, the interrupt will not report cpu, a certain register in dma can query the interrupt status, per1 can send a read command to poll the interrupt register through the protocol conversion module 1 and know the address of empty lli, and per1 sees lli _req as 1 to indicate that updating of a lli content is allowed for the next transmission;
6) Immediately in step 5), per1 needs to write a new transmission configuration into lli of the first address, per1 requests lli content to be written to slave1 connected with the first address, a user transmits the new configuration content to per1 through slave1, then the new configuration content is sent out by an AHB interface of per1, lli information is sent to dma through a protocol conversion module 2, and the lli information is written into mem through the protocol conversion module 2 for subsequent use;
7) When last=1 in ctrl field in lli indicates that this is the last transmission, dma will stop carrying after this data transfer and will not fetch or write lli any more, and send a finish signal to per1 to tell the end of the transmission, if data carrying is to be started again, per1 will pull up the req signal to dma again.
Preferably, both configurations in the step 1) pass through an APB interface of dmas, and the command sent by the cpu is an AXI signal, and is converted into the APB signal configuration dmas by the protocol conversion module 1.
Preferably, the specific configuration content of the first writing lli in the step 2) is as follows:
a) write_back_stat is written back after the data amount defined by lli is transmitted by dma, and indicates the result of the transmission, and cpu can read the address to know the transmission state;
b) The ctrl field contains all configuration information transmitted by dma, only two signals are concerned here, the last is 1 to indicate that the current transmission is the last, 0 to indicate that the current transmission is completed and the transmission is still completed, the llp field needs to be removed to obtain the next lli finger address, then the linked list information is obtained to start the next transmission, and valid is 1 to indicate that lli is effective;
c) llp is the next lli fetch address;
d) block transfer size are all 0xf, representing the data amount of the present data transmission.
Preferably, the steps 6) and 5) are performed simultaneously with the step 4), the step 4) is performed continuously, the steps 6) and 5) monitor lli _req at any time and update lli so as to transmit data all the time, once the step 4) finishes transmitting a data, lli _req is generated, and then steps 5) and 6) are performed, and thus, the processes lli1, lli2 and lli are all written twice.
Preferably, the protocol conversion module 1 mainly receives an instruction sent by the cpu, writes the instruction into the memory after decoding, configures the dma and the peripheral, the protocol type of an output port of the protocol conversion module 1 is not limited, the protocol conversion module 1 can accept a read-write access command of the peripheral per1 or per2, and transmits an APB/AHB instruction signal of the peripheral to an APB interface of the dma after decoding, so as to implement writing or reading of a dma register.
Preferably, the dma module supports a linked list transmission mode, and after receiving an instruction of peripheral write lli, the dma module can send lli information to the protocol conversion module 2 through an AXI interface, and route the information to the corresponding memory unit through the protocol conversion module 2.
Preferably, the protocol conversion module 2 is mainly a data transferring channel of dma, and the protocol type of the output interface is not limited, and can complete data transferring from peripheral to peripheral, from storage unit to storage unit, from peripheral to storage, from storage to peripheral, etc.
Preferably, the peripheral-to-peripheral data handling process is as follows:
the method comprises the steps that an AXI interface of dma initiates a read command and converts the read command into an AHB/APB command through a protocol conversion module 2 to be sent to a source peripheral, after read-back data is received, the data temporarily stores a dma, and simultaneously the dma can send the write command initiated by the AXI interface of dma to the destination peripheral through the protocol conversion module 2 to be converted into the AHB/APB command according to configuration to be sent to the destination peripheral, and the data is carried to the destination peripheral;
the data handling process from storage unit to storage unit is as follows:
and after receiving the read-back data, the data temporarily stores the dma fifo of the dma, and simultaneously the dma can send a write command to the AXI interface of the destination mem through the packing and unpacking of the protocol conversion module 2 according to configuration initiated by the AXI interface of the dma, and carry the data to the destination mem.
Preferably, the data handling process from the peripheral to the storage unit is as follows:
the method comprises the steps that an AXI interface of dma initiates a read command, the read command is converted into an AHB/APB instruction through a protocol conversion module 2 and is sent to a source peripheral, after read-back data is received, the data temporarily stores a dma, and simultaneously the dma can send the write command to an AXI interface of a destination mem after being packed and unpacked through the protocol conversion module 2 according to configuration by the AXI interface of the dma, and the data is carried to the destination mem;
the data handling process from the storage unit to the peripheral device is as follows:
and packaging and unpacking the AXI interface read command of the dma through the protocol conversion module 2, sending the package to an AXI interface of the source mem, temporarily storing the data in the fifo of the dma after receiving the read-back data, and simultaneously, converting the AXI interface initiated write command of the dma into an AHB/APB instruction through the protocol conversion module 2 according to configuration by the dma to send the AHB/APB instruction to the destination peripheral equipment, and carrying the data to the destination peripheral equipment.
(III) beneficial effects
Compared with the prior art, the application provides a lli dynamic writing method of a dma linked list mode, which has the following beneficial effects:
in the traditional dma linked list transmission mode, updating the linked list information of the dma can only be read and written by the cpu, and all lli needs to be configured before transmission starts, if the transmission data volume is relatively large, the memory unit for storing lli information is also quite considerable, the application can solve the problems, and does not need a large memory for storing lli information, and in the process of transferring data of the dma, the peripheral equipment initiates writing or reading operation to the dma through the bus module, and the dma updates lli information without participation of the cpu, so that the cpu is released to improve the cpu efficiency.
Drawings
FIG. 1 is a schematic diagram of a data structure of a conventional linked list transmission mode in the present application;
FIG. 2 is a block diagram of a chip application of the dma module of the present application;
FIG. 3 is a diagram showing a specific configuration of lli when first writing in the present application;
FIG. 4 is a diagram showing the configuration of a secondary write and last transfer lli according to the present application;
FIG. 5 is a flow chart of the dma extraction lli according to the present application.
Detailed Description
The technical solutions of the embodiments of the present application will be clearly and completely described below in conjunction with the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Referring to fig. 1-2, dma generally has four transmission modes, wherein one transmission mode is a linked list mode, the mode is based on the data structure of fig. 1, the linked list mode needs to write lli information, when the transmission data volume is large, lli occupies a large memory space, in order to solve the problem that cpu is required to continuously participate in updating lli when lli storage space is recycled, the application provides a lli dynamic writing method of the dma linked list mode, through a protocol conversion module 2, a decoding function of peripheral read/write signals accessing dma is added, a command of writing lli can be sent by any peripheral, the command is given to dma, dma through the protocol conversion module 2, and then lli information is written into a certain memory, the process is realized by updating lli information by the peripheral, so that cpu is liberated, the efficiency of cpu is effectively improved by updating lli, and lli by the peripheral when data is carried, and the specific operation is as follows:
preferably, the cpu configures the dma in a linked list transmission mode, configures the address of the first lli in the dma, and both configurations pass through the APB interface of the dma, and the command sent by the cpu is an AXI signal, and is converted into an APB signal configuration dma by the protocol conversion module 1.
For the cpu to configure a plurality of lli, specifically, an AXI write command is sent out through the cpu port, the write command is routed to the mem AXI port through the protocol conversion module 1, the information is written lli at a plurality of lli addresses respectively, and the specific configuration content of the first writing lli in step 2) can refer to fig. 3.
Wherein, a) write_back_stat is written back after the dma transmits the data volume defined by lli, which indicates the result of the transmission, cpu can read the address to know the transmission state; b) The ctrl field contains all configuration information transmitted by dma, only two signals are concerned here, the last is 1 to indicate that the current transmission is the last, 0 to indicate that the current transmission is completed and the transmission is still completed, the llp field needs to be removed to obtain the next lli finger address, then the linked list information is obtained to start the next transmission, and valid is 1 to indicate that lli is effective; c) llp is the next lli fetch address; d) block transfer size are all 0xf, representing the amount of data to be transferred for this time, a total of 16 data units need to be transferred (for simplicity of the scenario, the units here can be understood in terms of bytes), and as before this parameter is not of interest here, for simplicity, are configured to be a maximum of 16 bytes.
For the condition that the CPU configures the peripheral device per1 to send out a transmission request signal req, specifically, an AXI writing instruction is sent out by the CPU, and the AXI writing instruction is converted into the APB signal configuration per1 through the protocol conversion module 1.
Waiting for per1 to send a transmission request signal req to dm, dm confirming that the data is ready for transfer, returning an ack signal to per1, then dm starting data transfer, recognizing that the transfer is configured in linked list mode, obtaining the first lli information, starting transfer according to the information, copying 16 bytes of data from source address, needing to be described, starting digestion data after per1 obtaining data, when last=0, indicating that there is a subsequent transfer, thus obtaining the second lli information, starting transfer according to the information, copying 16 bytes of data from source address, it should be understood that assuming that 16 bytes of data for the last transfer are digested, there is no data loss problem in transferring data again to per1, dma starting third transferring data, and so on, needing to be described, source address source_addr of multiple transferring is discontinuous, the linked list mode has the advantage of flexible configuration of transmission parameters, in the above process, after the transmission of the first lli data amount is completed, the valid signal will be rewritten to 0 to indicate that lli is invalid, at this time, dma will synthesize all side signals (mainly the valid signal in ctrl domain of next lli, valid signal in this time, the signal req_configuration of the next lli requesting to continue to carry data) to generate a lli _req interrupt, this interrupt will not report cpu, a certain register in dma can query the interrupt status, per1 can send a read command to poll the interrupt register through protocol conversion module 1 and obtain the address of empty lli, per1 sees lli _req is 1 to indicate that it is allowed to update a lli content for next transmission, at this time, a new transmission configuration needs to be written into lli of the first address, per1 requests lli content to be written to slave1 connected to it, and the user transmits new configuration content to per1 through slave1, and then sends lli information to dma through protocol conversion module 2, and dma writes lli information to mem through protocol conversion module 2 for subsequent use by the AHB interface of per1.
It should be noted that, while the above process is performed synchronously, dma is continuously carrying data, lli _req is monitored and updated lli in real time so that transmission is performed all the time, lli _req is generated once dma finishes transmitting a data, the subsequent operation is performed, accordingly, lli1, lli2 and lli3 are written twice, please refer to fig. 4, when last=1 in ctrl field in lli indicates that this is the last transmission, dma stops carrying after transmitting the data and does not fetch or write lli content, and sends a finish signal to per1 to inform that transmission is finished, if data carrying is to be started again, per1 pulls up req signal to dma again.
The whole process realizes the data transfer from the discontinuous mem storage space to the per1, and the dma automatic work is realized by using less lli storage space, and CPU is not needed in the data transfer process.
In the method, the protocol conversion module 1 mainly receives an instruction sent by the cpu, writes the instruction into the memory after decoding, configures the dma and the peripheral, has no limitation on the protocol type of an output port of the protocol conversion module 1, can flexibly operate an AXI interface, an AHB interface, an APB interface and the like, has a function suitable for all the peripheral, can accept a read-write access command of the peripheral (for example, per1 and per2 in fig. 2), and transmits an APB/AHB instruction signal of the peripheral to the APB interface of the dma after decoding, thereby realizing writing or reading of a dma register.
The dma module supports a linked list transmission mode, and the dma has the following functions: after receiving the command of writing lli from the peripheral, lli information can be sent to the protocol conversion module 2 through the AXI interface, and the information can be routed and written to a corresponding memory unit (for example, mem & mem1 in fig. 2) through the protocol conversion module 2, wherein the protocol conversion module 2 is mainly a channel for dma to carry data, the protocol type of the output interface is not limited, and the interface can be compatible with the AXI interface, the AHB interface, the APB interface and the like, so that data carrying from the peripheral to the peripheral, from the storage unit to the storage unit, from the peripheral to the storage, to the peripheral and the like can be completed.
The data carrying process is as follows:
a) For data handling from the peripheral to the peripheral, an AXI interface of dma initiates a read command and converts the read command into an AHB/APB command through a protocol conversion module 2 and sends the AHB/APB command to the source peripheral, after receiving read-back data, the data temporarily stores a dma, and simultaneously the dma can initiate a write command according to configuration by the AXI interface of dma and convert the write command into the AHB/APB command through the protocol conversion module 2 and send the AHB/APB command to the destination peripheral, and the data is handled to the destination peripheral;
b) For data handling from storage unit to storage unit, the dma AXI interface read command is packed by the protocol conversion module 2 and unpacked and sent to the AXI interface of the source mem, after the read-back data is received, the data is temporarily stored in dma fifo, and simultaneously dma can initiate a write command according to configuration by the dma interface of dma, is packed by the protocol conversion module 2 and unpacked and sent to the AXI interface of the destination mem, and the data is handled to the destination mem;
c) Carrying data from the peripheral device to the storage unit, converting an AXI interface of the dma into an AHB/APB instruction through a protocol conversion module 2, sending the AHB/APB instruction to the source peripheral device, temporarily storing the data in a fifo of the dma after receiving the read-back data, and meanwhile, packaging and unpacking the data to an AXI interface of a destination mem according to configuration by the AXI interface of the dma, and carrying the data to the destination mem;
d) And (3) carrying data from the storage unit to the peripheral equipment, packaging an AXI interface read command of the dma through the protocol conversion module 2, unpacking and sending the read-back data to an AXI interface of the source mem, temporarily storing the data in a fifo of the dma after receiving the read-back data, and simultaneously, carrying out write command initiated by the AXI interface of the dma according to configuration, converting the write command into an AHB/APB instruction through the protocol conversion module 2 and sending the AHB/APB instruction to the target peripheral equipment, and carrying the data to the target peripheral equipment.
The following illustrates an application scenario, and the detailed scheme is described with a specific application scenario:
in fig. 2, when 96 bytes of data are required to be transferred from mem1 to per1, the data to be transferred from mem1 are stored in several non-continuous address spaces, only three non-continuous spaces are used for storing lli information, the total data amount to be transferred is 96 bytes, the maximum data amount to be transferred can be configured to be 16 bytes (the block_ts in lli can be configured to be more abundant, which is not the focus of attention here, and the application scene is simplified according to the maximum 16 bytes), then 6 lli are required to inform the source/destination address and the configuration information of dma transfer data, so that three lli storage spaces are respectively recycled for two times to provide corresponding transfer configuration information for dma, the first lli has a finger fetch address of 0x0000, the second block lli has a finger fetch address of 0x0100, and the third block lli has a finger fetch address of 0x0200.
The specific operation process is as follows:
1) The CPU configuration dma is in a linked list transmission mode, the index address of the first lli in the configuration dma is 0x0000, the two configurations are through an APB interface of the dma, a command sent by the CPU is an AXI signal, and the command is converted into the APB signal configuration dma through a protocol conversion module 1;
2) Three lli are configured by the cpu, specifically, an AXI write instruction is sent out by the cpu port, the write instruction is routed to the mem AXI port through the protocol conversion module 1, lli information is written into the three lli addresses respectively, and the specific configuration content of lli is shown in fig. 3;
4) Waiting for per1 to send a transmission request signal req to dm, dm confirming that data is ready for transfer, returning an ack signal to per1, then, dm starting data transfer, recognizing that the transmission is configured in a linked list mode, obtaining first lli information by removing address 0x0, starting transmission according to the first lli information, obtaining 16 bytes of data from source address 0x8000, copying to 0x9000 address (data is digested after per1 obtains data), obtaining second lli information by removing llp =0x0100 because last=0x0100 indicates that data is still transmitted, starting transmission according to the second lli information, obtaining 16 bytes of data from source address 0x8400, copying to 0x9000 address (assuming that 16 bytes of data carried last time are digested, and carrying data again to per1 will not have the problem of data loss), and in the same case, dma starting third data carrying;
5) In step 4), after the transmission of the first lli data amount is completed, the valid signal is rewritten to 0 by dma to indicate that lli is invalid, at this time, dma synthesizes all side signals (mainly transmits the written-back status, valid signal of ctrl field of next lli, signal req_configuration of per1 requesting to continue to carry data) to generate lli _req interrupt, this interrupt will not report cpu, a certain register in dma can query the interrupt status, per1 can issue a read command through protocol conversion module 1 to poll this interrupt register and obtain the address of empty lli, and per1 sees lli _req is 1 to indicate that updating of lli content is allowed for next transmission;
6) Following step 5), per1 needs to write a new transmission configuration to lli of the 0x0 address at this time, per1 requests lli content to be written to slave1 connected thereto, a user transmits a new configuration content to per1 through slave1, then sends lli information to dma via the protocol conversion module 2, dma writes this lli information to 0x0 address of mem via the protocol conversion module 2 for subsequent use, step 5) and step 6) are carried out simultaneously with step 4), step 4) uninterrupted carry data, step 5) and step 6) monitor lli _req and update lli at any time so that transmission is carried out all the time, lli _req is generated once step 4) has transmitted a piece of data, step 5) and step 6) are executed immediately, accordingly, lli, lli and lli are written twice, the values of which are as shown in fig. 4, and can be read again by a third field lli =dm 1, and finally the end of transmission of the data is notified that the transmission of the data is stopped, and if the transmission of the data to the slave 52 is completed, and the transmission of the data to the slave 52 is stopped at the end of the slave 1.
Referring to fig. 5, the order of the dma taking lli is shown in fig. 5, so that data is carried from discontinuous mem storage space to per1, dma automatic work is realized by using less lli storage space, and cpu participation is not needed in the process of carrying data.
Although embodiments of the present application have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the application, the scope of which is defined in the appended claims and their equivalents.
Claims (9)
1. The lli dynamic writing method of the dma linked list mode is characterized by comprising the following steps of:
1) CPU configures dma as a linked list transmission mode, and configures the address of the first lli in the dma;
2) The CPU configures a plurality of lli, particularly sends an AXI writing instruction through the CPU port, routes the writing instruction to the mem AXI port through the protocol conversion module 1, and writes lli information into a plurality of lli addresses respectively;
3) The CPU configures the condition that the peripheral device per1 sends out a transmission request signal req, specifically sends out an AXI writing instruction through the CPU, and converts the AXI writing instruction into an APB signal configuration per1 through the protocol conversion module 1;
4) Waiting for per1 to send a transmission request signal req to dma, dma confirming that data is ready for transfer, returning an ack signal to per1, then dma starting data transfer, recognizing that the transmission is configured in a linked list mode, obtaining first lli information, starting transmission according to the information, copying 16 bytes of data from a source address, indicating that there is a subsequent transmission when last=0, thus obtaining second lli information, starting transmission according to the information, copying 16 bytes of data from the source address, starting third data transfer by dma, and the like;
5) In step 4), after the transmission of the first lli data amount is completed, the valid signal is rewritten to 0 by dma to indicate that lli is invalid, at this time, dma generates a lli _req interrupt by synthesizing the signals of all parties, the interrupt will not report cpu, a certain register in dma can query the interrupt status, per1 can send a read command to poll the interrupt register through the protocol conversion module 1 and know the address of empty lli, and per1 sees lli _req as 1 to indicate that updating of a lli content is allowed for the next transmission;
6) Immediately in step 5), per1 needs to write a new transmission configuration into lli of the first address, per1 requests lli content to be written to slave1 connected with the first address, a user transmits the new configuration content to per1 through slave1, then the new configuration content is sent out by an AHB interface of per1, lli information is sent to dma through a protocol conversion module 2, and the lli information is written into mem through the protocol conversion module 2 for subsequent use;
7) When last=1 in ctrl field in lli indicates that this is the last transmission, dma will stop carrying after this data transfer and will not fetch or write lli any more, and send a finish signal to per1 to tell the end of the transmission, if data carrying is to be started again, per1 will pull up the req signal to dma again.
2. The method according to claim 1, wherein both configurations in step 1) pass through an APB interface of dma, and the command issued by the cpu is an AXI signal, and is converted into an APB signal configuration dma by the protocol conversion module 1.
3. The method for dynamically writing lli in the dma linked list mode according to claim 2, wherein the specific configuration contents of the first writing lli in the step 2) are as follows:
a) write_back_stat is written back after the data amount defined by lli is transmitted by dma, and indicates the result of the transmission, and cpu can read the address to know the transmission state;
b) The ctrl field contains all configuration information transmitted by dma, only two signals are concerned here, the last is 1 to indicate that the current transmission is the last, 0 to indicate that the current transmission is completed and the transmission is still completed, the llp field needs to be removed to obtain the next lli finger address, then the linked list information is obtained to start the next transmission, and valid is 1 to indicate that lli is effective;
c) llp is the next lli fetch address;
d) The blocktransfer size is 0xf, which indicates the data amount of the present data transmission.
4. A method of dynamically writing lli in a dma linked list mode according to claim 3, wherein said step 6) and step 5) are performed simultaneously with step 4), step 4) is performed with uninterrupted handling of data, step 6) and step 5) are performed at any time to monitor lli _req and update lli for transmission to continue, and once step 4) is performed with a data transfer, lli _req is interrupted, and then steps 5) and 6) are performed, whereby lli1, lli2 and lli3 are written twice.
5. The method according to any one of claims 1 to 4, wherein the protocol conversion module 1 mainly receives an instruction sent by cpu, writes the instruction into memory after decoding, configures dma and peripheral, the protocol type of the output port of the protocol conversion module 1 is not limited, and the protocol conversion module 1 can accept a read-write access command of the peripheral per1 or per2, and transmits an APB/AHB instruction signal of the peripheral to an APB interface of dma after decoding to implement writing or reading of a dma register.
6. The method according to any one of claims 1-4, wherein the dma module supports a linked list transmission mode, and the dma module receives an instruction for writing lli from a peripheral device and sends lli information to the protocol conversion module 2 via an AXI interface, and routes the information to the corresponding memory unit via the protocol conversion module 2.
7. The method according to any one of claims 1-4, wherein the protocol conversion module 2 is mainly a data transferring channel of dma, and the protocol type of the output interface is not limited, and it can complete data transferring from peripheral to peripheral, from storage unit to storage unit, from peripheral to storage, and from storage to peripheral.
8. The method of claim 7, wherein the peripheral-to-peripheral data handling process is as follows:
the method comprises the steps that an AXI interface of dma initiates a read command and converts the read command into an AHB/APB command through a protocol conversion module 2 to be sent to a source peripheral, after read-back data is received, the data temporarily stores a dma, and simultaneously the dma can send the write command initiated by the AXI interface of dma to the destination peripheral through the protocol conversion module 2 to be converted into the AHB/APB command according to configuration to be sent to the destination peripheral, and the data is carried to the destination peripheral;
the data handling process from storage unit to storage unit is as follows:
and after receiving the read-back data, the data temporarily stores the dma fifo of the dma, and simultaneously the dma can send a write command to the AXI interface of the destination mem through the packing and unpacking of the protocol conversion module 2 according to configuration initiated by the AXI interface of the dma, and carry the data to the destination mem.
9. The method of claim 7, wherein the data handling process from the peripheral device to the storage unit is as follows:
the method comprises the steps that an AXI interface of dma initiates a read command, the read command is converted into an AHB/APB instruction through a protocol conversion module 2 and is sent to a source peripheral, after read-back data is received, the data temporarily stores a dma, and simultaneously the dma can send the write command to an AXI interface of a destination mem after being packed and unpacked through the protocol conversion module 2 according to configuration by the AXI interface of the dma, and the data is carried to the destination mem;
the data handling process from the storage unit to the peripheral device is as follows:
and packaging and unpacking the AXI interface read command of the dma through the protocol conversion module 2, sending the package to an AXI interface of the source mem, temporarily storing the data in the fifo of the dma after receiving the read-back data, and simultaneously, converting the AXI interface initiated write command of the dma into an AHB/APB instruction through the protocol conversion module 2 according to configuration by the dma to send the AHB/APB instruction to the destination peripheral equipment, and carrying the data to the destination peripheral equipment.
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