CN114528238A - PCIE changes low time delay adaptive circuit of polymorphism of SATA - Google Patents
PCIE changes low time delay adaptive circuit of polymorphism of SATA Download PDFInfo
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- CN114528238A CN114528238A CN202210163115.7A CN202210163115A CN114528238A CN 114528238 A CN114528238 A CN 114528238A CN 202210163115 A CN202210163115 A CN 202210163115A CN 114528238 A CN114528238 A CN 114528238A
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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Abstract
The invention discloses a PCIE-SATA polymorphic low-delay self-adaptive circuit, which belongs to the field of integrated circuits and comprises a reset module, a clock module, a configuration module, a debugging module, a PCIE data receiving and processing module, an SATA data receiving and transmitting module and a rate self-adaptive module. The reset module is used for resetting the circuit; the clock module provides a working clock; the configuration module provides a configuration circuit function; the debugging module provides a debugging chip function; the PCIE data receiving and processing module realizes the data receiving, sending and processing functions of the PCIE; the SATA data processing module is used for SATA data processing; the SATA data transceiver module realizes the functions of transmitting and receiving SATA and PCIE data; the rate self-adaptive module automatically adjusts the transmission communication capacity of the PCIE after analyzing and operating the transmission rates of the PCIE and the SATA. The PCIE-SATA polymorphism low-delay self-adaptive circuit has polymorphism, low delay, self-adaptation, high channel, high bandwidth, multiple channels and real-time performance.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a polymorphism low-delay self-adaptive circuit for converting PCIE into SATA.
Background
Aiming at the problems that the traditional PCIE-SATA bridge chip has single function, the circuit function expansibility is not strong, the power of the traditional SATA bridge chip is higher, and the practical application scene is higher and higher, the invention designs a PCIE-SATA bridge circuit based on polymorphism low-delay self-adaption.
Disclosure of Invention
The invention aims to provide a polymorphism low-delay self-adaptive circuit for converting PCIE to SATA, which aims to solve the problems in the background technology.
In order to solve the above technical problem, the present invention provides a polymorphism low-delay adaptive circuit for converting PCIE to SATA, including:
the reset module is used for resetting the circuit;
the clock module is used for providing a working clock;
a configuration module providing a configuration circuit function;
the debugging module is used for providing a debugging chip function;
the PCIE data receiving and processing module is used for realizing the data receiving, sending and processing functions of the PCIE;
the SATA data processing module is used for processing SATA data;
the SATA data transceiver module realizes the functions of transmitting and receiving the data of SATA and PCIE,
and the rate self-adaptive module is used for automatically adjusting the transmission and communication capacity of the PCIE after analyzing and operating the transmission rates of the PCIE and the SATA.
Optionally, the reset module can reset the whole circuit, or reset other modules on the circuit separately; separately resetting other modules includes: the system comprises a reset PCIE data receiving and processing module, a reset SATA data receiving and sending module, a reset configuration module, a reset debugging module and a reset clock module.
Optionally, the basis for analyzing the transmission rate of the rate adaptive module is to reallocate the transmission rates of the PCIE and the SATA according to an actual situation of data communication of the whole circuit after the whole circuit operates for a period of time; the actual conditions comprise the number of SATA channels, PCIE transmission rate, SATA processing rate and SATA hard disk processing rate, and dynamic analysis is carried out on the actual conditions, namely re-analysis is carried out every period of time.
Optionally, the configuration module reads the peripheral storage device through the configuration bus, and reconfigures the circuit; the configuration contents provided by the configuration module comprise PCIE configuration coverage, SATA configuration coverage and reconfiguration of other resources mounted on the whole circuit; the configuration mode of the configuration module is realized by circuit register configuration or an internal signal mode.
Optionally, the configuration bus is a variety of bus protocols, and the bus protocols include: UART, CAN, USB, I2C, SSI, SPI, CAN mainstream bus protocol; the configuration bus selects one of the implementations according to the actual requirements of the circuit.
Optionally, the SATA data transceiver module and the PCIE data receiving and processing module accelerate data transmission and reception of SATA through low-latency design; the low-delay design specifically realizes the requirements by combining the buffer mode, data buffer ping-pong processing, pipeline technology and data bypass technology.
Optionally, the number of the SATA data transceiver modules may be from 1 to 32, and the number of the SATA data transceiver modules is determined according to actual design requirements of the circuit, and the SATA data transceiver modules have a main function of transmitting data received from the SATA data processing module to an assigned SATA hard disk; and the data returned from the SATA hard disk is sent to the SATA data receiving and sending module, and the SATA data receiving and sending module sends the data to the SATA data processing module.
The polymorphism low-delay self-adaptive circuit for converting PCIE into SATA provided by the invention has the following beneficial effects:
(1) by dynamically analyzing the speed conditions of PCIE and SATA, the self-adaptation of the circuit speed is realized, the power consumption of the circuit is reduced, and meanwhile, the circuit resources are fully utilized;
(2) the same circuit can realize different functions, the multi-state performance of the circuit is rich, and more attributes can be configured compared with the traditional circuit;
(3) the PCIE data channel is fully utilized, the circuit function is exerted, and the expansibility of the circuit SATA is effectively expanded;
(4) the method can be applied to application scenes with very high requirements on time sequence;
(5) the data communication capability is effectively improved, and the continuously improved data requirements are adapted.
Drawings
FIG. 1 is a schematic diagram of the principle structure of a PCIE-to-SATA polymorphic low-latency adaptive circuit provided by the present invention;
fig. 2 is a schematic diagram of a specific implementation structure of a PCIE-to-SATA polymorphic low-latency adaptive circuit according to the present invention.
Detailed Description
The following describes a polymorphism low-latency adaptive circuit for PCIE to SATA according to the present invention in further detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
The invention provides a PCIE-SATA polymorphism low-delay self-adaptive circuit which comprises a reset module, a clock module, a configuration module, a debugging module, a PCIE data receiving and processing module, an SATA data receiving and transmitting module and a rate self-adaptive module.
The reset module is used for resetting the whole chip, and can reset the whole circuit and also can reset other modules on the circuit independently. Separately resetting other modules includes: the system comprises a reset PCIE data receiving and processing module, a reset SATA data receiving and sending module, a reset configuration module, a reset debugging module and a reset clock module. The selectable reset module needs to select a reset module according to actual circuit requirements.
The clock module provides the clock signal of the circuit, the clock signal is provided for each module through the PLL frequency divider, and after the clock signal is provided, the circuit can normally run logic functions. The clock module design refers to the requirements of matching SATA channel number, PCIE transmission rate, SATA processing rate, SATA hard disk processing rate and the like.
The configuration module can achieve circuit polymorphism by configuring internal functions of the circuit. The configuration module can select a module for configuring the circuit to realize various functions of the circuit. The configuration module optionally includes: the system comprises a clock configuration module, a reset configuration module, a debugging configuration module, a PCIE data receiving and processing module, an SATA data processing module and an SATA data receiving and transmitting module. The selectable configuration module selects the configured module according to the actual circuit requirement. The configuration module can be divided into two configuration modes, wherein one mode is that the circuit actively receives configuration data through a configuration bus; one is for the circuit to passively receive configuration data over a configuration bus. After the configuration module receives the configuration data, the corresponding module is configured according to the configuration data. The configuration module selects one of the two modes to realize according to the actual circuit requirements.
The configuration bus may select various bus protocols, including: mainstream bus protocols such as UART, CAN, USB, I2C, SSI, SPI, CAN and the like; the configuration bus can select one of the implementations according to the actual requirements of the circuit.
The debugging module can debug the internal functions of the circuit. The debugging module can select whether the debugging module needs to be added in the circuit according to the actual requirements of the circuit. The debugging module can choose to add the content of the module needing debugging. The debugging module optionally comprises: the system comprises a debugging reset module, a debugging clock module, a debugging configuration module, a debugging PCIE data receiving and processing module, a debugging SATA data processing module and a debugging SATA data receiving and transmitting module. The optional debugging module needs to select a debugging module according to the actual circuit requirement.
The circuit receives and transmits data through the PCIE bus. The PCIE data receiving and processing module acquires PCIE data from the PCIE bus and performs corresponding operation on the data according to the type of the PCIE data. After the PCIE data receiving and processing module acquires data from the SATA part, the data is processed according to the data type, and a standard business logic protocol is used for processing a PCIE-to-SATA interface.
And the SATA data processing module processes the data according to the data type after the SATA part receives the data processing module sent by the PCIE, and sends the data to the formulated SATA data channel respectively according to the data channel requirement. And after the SATA data processing module receives the data sent by the SATA data receiving and sending module, the data is processed and sent to the PCIE data receiving and processing module. The SATA data processing module processes the SATA to PCIE interfaces using standard business logic protocols.
The number of the SATA data transceiver modules can be from 1 to 32, the number of the SATA data transceiver modules is determined according to the actual design requirements of the circuit, and the SATA data transceiver modules have the main function of sending data received from the SATA data processing module to an appointed SATA hard disk; and the data returned from the SATA hard disk is sent to the SATA data receiving and sending module, and the SATA data receiving and sending module sends the data to the SATA data processing module.
The rate self-adaptive module is used for automatically adjusting the transmission communication capacity of the PCIE and the SATA after analyzing and operating the transmission rates of the PCIE and the SATA. It is necessary to select whether the function of the rate adaptation module needs to be selected according to the actual requirements of the circuit.
When the rate adaptive module is bypassed (bypass) in the circuit design, the circuit needs to combine the read-write upstream and downstream rates of the SATA hard disk, the SATA bus rate and the PCIE bus rate to select the SATA protocol version, the PCIE protocol version and the PCIE link width. The rate transmission of the PCIE exceeds the data processing transmission requirement of the SATA controller.
The invention provides a PCIE-SATA polymorphism low-delay self-adaptive circuit, which comprises a reset module, a clock module, a configuration module, a debugging module, a PCIE data receiving and processing module, an SATA data receiving and transmitting module and a rate self-adaptive module as shown in figure 1.
In this embodiment, the reset module includes a reset whole circuit, and the circuit register controls the separate reset debugging module, the separate reset PCIE data receiving and processing module, the separate reset SATA data processing module, and the separate reset SATA data transceiver module.
In this embodiment, the clock module is provided for the PCIE data receiving and processing module, the SATA data processing module, and the SATA data transceiving module. The configuration module is provided with the SATA data processing module to modify the functions of SATA such as transmission rate, the configuration SATA data transceiver module is provided with the SATA transceiving channels, and the configuration rate self-adaptive module is provided with the functions of self-adaptive module opening and closing.
The configuration mode of the configuration module, in this embodiment, the circuit actively receives configuration data via a configuration bus. The configuration bus selects the I2C bus protocol. The debugging module is used for debugging the configuration module and checking whether the configuration register is changed or not through the debugging configuration circuit.
When the circuit of the PCIE data receiving and processing module is started, the transmission rate of the PCIE is 2.5Gbps, the link width is x8, and the processing module processes the interface from the PCIE to the SATA by using a standard service logic protocol. The PCIE data receiving and transmitting low-delay design realizes the low-delay requirement by combining the cache mode data bypass technology and the application.
The SATA data processing module is used for processing SATA to PCIE interfaces for a standard service logic protocol. The SATA data transceiver module has 8, and the SATA data transceiver module and the SATA hard disk use standard SATA protocol for communication. When the circuit is started, the SATA transmission rate is 3Gbps, and the bandwidth is x 1. In the embodiment, the low latency requirement is realized by a cache mode technology.
The rate adaptation module, in this embodiment, is turned on. When the adaptive module is turned off by the configuration module, it is the adaptive module that is bypassed (bypass), and in this embodiment, when the adaptive module is bypassed, the transmission rate of PCIE is 5Gbps and the link width is x 8. The number of the SATA data transceiver modules is 8, the transmission rate is 3Gbps, and the link width is x 1.
Referring to fig. 2, in the data connection diagram of a broadband signal in the embodiment, the reset module may reset the whole circuit, and the reset module is connected to the debugging module, the PCIE data receiving and processing module, the SATA data processing module, and the SATA data transceiver module; the clock module provides clock signals for the PCIE data receiving and processing module, the SATA data processing module and the SATA data receiving and sending module; the debugging module is connected with the configuration module; the configuration module is connected with the SATA data processing module and the SATA data receiving and transmitting module; the circuit actively receives configuration data through a configuration I2C bus protocol; when the circuit is started, the PCIE uses 5Gbps rate, the link width is x8 to carry out data communication, and the PCIE data processing module uses a standard business logic protocol to process a PCIE-to-SATA interface; the SATA data processing module processes an SATA-to-PCIE interface for a standard service logic protocol, and the SATA data transceiver module and the SATA hard disk are communicated by using the standard SATA protocol; when the circuit is started, 8 SATA data transceiver modules are provided, wherein the SATA transmission rate is 3Gbps, and the link width is x 1; when the circuit is started, the self-adaptive module is started.
The polymorphism low-delay self-adaptive circuit for PCIE-SATA conversion is applied to actual measurement:
the circuit realizes polymorphism through the configuration module, and realizes the functions of closing part of SATA channels and switching on and off the self-adaptive module.
The circuit completes the verification of high channel, high bandwidth, multiple channels and real-time property through large data volume pressure test, the channel realizes low time delay, the signal quality is good, and the circuit has higher sensitivity and resolution.
The circuit opens the self-adaptive module, and the self-adaptive attribute of the circuit is verified in a way of adding the number of the paths. The circuit realizes that the PCIE changes the transmission rate, and the test result shows that the circuit meets the requirement.
According to the method for expanding the SATA controller through the PCIE high-speed bus, the data flux and bandwidth requirements of SATA multi-channel are perfectly met through the PCIE high flux and the high bandwidth attribute, and the method is effectively suitable for relevant application scenes; meanwhile, a rate self-adaptive mode is innovatively used for solving the problem that the rates of the SATA data and the PCIE data are not matched due to various factors in actual operation, the rate self-adaptation saves circuit resources, reduces the power consumption of the circuit, and realizes circuit polymorphism through a configuration module, wherein the circuit polymorphism comprises functions of data channel expansion and the like. The PCIE-SATA polymorphism low-delay self-adaptive circuit has the following characteristics: polymorphism, low latency, self-adaptation, high channel, high bandwidth, multiple channels, real-time.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (7)
1. A PCIE-SATA polymorphism low-delay adaptive circuit is characterized by comprising:
the reset module is used for resetting the circuit;
the clock module is used for providing a working clock;
a configuration module providing a configuration circuit function;
the debugging module is used for providing a debugging chip function;
the PCIE data receiving and processing module is used for realizing the data receiving, sending and processing functions of the PCIE;
the SATA data processing module is used for processing SATA data;
the SATA data transceiver module realizes the functions of transmitting and receiving SATA and PCIE data;
and the rate self-adaptive module is used for automatically adjusting the transmission and communication capacity of the PCIE after analyzing and operating the transmission rates of the PCIE and the SATA.
2. The polymorphism low-delay adaptive circuit for PCIE-to-SATA according to claim 1, wherein the reset module can reset the whole circuit or reset other modules on the circuit separately; separately resetting other modules includes: the system comprises a reset PCIE data receiving and processing module, a reset SATA data receiving and sending module, a reset configuration module, a reset debugging module and a reset clock module.
3. The PCIE-to-SATA polymorphism low-latency adaptive circuit of claim 1, wherein the analysis of the transmission rate of the rate adaptive module is based on reallocating the transmission rates of PCIE and SATA according to the actual data communication situation of the whole circuit after the whole circuit is operated for a period of time; the actual conditions comprise the number of SATA channels, PCIE transmission rate, SATA processing rate and SATA hard disk processing rate, and dynamic analysis is carried out on the actual conditions, namely re-analysis is carried out every period of time.
4. The polymorphism low-latency self-adaptive circuit for PCIE-to-SATA according to claim 1, wherein the configuration module reads the peripheral storage device through a configuration bus and reconfigures the circuit; the configuration contents provided by the configuration module comprise PCIE configuration coverage, SATA configuration coverage and reconfiguration of other resources mounted on the whole circuit; the configuration mode of the configuration module is realized by circuit register configuration or an internal signal mode.
5. The polymorphism low-latency self-adaptive circuit for PCIE-SATA according to claim 4, wherein the configuration bus is various bus protocols, and the bus protocols include: UART, CAN, USB, I2C, SSI, SPI, CAN mainstream bus protocol; the configuration bus selects one of the implementations according to the actual requirements of the circuit.
6. The PCIE-to-SATA polymorphism low-latency adaptive circuit of claim 1, wherein the SATA data transceiver module and the PCIE data receiving and processing module accelerate SATA data transmission and reception through low-latency design; the low-delay design specifically realizes the requirements by combining the buffer mode, data buffer ping-pong processing, pipeline technology and data bypass technology.
7. The PCIE-to-SATA polymorphism low-delay self-adaptive circuit of claim 1, wherein the number of SATA data transceiver modules is from 1 to 32, the number of SATA data transceiver modules is determined according to the actual design requirements of the circuit, and the main function of the SATA data transceiver modules is to send data received from the SATA data processing module to a designated SATA hard disk; and the data returned from the SATA hard disk is sent to the SATA data transceiver module, and the SATA data transceiver module sends the data to the SATA data processing module.
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| CN202210163115.7A CN114528238A (en) | 2022-02-22 | 2022-02-22 | PCIE changes low time delay adaptive circuit of polymorphism of SATA |
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| CN202210163115.7A CN114528238A (en) | 2022-02-22 | 2022-02-22 | PCIE changes low time delay adaptive circuit of polymorphism of SATA |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115048327A (en) * | 2022-06-14 | 2022-09-13 | 中国电子科技集团公司第五十八研究所 | PCIE-SATA (peripheral component interface express) bridge chip |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105335326A (en) * | 2015-10-10 | 2016-02-17 | 广州慧睿思通信息科技有限公司 | PCIE-SATA interface array device based on FPGA |
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- 2022-02-22 CN CN202210163115.7A patent/CN114528238A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105335326A (en) * | 2015-10-10 | 2016-02-17 | 广州慧睿思通信息科技有限公司 | PCIE-SATA interface array device based on FPGA |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115048327A (en) * | 2022-06-14 | 2022-09-13 | 中国电子科技集团公司第五十八研究所 | PCIE-SATA (peripheral component interface express) bridge chip |
| CN115048327B (en) * | 2022-06-14 | 2024-03-22 | 中国电子科技集团公司第五十八研究所 | Bridge chip for converting PCIE into SATA |
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