CN107517170A - Redundant system and splicing system for polymorphic type, multi tate baseband signal - Google Patents

Redundant system and splicing system for polymorphic type, multi tate baseband signal Download PDF

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Publication number
CN107517170A
CN107517170A CN201710643016.8A CN201710643016A CN107517170A CN 107517170 A CN107517170 A CN 107517170A CN 201710643016 A CN201710643016 A CN 201710643016A CN 107517170 A CN107517170 A CN 107517170A
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China
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signal
data
clock
module
input
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CN201710643016.8A
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Chinese (zh)
Inventor
胡运辉
董叱风
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Guangdong In Sea Of Clouds Technology Co Ltd
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Guangdong In Sea Of Clouds Technology Co Ltd
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Priority to CN201710643016.8A priority Critical patent/CN107517170A/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0262—Arrangements for detecting the data rate of an incoming signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0006—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/028—Arrangements specific to the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0292—Arrangements specific to the receiver end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/06—Notations for structuring of protocol data, e.g. abstract syntax notation one [ASN.1]

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Computer Security & Cryptography (AREA)
  • Quality & Reliability (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

The present invention relates to base band signal transmission technical field, more particularly to a kind of it is used for polymorphic type, the redundant system and splicing system of multi tate baseband signal.Redundant system includes：16 input interfaces, signal gating circuit, decoding circuit, 16 buffers, serial-parallel conversion circuit, multi tate Auto-matching module, signal condition detection module, ARM controller, data framing module, signal multiplexing module, signal checking module, electro-optical conversion circuit etc..Splicing system includes：Electro-optical conversion circuit, clock and data recovery module, parallel descrambling module, the De-mapping modules of STM 1, VC4 demappings, C4 demappings, signal Demultiplexing module, clock recovery module, DDS circuit etc..Redundant system of the present invention, splicing system are easy to signal to transmit and the maintenance and wiring of equipment different type, the unitized processing of the baseband signal of speed.

Description

Redundant system and splicing system for polymorphic type, multi tate baseband signal
Technical field
The present invention relates to base band signal transmission technical field, more particularly to one kind to be used for polymorphic type, multi tate baseband signal Redundant system and splicing system.
Background technology
As electronic communication continues to develop, signal of communication species, quantity are continuously increased, signal specification from speed it is low, Species is few to speed is high, the direction more than species is developed., it is necessary in face of all size, various speed in Integrated Service Digital Network believes computer room Signal, connects up during deployment facility extremely complex, if the control for wanting to reach to certain signal is kept, generally requires to turn by multiple signal Connect, fault rate is high, is unfavorable for safeguarding；And between various kinds of equipment be pure lead connection, keep it in the control up to pair signals Before, panorama monitoring can not be realized to signal, it is difficult to meet to grasp various types of signal rule, situation etc. totally, and be unfavorable for a line The regular maintenance of personnel.
The content of the invention
In view of the above-mentioned deficiencies in the prior art, it is an object of the present invention to provide a kind of for polymorphic type, multi tate baseband signal Redundant system, be advantageous to the uniform transmission of signal, be easy to plant maintenance and wiring.
Another object of the present invention is to：Tap processing can be carried out for multiplexed signal, all kinds of baseband signals are reduced.
A kind of to be used for polymorphic type, the redundant system of multi tate baseband signal, it includes：
16 input interfaces, including clock data interface and line code interface；
Signal gating circuit, for gating one of input interface as signal input interface；
Decoding circuit, when selecting line code input, decoding circuit becomes clock data after the line code of input is decoded；
16 buffers, it is corresponding with signal input interface, after being respectively used to clock data or the line code decoding of storage input Data；
Serial-parallel conversion circuit, the data flow of serial input is subjected to serioparallel exchange, is converted into 8bit parallel data stream；
Speed and state detection module, the speed and signal work shape of the input signal received for detecting each input interface State；
ARM control modules, monitor the speed and working condition of input signal, input signal types selection, input signal gating and Input signal edge is set；
Data framing module, parallel data is formed into GFP data frames, while GFP data frames carrying input signal speed, state etc. Information；
Multiplex circuit, GFP data frames are multiplexed to C4 containers, and C4 container mappings re-map into VC4 virtual containers, VC4 virtual containers The signal of STM-1 frame formats.
When detecting input signal speed, when speed and state detection module are using 155.52MHz system clock as reference Clock, all counted for every road input signal with a counter N1, counter N is also used with reference to clockSCounted, it is per second Counter NSA pulse is sent, counter N1 numerical value is read as the real time rate of input signal by excitation of pulse.
Buffer includes a two-port RAM, shares 16 two-port RAMs；Each two-port RAM is divided into two Bank wheels Stream switching, when Bank data are full, it is data cached to be switched to another Bank, while puts corresponding flag bit, etc. Treat state machine poll.
Parallel scrambling module, it is G (X)=X that the electric signal for the STM-1 frame formats to generation, which carries out multinomial,7+X6+ 1 Parallel scrambling processing.
GFP data frames include core head and payload field two parts, and wherein core head is wrong by payload length instruction and core head Verification composition by mistake, payload length represent that payload field byte is the byte of fixed value 252, and Length Indication and error checking are also represented by data Synchronous head is reported, the generator polynomial of core head error checking is G (x)=X16+X12+X5+1；Payload field is by port numbers, equipment sequence Number, speed instruction and the part of payload information domain four composition, port numbers represent the port numbers of the input interface of institute multiplexed signal, take 1 byte, equipment Serial Number represent input signal source numbering, take 2 bytes；Speed instruction represents the real velocity of this signal, Output clock is produced for rear end drop set, takes 4 bytes；The information of payload information domain representation this frame carrying, takes 245 words Section.
A kind of baseband signal splicing system, it includes：
Photoelectric switching circuit, for being changed to STM-1 optical signals, form electric signal；
Clock and data recovery module, for electrical signal data to be converted into clock data；
Frame synchronization module；Position STM-1 data frame heads；
Parallel descrambling module, remove the scrambler in clock data；
STM-1 De-mapping modules, demapping is carried out to STM-1 signals, generates VC4 signal datas；
VC4 demappings, to VC4 signal data demappings, generate C4 container datas；
C4 demappings, to C4 container data demappings, generate GFP data frames；
Signal Demultiplexing module, extract the information such as baseband signal speed, working condition in GFP data frame formats；
Clock recovery module, code quick-recovery and chock smotthing are carried out to baseband signal；
DDS circuit, for entering Mobile state adjustment to signal rate.
Beneficial effects of the present invention：Redundant system of the present invention, splicing system are unified to different type, the baseband signal of speed Change format analysis processing, be easy to the transmission of signal and the maintenance of equipment and wiring.
Brief description of the drawings
Fig. 1 is redundant system schematic flow sheet.
Fig. 2 is GFP data frame formats.
Fig. 3 is STM-1 frame structures.
Fig. 4 is splicing system schematic flow sheet.
Embodiment
The present invention is described in detail below in conjunction with accompanying drawing, as shown in Figures 1 to 4.
Embodiment：A kind of to be used for polymorphic type, the redundant system of multi tate baseband signal, it includes：
16 input interfaces, input interface are divided into clock data interface or line code input interface；
Signal gating circuit, for gating one of input interface as signal input interface；
Line code decoding circuit, when selecting line code input, the line code of input is reverted to clock data mode by decoding circuit； Line code includes：E1、T1.
16 buffers, are correspondingly arranged with input interface, are respectively used to after storing the clock data of input, line code decoding Data；
Serial-parallel conversion circuit, for carrying out serioparallel exchange to the signal in buffer, clock data, line code solution in buffer Data after code are transformed into 8bit parallel data；
Speed and state detection module, for detecting the information such as input signal speed, state；
ARM control modules, monitor the speed and working condition of input signal, input signal types selection, input signal gating；
Data framing module, parallel data is formed into GFP data frames, while GFP data frames carrying input signal speed, state etc. Information；
Multiplex circuit, GFP data frames are multiplexed to C4 containers, and C4 container mappings re-map into VC4 virtual containers, VC4 virtual containers The signal of STM-1 frame formats.
In the technical program, 16 road clock datas or line code are received by input interface；ARM control circuit control inputs Signal behavior, input data is uniformly processed, is generated after parallel-serial conversion and form GFP data frames, buffer corresponding to deposit It is interior；State machine poll buffer, when there is data output, the data output in state machine control buffer；Speed and state inspection Survey module to detect the speed and state of signal, and status information is inserted into the relevant position of GFP data frames；By GFP Data frame is multiplexed to C4 volumetric standards, and then C4 signals are mapped, and makes 150.336Mbps VC4 virtual containers； The 155.52Mbps electric signals of STM-1 frame formats are become on VC4 plus Administrative Unit Pointer and section overhead.
When detecting input signal speed, when speed and state detection module are using 155.52MHz system clock as reference Clock, all counted for every road input signal with a counter N1, counter N is also used with reference to clockSCounted, it is per second Counter NSA pulse is sent, counter N1 numerical value is read as the real time rate of input signal by excitation of pulse.
Buffer includes a two-port RAM, shares 16 two-port RAMs；Each two-port RAM is divided into two Bank wheels Stream switching, when Bank data are full, it is data cached to be switched to another Bank, while puts corresponding flag bit, etc. Treat state machine poll.
GFP data frames are multiplexed to C4 volumetric standards and form C4 signals, and C4 signals carry out mapping as 150.336Mbps's VC4 virtual containers；The 155.52Mbps telecommunications of STM-1 frame formats is become plus Administrative Unit Pointer and section overhead on VC4 Number.
Parallel scrambling module, it is G (X)=X that the electric signal for the STM-1 frame formats to generation, which carries out multinomial,7+X6+ 1 Parallel scrambling processing.
GFP data frames include core head（corehead）With payload field two parts, wherein core head is indicated by payload length （2 bytes）With core head error checking（2 bytes）Composition, payload length represent that payload field byte is the byte of fixed value 252, length Instruction and error checking are also represented by datagram synchronous head, core head error checking（CRC-16）Generator polynomial be G (x)=X16+ X12+X5+1；Payload field is made up of port numbers, equipment Serial Number, speed instruction and the part of payload information domain four, and port numbers represent institute The port numbers of multiplexed signal, take 1 byte, and equipment Serial Number represents input signal source numbering, takes 2 bytes；Speed indicates The real velocity of this signal is represented, output clock is produced for rear end drop set, takes 4 bytes；Payload information domain representation sheet The information of frame carrying, takes 245 bytes.
Input data is uniformly converted to TTL signal, after serioparallel exchange, generates GFP data frames, realizes that input data is returned One change is handled, and is easy to the transmission, exchange and tap of data.The core head of GFP data frames records the length of each signal, payload field The status informations such as carrying signal source, input slogan, equipment Serial Number, signal rate.
A kind of baseband signal splicing system, it includes：
Photoelectric switching circuit, for being changed to STM-1 optical signals, form electric signal；
Clock and data recovery module, for electrical signal data to be converted into clock data；
Frame synchronization module；Position STM-1 data frame heads；
Parallel descrambling module, remove the scrambler in clock data；
STM-1 De-mapping modules, demapping is carried out to STM-1 signals, generates VC4 signal datas；
VC4 demappings, to VC4 signal data demappings, generate C4 container datas；
C4 demappings, to C4 container data demappings, generate GFP data frames；
Signal Demultiplexing module, extract the information such as baseband signal speed, working condition in GFP data frame formats；
Clock recovery module, code quick-recovery and chock smotthing are carried out to baseband signal；
DDS circuit, for entering Mobile state adjustment to signal rate.
Splicing system is the contrary operation of redundant system, and the 155.52Mbps optical signals of STM-1 frame formats are converted into clock After data, by the step such as frame synchronization, parallel descrambling, STM-1 demappings, justification, VC4 demappings, it is converted into 149.76Mbps C4 signals；After C4 signal demappings, code quick-recovery and chock smotthing are carried out to every road output signal；Pass through control DDS chips processed, the clock after producing smoothly, the output clock as 16 roadbed band signals；ARM controller is believed by reading each road Number status information, and shown on liquid crystal touch screen, panorama monitoring server can also be transmitted to by network.
Above content is only presently preferred embodiments of the present invention, for one of ordinary skill in the art, according to the present invention's Thought, there will be changes, this specification content should not be construed as to the present invention in specific embodiments and applications Limitation.

Claims (7)

1. for polymorphic type, the redundant system of multi tate baseband signal, it is characterised in that：It includes：
16 input interfaces, including clock data interface and line code interface；
Signal gating circuit, for gating one of input interface as signal input interface；
Decoding circuit, when the input interface of gating is line code interface, the line code of input is decoded into clock number by decoding circuit According to form；
16 buffers, are correspondingly arranged with input interface, are respectively used to clock data, the decoded number of line code of storage input According to；
Serial-parallel conversion circuit, for carrying out serioparallel exchange to the signal in buffer, clock data, line code solution in buffer Data after code are transformed into 8bit parallel data；
Speed and state detection module, the speed and signal work shape of the input signal received for detecting each input interface State；
ARM controller, receive the speed and signal working condition of input signal, and the gating of control signal gating circuit；
Data framing module, parallel data framing is formed into GFP data frames, while by the input signal corresponding to parallel data Speed and signal condition are inserted into the relevant position of GFP data frames；
Multiplex circuit, GFP data frames are multiplexed to C4 containers, and C4 container mappings re-map into VC4 virtual containers, VC4 virtual containers The signal of STM-1 frame formats.
2. according to claim 1 be used for polymorphic type, the redundant system of multi tate baseband signal, it is characterised in that：Speed And state detection module detect input signal speed when, using 155.52MHz system clock as reference clock, for every road Input signal is all counted with a counter Ns, and counter N is also used with reference to clock200Counted, every 1/100 second with public affairs Formula f=(Ns/ N200) * 200Mbps calculate the speed of every road signal, often complete counter O reset after once calculating.
3. according to claim 2 be used for polymorphic type, the redundant system of multi tate baseband signal, it is characterised in that：Caching Device includes a two-port RAM, shares 16 two-port RAMs；Each two-port RAM is divided into two Bank and switched in turn, when one When individual Bank data are full, it is data cached to be switched to another Bank, while puts corresponding flag bit, waits ARM controller Poll, when there are data to swap, the data of the Bank are exported, and serioparallel exchange is carried out to the data and is multiplexed to C4 marks Quasi- container.
4. according to claim 3 be used for polymorphic type, the redundant system of multi tate baseband signal, it is characterised in that：Including Parallel scrambling module, it is G (X)=X that the electric signal for the STM-1 frame formats to generation, which carries out multinomial,7+X6+ 1 parallel scrambling Processing.
5. according to claim 4 be used for polymorphic type, the redundant system of multi tate baseband signal, it is characterised in that：GFP numbers Include core head and payload field two parts according to frame, wherein core head is made up of payload length instruction and core head error checking, only Lotus length represents that payload field byte is the byte of fixed value 252, and Length Indication and the error checking of core head represent datagram synchronous head, The generator polynomial of core head error checking is G (x)=X16+X12+X5+1；Payload field is referred to by port numbers, equipment Serial Number, speed To show and formed with the part of payload information domain four, port numbers represent the port numbers of the input interface of institute's multiplexed signal, take 1 byte, if Standby sequence number represents input signal source numbering, takes 2 bytes；Speed instruction represents the real velocity of this signal, for rear end Drop set produces output clock, takes 4 bytes；The information of payload information domain representation this frame carrying, takes 245 bytes.
6. baseband signal splicing system, its feature includes：
Electro-optical conversion circuit, for the electric signal of STM-1 forms to be converted into optical signal；
Clock and data recovery module, for electrical signal data to be converted into clock data；
Parallel descrambling module, remove the scrambler in clock data；
STM-1 De-mapping modules, demapping is carried out to STM-1 signals, generates VC4 signal datas；
VC4 demappings, to VC4 signal data demappings, generate C4 container datas；
C4 demappings, to C4 container data demappings, generate GFP data frames.
7. baseband signal splicing system according to claim 6, its feature also include：DDS circuit, for signal rate Enter Mobile state adjustment.
CN201710643016.8A 2017-07-31 2017-07-31 Redundant system and splicing system for polymorphic type, multi tate baseband signal Pending CN107517170A (en)

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Application publication date: 20171226