CN1812315A - Multi-channel data signal processing method and apparatus - Google Patents
Multi-channel data signal processing method and apparatus Download PDFInfo
- Publication number
- CN1812315A CN1812315A CNA2005100330267A CN200510033026A CN1812315A CN 1812315 A CN1812315 A CN 1812315A CN A2005100330267 A CNA2005100330267 A CN A2005100330267A CN 200510033026 A CN200510033026 A CN 200510033026A CN 1812315 A CN1812315 A CN 1812315A
- Authority
- CN
- China
- Prior art keywords
- signal
- frame
- bus
- module
- data signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Time-Division Multiplex Systems (AREA)
Abstract
This invention is a kind of multiplex data signals processing method and equipment which relates to digital message transmission. It concludes the following steps: A, multi-line data signals are received; B, the multiplex data signals are respectively undertaken the packaging process to generate data frames. The said data frames contain the corresponding channel identifications. C, through velocity adaptation, the data frames output frame signal with fixed bandwidth. D, the said frame signals are undertaken bus feed-through process, after which are multiplexed to a serial bit stream signals for transmission; E, the said signals are transmitted to the receiving end for corresponding demultiplexing process. The parallel bus signals are generated; F, the bus signals are separated into groups. According to frame header searching consequence and channel identification of the bus frame signals, each line data signals are separated and transmitted to the data port corresponded to the channel identification.
Description
Technical field
The present invention relates to the transmission of digital information, relate in particular to a kind of multi-channel data signal processing method and device.
Background technology
Current local area network (LAN) adopts the Ethernet construction mostly, and Ethernet has that price is low, reliability is high, extensibility is good, be easy to advantages such as management, becomes a kind of configuration technology widely.
The Ethernet transmission rate has 10Mbps, 100Mbps, three kinds of speed of 1000Mbps, and ten thousand mbit ethernets are large-scale application not as yet.In these three kinds of Ethernets were used, 10Mbps, 100Mbps Ethernet were mainly used in occasions such as short distance interconnection, desktop communication, compunication.Current main flow router mainly provides gigabit ethernet interface, widespread deployment in local area network (LAN), and further expand to metropolitan area network and wide area network application.
In the application of metropolitan area network and wide area network, adopt gigabit Ethernet GE transmission broadband business to become main flow.The mixed network's mode of router and transmission equipment has accounted for greatly in the network application.Therefore main 2.5Gbps and the 10Gbps line speed of using in the present transmission equipment, need to solve and how to utilize transmission bandwidth effectively to carry Ethernet service, especially is directed to the GE business that is applied at metropolitan area network and wide area network.
In addition, the expansion of storage networking also is a trend of present network development, as application needs such as storage backup, storage integrations storage service is expanded by wide area network, require the storage service of transmission equipment carrying to comprise as optical-fibre channel (FC:Fibre Channel), business system connection (ESCON:Enterprise System Connection), optical fiber connection (FICON:Fiber Connection), simultaneously, transmission network also faces the demand of carrying video traffic such as digital video broadcasting (DVB:Digital VideoBroadcasting).
In the prior art, be example with multichannel GE, mainly adopt SDH (Synchronous Digital Hierarchy) SDH/SONET synchronous multiplexing mode to realize that multichannel GE converges in 2.5G or the 10G line speed, in this way carrying GE business in transmission network.Main processing procedure is, the GE business is carried out encapsulation process, can adopt general frame forming to handle (GFP:Generic Framing Procedure), High-Level Data Link Control packaged types such as (HDLC:High Level Data Link Control), with the encapsulation after signal map in the virtual container VC of SDH/SONET, adopt the byte interleaving mode to be multiplexed in the SDH/SONET frame structure then, give the circuit transmission; For transport layer is the situation of optical transfer network OTN frame structure, also needs the SDH/SONET signal is mapped among the optical channel Payload Unit OPU of OTN again, transmits in the line with the OTN form, and the prior art mapping structure is handled complicated, and network layer is many.
Summary of the invention
The object of the present invention is to provide a kind of multi-channel data signal processing method easy and simple to handle and device, to solve in the prior art multichannel data signal gathering mapping structure complexity in the high-speed line, the problem that network layer is many.
Multi-channel data signal processing method of the present invention adopts following steps:
A, transmitting terminal receive the multichannel data signal;
B, described multichannel data signal is produced Frame after the encapsulation process respectively, comprise corresponding gap marker in the described Frame;
C, described Frame are through the fixing frame signal of rate adapted output bandwidth;
D, described frame signal is carried out the bus punch-through process, be multiplexed into a serial bit stream signal then, deliver to the circuit transmission;
E, described signal transfer to receiving terminal by circuit, and described receiving terminal carries out corresponding demultiplexing to be handled, and produces parallel bus signals;
F, to bus signals grouping, according to the gap marker of frame signal in frame head Search Results and the bus signals, each circuit-switched data Signal Separation is come out, be sent to the FPDP of gap marker correspondence.
In the described steps A, transmitting terminal is carried out opto-electronic conversion, input, clock and data recovery processing to the multichannel data signal, determines the client signal state that receives;
Among the described step B, the frame structure of described encapsulation of data frame comprises frame head, frame length information, frame category sign, gap marker, payload area and check information;
Described frame head can adopt the information of set form, or adopts the mode of in GFP or the ATM encapsulation frame head payload of regular length being carried out cyclic redundancy check (CRC);
Described payload area can or be a certain size data block for a complete medium access control mac frame signal, and its classification is divided into Frame, maintenance frame and rate adapting frame;
Among the described step C, frame signal is carried out scrambler handle, the frame signal after the rate adapted changes into parallel form output;
Among the described step D, described frame signal carried out the bus punch-through process after, signal is interleave synchronously multiplexing, produce the serial bit stream that is suitable for the circuit transmission;
Among the described step D, can be used as synchronization bit stream for the signal after multiplexing and map directly in the payload structure of SDH/SONET, OTN, produce the SDH/SONET frame signal, or after directly carrying out forward error correction FEC processing, deliver to the circuit transmission;
The mask data signal adopts following method in the described step F:
F1, according to the parallel bus quantity of each circuit-switched data signal in multiplexing, bus signals is carried out sequential packet;
F2, information that each group parallel bus signal reorganization is formed are carried out the frame head search, and as feedback quantity, the grouping again of control bus signal all searches correct header signal until each road signal with the result of frame head search;
F3, according to the signal frame structure feature, peel off the signal that is used for rate adapted;
F4, signal is carried out decapsulation handle, check the gap marker of each road signal, the gap marker that extracts and this gap marker of setting are compared, if both are inconsistent, again the grouping of control bus signal, carry out corresponding cross processing, till the gap marker signal that extracts is the gap marker that receive from each road signal.
Among the described step B, when data-signal breaks down, with the information in the fixed mode information substitution data-signal;
Described line transmission bandwidth is the bandwidth sums of a plurality of passages through rate adapted output.
This multichannel data signal processing apparatus, be connected in metropolitan area network or the wide area network system transmission line, it comprises the client clock module, a plurality of data-signal processing modules corresponding and encapsulation process module with respective channel, and interleave the multiplexing process module, it is characterized in that: also comprise a plurality of and respective channel rate corresponding adaptation module and frame head search module, and bus processing module and corresponding system clock module, wherein: described rate adapted module receives the signal from encapsulation process module or frame head search module, finishes the rate adapted of respective channel signal; Described frame head search module is used for the frame head search of respective channel signal, and feeds back relevant Search Results to the bus processing module; Described bus processing module is a central processing module, finishes the bus punch-through process that sends signal, receives the feedback information of frame head search module and encapsulation process module, control bus signal packets, and the transmission of relevant signal; Described system clock module is to rate adapted module, bus processing module and interleave multiplexing process module etc. system clock reference is provided; Described encapsulation process module is also checked the gap marker in the frame signal, the gap marker that extracts in the frame signal and this gap marker of setting is compared, and comparative result is sent to the bus processing module;
Described bus processing module comprises bus break-through submodule, bus selection submodule and total line traffic control submodule, and wherein: described bus break-through submodule is finished bus break-through and the information of frame signal when multiplexing and transmitted; Described total line traffic control submodule directly receives the feedback information of frame head search module and encapsulation process module, sends corresponding grouping instruction to the bus selection submodule; Described bus selection submodule is finished the grouping of bus signals, and information transmits, according to the grouping instruction of total line traffic control submodule to bus signals divide into groups again, cross processing.
Beneficial effect of the present invention is, in the present invention, in the process of encapsulation, directly carry out different gap markers, signal after the encapsulation is carried out rate adapted, insert rate adapting frame, make the signal bandwidth of each path fix, and then use and to interleave multiplexing mode synchronously and realize that a plurality of data-signals converge in the line signal and transmit, needn't adopt and of the prior art the data business be encapsulated, be mapped in the virtual container of SDH/SONET, carry out framing then, the processing of line management expense, simplified the convergence processing process, reduce the network mapping level, easy and simple to handle, the present invention is based on ripe circuit transmission technology, can be unrestricted for the data-signal number that is converged, the transparent transmission that is particularly suitable for a plurality of data-signals is used, adopt the present invention, can realize that the multichannel data signal directly converges in the single circuit transmits, and improves line transmission bandwidth, reduces the complexity of handling, processing mode is flexible, realizes simple.
Description of drawings
Fig. 1 is a general structure schematic diagram of the present invention;
Fig. 2 is a bus processing module internal structure schematic diagram;
Fig. 3 is the overall control flow schematic diagram of the present invention;
Fig. 4 is the signal controlling structural representation of the present invention to the multiplexing direction of ethernet signal;
Fig. 5 is the signal controlling structural representation of the present invention to ethernet signal demultiplexing direction;
Fig. 6 is the encapsulated frame structural representation;
Fig. 7 is the frame head zone form schematic diagram of set form;
Fig. 8 is the frame head zone form schematic diagram with frame head payload defencive function;
Fig. 9 is a frame length information form schematic diagram;
Figure 10 is the form schematic diagram of frame category identified areas;
Figure 11 interleaves multiplexing information flow view for adopting bit;
Figure 12 is a data-signal separating controlling schematic flow sheet;
Figure 13 is the information state schematic diagram by the operation of frame head identification control bus selection.
Embodiment
With embodiment the present invention is described in further detail with reference to the accompanying drawings below:
According to Fig. 1 and Fig. 2, the present invention is connected in metropolitan area network or the wide area network system transmission line, it comprises a plurality of data-signal processing modules corresponding with respective channel, in the present embodiment, it is that example describes that data-signal adopts ethernet signal, as shown in Figure 1, a plurality of data-signal processing modules, that is, ethernet signal # 1 processing module 1, ethernet signal # 2 processing module 1 ..., ethernet signal #n processing module 1 passage respectively corresponding ethernet signal # 1 port, ethernet signal # 2 port ..., ethernet signal #n port; As shown in Figure 1, the present invention also comprises encapsulation process module 2, rate adapted module 3 and frame head search module 4, bus processing module 5, interleaves multiplexing process module 6, system clock module 7 and client clock module 8.
As shown in Figure 1, a plurality of data-signal processing modules receive the multichannel ethernet signal respectively, before ethernet signal is multiplexing, do relevant opto-electronic conversion, input, clock and data recovery processing, behind the ethernet signal demultiplexing, ethernet signal is done corresponding electric light conversion and the synthetic processing of clock; A plurality of encapsulation process modules 2 encapsulate each road ethernet signal respectively and corresponding decapsulation, encapsulation process module 2 is also checked the gap marker in the frame signal, the gap marker that extracts in the frame signal and this gap marker of setting are compared, and comparative result is sent to bus processing module 5.
As shown in Figure 1, described rate adapted module 3 receptions are finished the rate adapted of respective channel signal from the signal of encapsulation process module 2 or frame head search module 4.
As shown in Figure 1, frame head search module 4 is used for the frame head search of respective channel signal, and to the relevant Search Results of bus processing module 5 feedbacks.
As shown in Figure 1, interleave the multiplexing and corresponding demultiplexing that multiplexing process module 6 is finished signal, transmit signal to circuit or bus processing module 5.
As shown in Figure 1, system clock module 7 is to rate adapted module 3, bus processing module 5 with interleave multiplexing process module 6 etc. system clock reference is provided.
As shown in Figure 1, bus processing module 5 is a central processing module, finish the bus punch-through process that sends signal, receive the feedback information of frame head search module 4 and encapsulation process module 2, the control bus signal packets, and relevant signal transmission, as shown in Figure 2, bus processing module 5 comprises bus break-through submodule 51, bus selection submodule 52 and total line traffic control submodule 53.
As shown in Figure 2, bus break-through submodule 51 is finished bus break-through and the information of frame signal when multiplexing and is transmitted.
As shown in Figure 2, total line traffic control submodule 53 directly receives the feedback information of frame head search module 4 and encapsulation process module 2, send corresponding grouping instruction to bus selection submodule 52, bus selection submodule 52 is finished the grouping of bus signals, information transmits, according to the grouping instruction of total line traffic control submodule 53 to bus signals divide into groups again, cross processing.
Concrete control flow of the present invention is as follows:
1, as shown in Figure 3 and Figure 4, ethernet signal # 1 processing module 1 in the transmitting terminal, ethernet signal # 2 processing module 1 ..., ethernet signal #n processing module 1 receive respectively ethernet signal # 1, ethernet signal # 2 ..., ethernet signal #n, and corresponding ethernet signal made relevant treatment, processing such as opto-electronic conversion, input, clock and data recovery processing, and the signal condition of definite input.
2, as shown in Figure 3 and Figure 4, signal is sent to encapsulation process module 2, and 2 pairs of multichannel ethernet signals of each encapsulation process module encapsulate, add gap marker respectively and handle back generation Frame.The encapsulation of 2 pairs of ethernet signals of encapsulation process module can be adopted the GFP mode, also can adopt following manner.
The encapsulating structure that encapsulation process module 2 is adopted as shown in Figure 6, the encapsulating structure of ethernet signal comprises frame head, frame length information, frame category sign, gap marker, payload area and several parts of check information.Encapsulating structure can be for the frame of regular length, also can be the frame signal of variable-length, for the convenience of describing, adopts the encapsulating structure of regular length here.
As shown in Figure 6, the original position of frame head reflection frame signal, the length of frame length information reflection payload area, the classification of frame category sign reflection payload area, the respective channel sequence number of gap marker reflection transmitting data information, the state of payload area carry data information, Adapted information or indication client signal, check information is used to guarantee the integrality of signals transmission, can adopt cyclic redundancy check (CRC) mode or bit interleaved parity mode.Respectively each zone is described in detail below:
A, frame head: frame head is used to discern the starting position of frame signal, frame head can adopt the information of set form, for example shown in Figure 7, adopt the repetitive sequence pattern of the F628 in SDH/SONET, the OTN frame format, the mode that also can adopt the frame head payload to regular length that defines in the encapsulation of GFP or asynchronous transfer mode ATM to carry out cyclic redundancy check (CRC) forms the mode of frame head.When adopting this mode; as shown in Figure 8; payload length information or other important informations can be placed as the frame head payload; then payload is carried out cyclic redundancy check (CRC); the check information that produces is added on the payload back, forms a complete frame head zone, and this processing can protect frame head not to be vulnerable to the interference of circuit transmission; in the frame receiving course under this processing mode, need calculate the frame head information that obtains by cyclic redundancy check (CRC).
B, frame length information: be used to represent the byte length of the payload area of encapsulating structure, be convenient to the start-stop position that receiving terminal is correctly discerned frame signal apace, can adopt the area identification frame length information of a regular length.For example among Fig. 9, if with the region representation frame length information of 2-byte, the then maximum payload area that can support 65536 byte lengths.For normal ethernet signal, the Ethernet information of regular length can be represented in this zone, and corresponding frame signal is called the Ethernet maintenance information of Frame or regular length, and corresponding frame signal is called maintenance frame.For maintenance frame, the payload area that can stipulate it is the fixed sequence program (for example complete 1 sequence, pseudo random sequence, the condition that the Ethernet service of the content maintenance information representation input in the payload area breaks down) of regular length.The regular length that also can represent rate adapting frame.Frame length information also can be represented the payload area byte length of the Frame of variable-length.
C, frame category sign: be used for the classification of the payload area of identification frames signal structure, can adopt the zone of a regular length to identify as frame category, for example shown in Figure 10, the classification of the region representation payload area of usefulness 2-byte.
Frame category can be divided as follows:
Frame, that is, and normal Ethernet service signal;
Maintenance frame, the client signal of this passage that indication receives breaks down, and the payload area part of maintenance frame produces fixed mode signal flow according to the client clock territory of data-signal processing module;
Rate adapting frame is rate adapted information.
In the present invention, use this frame category identified areas to represent payload area loaded information classification: Frame, maintenance frame and rate adapting frame, as shown in table 1 according to Figure 10, shown form and encoded radio that frame category coding and Frame are encoded.
| Position in the encapsulating structure | The value of frame category identified areas (binary system/hexadecimal) | Information type in the payload area | Remarks |
| | 0000 0000/0x00 | Rate adapting frame | |
| 0001 0000/0x10 | Frame | ||
| 0001 0001/0x11 | Maintenance frame | ||
| Other | Keep or the other | ||
| Byte | |||
| 8 | 0000 0000/0x00 | Gigabit Ethernet GE Frame/GE maintenance frame | Need determine in conjunction with the definition in the |
| 0000 0001/0x01 | Fast Ethernet FE Frame/FE maintenance frame | ||
| 0000 0010/0x02 | Ether Ethernet Frame/Ethernet maintenance frame | ||
| 0000 0011/0x03 | Multiprotocol label switching MPLS Frame/MPLS maintenance frame | ||
| 0000 0100/0x04 | Optical-fibre channel FC 1G Frame/FC 1G maintenance frame | ||
| 0000 0101/0x05 | Optical-fibre channel FC 2G Frame/FC 2G maintenance frame | ||
| 0000 0110/0x06 | Optical fiber connects FICON 1G Frame/FICON 1G maintenance frame | ||
| 0000 0111/0x07 | Optical fiber connects FICON 2G Frame/FICON 2G maintenance frame | ||
| 0000 1000/0x08 | Business system connects ESCON Frame/ESCON maintenance frame | ||
| 0000 1001/0x09 | Digital video broadcasting DVB Frame/DVB maintenance frame | ||
| 0,000 1010～1,111 1111/0x0A～0xff | Keep or the other types definition |
Table 1
D, gap marker: determined that in the frame category sign frame signal is under the situation of Frame or maintenance frame, the gap marker territory identifies the signal from different passages, the channel number of the signal that carries in the regulation payload area, it can be defined as the 2-byte section, the gap marker zone combines with payload area, and receiving terminal just can correctly be finished signal and recover.
E, payload area: Frame can be carried in this zone, can be a complete frame signal, promptly carries the mac frame of Ethernet information, and it comprises a complete mac frame signal, includes lead code, frame begins information such as delimiter and frame end delimiter; Also can be the data block signal, the data block of a certain size that promptly a plurality of 10-bit characters form after decoding through 8B/10B.
Payload area also can carry maintenance frame, it is the maintenance information of regular length, when the Ethernet service of this passage breaks down, for example the data-signal processing module monitors dropout, correctly under the fault condition such as recovered clock data-signal, utilize the client clock territory to produce the bit sequence of set form, be placed in the payload area, substitute the information in the ethernet signal, and in frame length information and frame category indication, provide corresponding indication, pass to receiving terminal, receiving terminal is according to frame length information, information such as frame category indication are discerned this fault message, and this fault message are sent to the data equipment of far-end.
F, check information: this zone is protected the information in the encapsulating structure, can begin to carry out verification to the section of payload area end position from frame head at whole encapsulating structure, also can select some zone to carry out checking treatment.The method of calibration that adopts can be the cyclic redundancy check (CRC) mode, also can be the bit interleaved parity mode, and concrete processing can be with reference to relevant criterion.
3, as shown in Figure 3 and Figure 4, because the transmission of Ethernet service signal has sudden, signal in transmission line should be continuous data stream, therefore, payload area is except the carrying Frame or maintenance frame relevant with each passage, also need to insert the rate adapting frame that is used for rate adapted, Frame after the processing of rate adapted module 3, the frame signal that output bandwidth is fixing.
According to the existing chip technology, internal clocking is operated in lower frequency, therefore to each road Ethernet service signal through adopting the form output of parallel bus after above-mentioned processing, the bit rate of the signal on every bus is also fixed.The ethernet signal of each passage is carried out after the rate adapted, and each road signal of generation all has fixing bandwidth, for example, after one road GE signal processing, the signal bandwidth that produces is 1.24416Gbps, and the signal bandwidth of transmitting on each bar parallel bus is fixed, and for example can be 77M or 38M.Line transmission bandwidth is the bandwidth sums of a plurality of passages through rate adapted output.In rate adapted, frame signal changes into before the parallel form, other parts except that frame head can be carried out scrambler and handle, and prevents the signal format that other parts are duplicated frame head in the frame structure.Each road Ethernet service is sent to bus break-through submodule 51 through the information after handling by parallel bus.
4, as shown in Figure 3 and Figure 4, the frame signal of 51 pairs of parallel buss of bus break-through submodule is carried out the bus punch-through process, interleaving the signal of multiplexing process module 6 after to each channel bus punch-through process interleaves multiplexing synchronously, multiplex mode can adopt bit to interleave multiplexing, byte intertexture division multiplexing or other interleave multiplex mode synchronously, Figure 11 shows that the employing bit interleaves multiplexing information flow view, and the principle that other multiplex modes are handled is similar.Through interleaving after the multiplexing process, produce the serial bit stream that is suitable for the circuit transmission, deliver to the circuit transmission.
Signal after multiplexing can be used as synchronization bit stream and maps directly in the payload structure of SDH/SONET, OTN, produces the SDH/SONET frame signal, or after directly carrying out the FEC processing, delivers to the circuit transmission.Utilize the SDH/SONET frame signal can add more line management information, adopting FEC to handle can be in order to improve the transmission performance of circuit.
5, as Fig. 3 and shown in Figure 5, signal transfers to receiving terminal by circuit, in the receiving terminal, interleaves 6 pairs of signals of multiplexing process module and carries out corresponding demultiplexing processing, produces parallel bus signals.
6, as Fig. 3 and shown in Figure 5, the grouping of the 52 pairs of bus signals of bus selection submodule, according to the gap marker of frame signal in frame head Search Results and the bus signals, with each road ethernet signal fully, separate exactly, its concrete operations flow process is as follows:
61, as Figure 12 and shown in Figure 5, bus selection submodule 52 is according to the parallel bus quantity of each road ethernet signal in multiplexing, bus signals is carried out sequential packet, for example, be applicable to the situation of 2 Ethernet services for the 2.5G line bandwidth, in multiplexing, each road ethernet signal is through encapsulation, bandwidth after rate adapted is handled is 1.24416Gbps, rate adapted is divided into 8 * 155Mbps bus transfer with the 1.24416Gbps bandwidth after handling, then as shown in Figure 5,52 inputs of bus selection submodule have 16 road 155Mbps buses, are divided into two groups of 8 * 155Mbps buses in order.
62, as Figure 12 and shown in Figure 5, frame head search module 4 carries out the frame head search to the information that each group parallel bus signal reorganization forms.
63, as Figure 12 and shown in Figure 5, if search is less than correct header signal, the result of frame head search module 4 usefulness frame heads search is sent to total line traffic control submodule 53 as feedback quantity, total line traffic control submodule 53 sends command adapted thereto to bus selection submodule 52,52 pairs of bus signals of bus selection submodule carry out the bit displacement, again grouping again, circular treatment like this, each road signal in each group parallel bus signal all searches correct header signal, as shown in figure 13, the information state that has reflected the operation of frame head identification control bus selection comparatively intuitively.
64, as Figure 12 and shown in Figure 5, the frame signal that frame head search module 4 will search the bus reorganization formation of correct header signal is sent to rate adapted module 3, rate adapted module 3 is according to the signal frame structure feature, peel off the signal that is used for rate adapted, shown in the dotted line among Fig. 5, the signal after rate adapted module 3 is adaptive works in the client clock territory.
65, as Figure 12 and shown in Figure 5, encapsulation process module 2 is carried out the decapsulation processing to each road signal, extracts corresponding gap marker signal.
66, as Figure 12 and shown in Figure 5, encapsulation process module 2 compares the gap marker that extracts and this gap marker of setting, if both are inconsistent, encapsulation process module 2 is sent error message to total line traffic control submodule 53, total line traffic control submodule 53 sends command adapted thereto to bus selection submodule 52, bus signals after 52 pairs of groupings of bus selection submodule carries out cross processing, and then judgement gap marker information, if the gap marker that extraction extracts from frame structure and this gap marker of setting are inconsistent, to repeat cross processing and judge gap marker information, till the gap marker signal that extracts from each road signal is the gap marker that receive.
67, as Figure 12 and shown in Figure 5, each correct group signal of gap marker transfers to corresponding data-signal processing module through separating to be honored as a queen.
7, as Fig. 3 and shown in Figure 5, the data-signal processing module is carried out respective handling to signal, and processing such as, electric light conversion synthetic as clock are sent to corresponding ethernet port, promptly corresponding FPDP with handling each road ethernet signal that the back produces.
In the present embodiment, done detailed elaboration for the processing of ethernet signal, in the present invention, for other data-signal, as, multiprotocol label switching MPLS Frame, optical-fibre channel FC Frame, optical fiber connect that FICON Frame, business system connect the processing of ESCON Frame or digital video broadcasting DVB data frame signal and the above is same or similar, repeat no more herein.
Claims (13)
1. multi-channel data signal processing method, it is characterized in that: it adopts following steps:
A, transmitting terminal receive the multichannel data signal;
B, described multichannel data signal is produced Frame after the encapsulation process respectively, comprise corresponding gap marker in the described Frame;
C, described Frame are through the fixing frame signal of rate adapted output bandwidth;
D, described frame signal is carried out the bus punch-through process, be multiplexed into a serial bit stream signal then, deliver to the circuit transmission;
E, described signal transfer to receiving terminal by circuit, and described receiving terminal carries out corresponding demultiplexing to be handled, and produces parallel bus signals;
F, to bus signals grouping, according to the gap marker of frame signal in frame head Search Results and the bus signals, each circuit-switched data Signal Separation is come out, be sent to the FPDP of gap marker correspondence.
2. multi-channel data signal processing method according to claim 1 is characterized in that: in the described steps A, transmitting terminal is carried out opto-electronic conversion, input, clock and data recovery processing to the multichannel data signal, determines the client signal state that receives.
3. multi-channel data signal processing method according to claim 1 is characterized in that: among the described step B, the frame structure of described encapsulation of data frame comprises frame head, frame length information, frame category sign, gap marker, payload area and check information.
4. multi-channel data signal processing method according to claim 3, it is characterized in that: described frame head can adopt the information of set form, or adopts general frame forming to handle the mode of in GFP or the ATM encapsulation frame head payload of regular length being carried out cyclic redundancy check (CRC).
5. multi-channel data signal processing method according to claim 3, it is characterized in that: described payload area can or be a certain size data block for a complete medium access control mac frame signal, and its classification is divided into Frame, maintenance frame and rate adapting frame.
6. multi-channel data signal processing method according to claim 1 is characterized in that: among the described step C, frame signal is carried out scrambler handle, the frame signal after the rate adapted changes into parallel form output.
7. multi-channel data signal processing method according to claim 1 is characterized in that: among the described step D, described frame signal carried out the bus punch-through process after, signal is interleave synchronously multiplexing, produce the serial bit stream that is suitable for the circuit transmission.
8. according to claim 1 or 7 described multi-channel data signal processing methods, it is characterized in that: among the described step D, can be used as synchronization bit stream for the signal after multiplexing maps directly in the payload structure of SDH/SONET, OTN, produce the SDH/SONET frame signal, or after directly carrying out forward error correction FEC processing, deliver to the circuit transmission.
9. multi-channel data signal processing method according to claim 1 is characterized in that: the mask data signal adopts following method in the described step F:
F1, according to the parallel bus quantity of each circuit-switched data signal in multiplexing, bus signals is carried out sequential packet;
F2, information that each group parallel bus signal reorganization is formed are carried out the frame head search, and as feedback quantity, the grouping again of control bus signal all searches correct header signal until each road signal with the result of frame head search;
F3, according to the signal frame structure feature, peel off the signal that is used for rate adapted;
F4, signal is carried out decapsulation handle, check the gap marker of each road signal, the gap marker that extracts and this gap marker of setting are compared, if both are inconsistent, again the grouping of control bus signal, carry out corresponding cross processing, till the gap marker signal that extracts is the gap marker that receive from each road signal.
10. multi-channel data signal processing method according to claim 1 is characterized in that: among the described step B, when data-signal breaks down, with the information in the fixed mode information substitution data-signal.
11. multi-channel data signal processing method according to claim 1 is characterized in that: described line transmission bandwidth is the bandwidth sums of a plurality of passages through rate adapted output.
12. multichannel data signal processing apparatus, be connected in metropolitan area network or the wide area network system transmission line, it comprises client clock module, a plurality of data-signal processing module corresponding with respective channel and encapsulation process module, and interleave the multiplexing process module, it is characterized in that: also comprise a plurality of and respective channel rate corresponding adaptation module and frame head search module, and bus processing module and corresponding system clock module, wherein:
Described rate adapted module receives the signal from encapsulation process module or frame head search module, finishes the rate adapted of respective channel signal;
Described frame head search module is used for the frame head search of respective channel signal, and feeds back relevant Search Results to the bus processing module;
Described bus processing module is a central processing module, finishes the bus punch-through process that sends signal; Receive the feedback information of frame head search module and encapsulation process module, control bus signal packets, and the transmission of relevant signal;
Described system clock module is to rate adapted module, bus processing module and interleave multiplexing process module etc. system clock reference is provided;
Described encapsulation process module is also checked the gap marker in the frame signal, the gap marker that extracts in the frame signal and this gap marker of setting is compared, and comparative result is sent to the bus processing module.
13. multichannel data signal processing apparatus according to claim 12 is characterized in that: described bus processing module comprises bus break-through submodule, bus selection submodule and total line traffic control submodule, wherein:
Described bus break-through submodule is finished bus break-through and the information of frame signal when multiplexing and is transmitted;
Described total line traffic control submodule directly receives the feedback information of frame head search module and encapsulation process module, sends corresponding grouping instruction to the bus selection submodule;
Described bus selection submodule is finished the grouping of bus signals, and information transmits, according to the grouping instruction of total line traffic control submodule to bus signals divide into groups again, cross processing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100330267A CN100512091C (en) | 2005-01-25 | 2005-01-25 | Multi-channel data signal processing method and apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100330267A CN100512091C (en) | 2005-01-25 | 2005-01-25 | Multi-channel data signal processing method and apparatus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1812315A true CN1812315A (en) | 2006-08-02 |
| CN100512091C CN100512091C (en) | 2009-07-08 |
Family
ID=36845024
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100330267A Expired - Fee Related CN100512091C (en) | 2005-01-25 | 2005-01-25 | Multi-channel data signal processing method and apparatus |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100512091C (en) |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008055441A1 (en) * | 2006-11-06 | 2008-05-15 | Huawei Technologies Co., Ltd. | Transmission method and apparatus for fiber channel services and system thereof |
| WO2009086778A1 (en) * | 2007-12-29 | 2009-07-16 | Huawei Technologies Co., Ltd. | Rate adapting method and apparatus, exchange board and line card |
| CN101543072B (en) * | 2007-02-19 | 2011-06-01 | 株式会社东芝 | Data multiplexing/separating device |
| CN102439995A (en) * | 2011-08-24 | 2012-05-02 | 华为技术有限公司 | Method and device for transmitting ultra high-speed Ethernet service |
| CN101500183B (en) * | 2009-03-06 | 2012-12-05 | 中兴通讯股份有限公司 | Method for synchronizing frame head by transmission equipment and apparatus thereof |
| CN102867525A (en) * | 2012-09-07 | 2013-01-09 | Tcl集团股份有限公司 | Multi-channel audio processing method, audio playback terminal and audio receiving device |
| CN103580786A (en) * | 2012-07-27 | 2014-02-12 | 中兴通讯股份有限公司 | Method and system for reducing time division multiplexing service delay jitter |
| CN104168199A (en) * | 2013-05-15 | 2014-11-26 | 中兴通讯股份有限公司 | Packet processing method and apparatus |
| WO2016037474A1 (en) * | 2014-09-12 | 2016-03-17 | 中兴通讯股份有限公司 | Framing method and device |
| CN106933768A (en) * | 2015-12-29 | 2017-07-07 | 北京中和卓远科技有限公司 | Airborne Ethernet high-speed parallel tape deck |
| CN107517170A (en) * | 2017-07-31 | 2017-12-26 | 广东中云海科技有限公司 | Redundant system and splicing system for polymorphic type, multi tate baseband signal |
| CN107579797A (en) * | 2017-11-09 | 2018-01-12 | 深圳震有科技股份有限公司 | A kind of multi tate SDH optical interfaces multiplex circuit, fpga chip and equipment |
| WO2018098896A1 (en) * | 2016-11-29 | 2018-06-07 | 深圳市元征科技股份有限公司 | Method for configuring structure of data subframe and related device |
| CN113473268A (en) * | 2020-03-31 | 2021-10-01 | 华为技术有限公司 | Channel identification method and device based on multiplexing |
| CN114024796A (en) * | 2021-11-30 | 2022-02-08 | 新华三半导体技术有限公司 | Data sending method, communication device and electronic equipment |
| CN114765528A (en) * | 2021-01-15 | 2022-07-19 | 烽火通信科技股份有限公司 | Frame synchronization method, device, equipment and readable storage medium |
-
2005
- 2005-01-25 CN CNB2005100330267A patent/CN100512091C/en not_active Expired - Fee Related
Cited By (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008055441A1 (en) * | 2006-11-06 | 2008-05-15 | Huawei Technologies Co., Ltd. | Transmission method and apparatus for fiber channel services and system thereof |
| CN101543072B (en) * | 2007-02-19 | 2011-06-01 | 株式会社东芝 | Data multiplexing/separating device |
| WO2009086778A1 (en) * | 2007-12-29 | 2009-07-16 | Huawei Technologies Co., Ltd. | Rate adapting method and apparatus, exchange board and line card |
| CN101471793B (en) * | 2007-12-29 | 2011-05-18 | 华为技术有限公司 | Method and equipment for adapting velocity, exchange plate and cable fastener |
| CN101500183B (en) * | 2009-03-06 | 2012-12-05 | 中兴通讯股份有限公司 | Method for synchronizing frame head by transmission equipment and apparatus thereof |
| US9497064B2 (en) | 2011-08-24 | 2016-11-15 | Huawei Technologies Co., Ltd. | Method and apparatus for transporting ultra-high-speed Ethernet service |
| CN102439995A (en) * | 2011-08-24 | 2012-05-02 | 华为技术有限公司 | Method and device for transmitting ultra high-speed Ethernet service |
| WO2012119415A1 (en) * | 2011-08-24 | 2012-09-13 | 华为技术有限公司 | Method and device for transporting ultra-high-speed ethernet service |
| CN102439995B (en) * | 2011-08-24 | 2014-09-03 | 华为技术有限公司 | Method and device for transmitting ultra high-speed Ethernet service |
| CN103580786A (en) * | 2012-07-27 | 2014-02-12 | 中兴通讯股份有限公司 | Method and system for reducing time division multiplexing service delay jitter |
| CN102867525A (en) * | 2012-09-07 | 2013-01-09 | Tcl集团股份有限公司 | Multi-channel audio processing method, audio playback terminal and audio receiving device |
| CN102867525B (en) * | 2012-09-07 | 2016-01-13 | Tcl集团股份有限公司 | A kind of multichannel voice frequency disposal route, audio-frequency playing terminal and apparatus for receiving audio |
| CN104168199A (en) * | 2013-05-15 | 2014-11-26 | 中兴通讯股份有限公司 | Packet processing method and apparatus |
| WO2016037474A1 (en) * | 2014-09-12 | 2016-03-17 | 中兴通讯股份有限公司 | Framing method and device |
| CN106933768A (en) * | 2015-12-29 | 2017-07-07 | 北京中和卓远科技有限公司 | Airborne Ethernet high-speed parallel tape deck |
| WO2018098896A1 (en) * | 2016-11-29 | 2018-06-07 | 深圳市元征科技股份有限公司 | Method for configuring structure of data subframe and related device |
| CN107517170A (en) * | 2017-07-31 | 2017-12-26 | 广东中云海科技有限公司 | Redundant system and splicing system for polymorphic type, multi tate baseband signal |
| CN107579797A (en) * | 2017-11-09 | 2018-01-12 | 深圳震有科技股份有限公司 | A kind of multi tate SDH optical interfaces multiplex circuit, fpga chip and equipment |
| CN113473268A (en) * | 2020-03-31 | 2021-10-01 | 华为技术有限公司 | Channel identification method and device based on multiplexing |
| CN114765528A (en) * | 2021-01-15 | 2022-07-19 | 烽火通信科技股份有限公司 | Frame synchronization method, device, equipment and readable storage medium |
| CN114765528B (en) * | 2021-01-15 | 2023-09-26 | 烽火通信科技股份有限公司 | Frame synchronization method, device, equipment and readable storage medium |
| CN114024796A (en) * | 2021-11-30 | 2022-02-08 | 新华三半导体技术有限公司 | Data sending method, communication device and electronic equipment |
| CN114024796B (en) * | 2021-11-30 | 2023-02-21 | 新华三半导体技术有限公司 | Data sending method, communication device and electronic equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100512091C (en) | 2009-07-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1812315A (en) | Multi-channel data signal processing method and apparatus | |
| US7809021B2 (en) | Communication system and encoding method having low overhead | |
| CN1748381A (en) | Efficient framing procedure for variable length packets | |
| CN110768742B (en) | OAM message transmission method, sending device, receiving device and readable storage medium | |
| CN1193549C (en) | System having meshed backplane and process for transferring data therethrough | |
| CN104580031B (en) | POS based on multi-protocols link encapsulation technology separates frame framing device and method | |
| JP6867473B2 (en) | Methods and equipment for sending services, methods and equipment for receiving services, and network systems. | |
| US9178713B1 (en) | Optical line termination in a passive optical network | |
| CN1791057A (en) | Method for transmitting data service in OTN and its device | |
| CN1449132A (en) | Multiplex system using common network group to transmit multiple 8B/10B bit stream | |
| US7164860B1 (en) | Advanced multi-protocol optical transport network | |
| US10044471B2 (en) | Delivering CPRI and ethernet signals over optical networks | |
| US7245633B1 (en) | Multiplexing method for gigabit ethernet signals in the synchronous digital hierarchy | |
| CN1512684A (en) | Method and device for elastic protection conversion in Ethernet passive optic network system | |
| CN1267164A (en) | Method and apparatus for transmission of low speed synchronous digital series signals | |
| CN1812316A (en) | Link collecting processing method and apparatus | |
| CN100568841C (en) | A kind of converging device of Ethernet service and method | |
| CN105790883A (en) | Signal processing method and communication device | |
| CN101035143A (en) | Physical layer chip, method for transferring the signal and switcher | |
| CN1691666A (en) | Method of multi-protocol universal line transmission and device therefor | |
| CN101039156A (en) | Method and apparatus for transmitting SDH data | |
| EP1648133B1 (en) | A method for encapsulating data stream | |
| CN1392684A (en) | Wavelength division multiplexing optical network transmission adapting method for IP data | |
| CN1206839C (en) | Reverse multiplexer circuit layer protecting and restoring method and device | |
| CN101035112A (en) | Device and method for transferring the additional information |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090708 Termination date: 20170125 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |