CN100486224C - Method and device for controlling ATM network flow based on FPGA - Google Patents
Method and device for controlling ATM network flow based on FPGA Download PDFInfo
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Abstract
This invention discloses the realizing ATM network flow control device and method based on FPGA.
Description
Technical field
The present invention relates to realize the flow control technique field in the router, particularly relate to the devices and methods therefor of on router, realizing the atm network flow control based on FPGA.
Background technology
Development along with computing technique, various data transmission networks have appearred, two kinds of networks of main at present existence, a kind of is to be transmission IP (the Internet Protocol of unit with the bag, Internet protocol) packet network, a kind of is to be the transmission ATM (Asynchronous Transfer Mode, asynchronous transfer mode) of unit network with the cell.As the router that is grouped into the exchange basis with IP, when connecting atm network, need be used for process IP and be grouped into the interface card that ATM cell is changed mutually.
Present atm line interface card is mainly by (as shown in Figure 1) optical module 101, physical chip 102, SAR (Segment And Reassemble, segmentation/reorganization or dismounting) chips such as chip 103, FPGA (FieldProgrammable Gate Array, field programmable logic array) chip 104 and network processing unit 105 form.Wherein, optical module 101 is finished opto-electronic conversion, physical chip 102 is finished SDH (Synchronous Digital Hierarchy, synchronous digital hierarchy) functions such as frame extraction and cell encapsulation, SAR chip 103 is finished burst, ATM cell reorganization and QoS (the Quality of Service of IP message, service quality) function such as business, fpga chip 104 is used to connect SAR chip 103 and network processing unit 105, finishes the data transaction between the two.Because the data-interface between network processing unit and the most chip and inconsistent need carry out data transaction at present, fpga chip is essential in system.Along with the semiconductor technology development, the scale of fpga chip is increasing, and price is also more and more cheap simultaneously, uses cheap fpga chip to replace the SAR chip to become possibility.The flow control of present atm line interface card relies on the SAR chip to finish, and there are shortcomings such as design complexity, cost height in this system.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of devices and methods therefor of realizing the atm network flow control based on FPGA, the atm network flow control that is used for overcoming in the router that prior art exists is realized by special-purpose SAR chip, causes system complex, too high problem and the defective of cost.
To achieve these goals, the invention provides a kind of device, comprise network processing unit, physical chip, it is characterized in that, also comprise based on the flow control of FPGA realization atm network:
One ATM cell memory is used to receive the ATM cell that described network processing unit transmits, and stores described ATM cell by PVC passage piecemeal;
One pvc management module is used for described ATM cell memory is invented a plurality of fifo queues according to PVC, and described each fifo queue is managed;
One pvc state cache module is used to store next ATM cell delivery time variable of described each PVC passage;
One PVC band width configuration module is used to dispose the bandwidth parameter of described each PVC passage;
One flow control module, be used to produce the PVC channel number, inquire about described pvc management module, pvc state cache module and PVC band width configuration module, whether the passage that calculates this PVC channel number correspondence has ATM cell and whether allows to read ATM cell, and the assembling ATM cell becomes cell frame and storage;
One cell frame sending module is used for reading the cell frame from described flow-control module, carries out ATM cell and controls at interval, and send the cell frame that does not contain frame head;
One physical interface module is used to receive the cell frame that described cell frame sending module is sent, and it is sent to described physical chip.
Described device based on the flow control of FPGA realization atm network, wherein, described ATM cell memory comprises again: an External memory equipment and a memory interface module; Described External memory equipment is used to store ATM cell, and described memory interface module is carried out the interface module of exchanges data as external RAM and FPGA internal logic.
Described device based on the flow control of FPGA realization atm network, wherein, described flow-control module comprises again: an ATM cell sending module, a cell frame buffer, a bandwidth control module and a benchmark be generation module constantly; Wherein
Described ATM cell sending module is used to inquire about described each PVC passage, produce the operation of the described pvc management module of inquiry, pvc state cache module, PVC band width configuration module and bandwidth control module, read address ram to described ATM cell memory transmission, the parameter that the ATM cell of reading back and described bandwidth control module are returned is formed the cell frame according to certain form, and deposit in to described cell frame buffer;
Described cell frame buffer is used to store the fifo queue of cell frame;
Described bandwidth control module is used to safeguard the time interval number variable of the maximum bandwidth of an ATM cell delivery time variable, system configuration, inquire about next ATM cell delivery time variate-value that described pvc state cache module returns respectively with the benchmark count variable value of generation module and the situation that a last ATM cell delivery time variate-value compares constantly, whether decision allows described ATM cell sending module to read ATM cell at this next ATM cell delivery time from described ATM cell memory according to comparative result, and the PVC channel status is safeguarded;
Described benchmark generation module constantly is a counter, is used to produce the described counting variable as described bandwidth control module judgement benchmark, and produces the signal of the described pvc state cache module of initialization.
Described device based on the flow control of FPGA realization atm network, wherein, described physical interface module is a standard Utopia interface.
To achieve these goals, the present invention also provides a kind of method based on the flow control of FPGA realization atm network that is applicable to described device, it is characterized in that, comprising:
Step 51, the ATM cell memory receives the ATM cell that described network processing unit transmits, and stores described ATM cell by PVC passage piecemeal;
Step 52, flow-control module produces the PVC channel number, constantly inquire about described pvc management module, pvc state cache module and PVC band width configuration module, whether the passage that calculates this PVC channel number correspondence has ATM cell and whether allows to read ATM cell, and the assembling ATM cell becomes cell frame and storage;
Step 53, cell frame sending module reads the cell frame from described flow-control module, carry out ATM cell and control at interval, and send the cell frame that does not contain frame head;
Step 54, physical interface module receive the cell frame that described cell frame sending module is sent, and it is sent to described physical chip.
The described method that realizes the atm network flow control based on FPGA, wherein, comprise also between the described step 51,52 that a pvc state initialization command that sends by flow-control module carries out initialized step to described pvc state cache module, be used for next ATM cell pointer of described all PVC passages is all pointed to zero.
The described method that realizes the atm network flow control based on FPGA, wherein, comprise also in the described step 52 that the fifo queue state of passage by inquiring about this PVC channel number correspondence that described pvc management module returns judges whether the passage of this PVC channel number correspondence has the step of ATM cell.
The described method that realizes the atm network flow control based on FPGA, wherein, comprise also in the described step 52 that a value of returning by described bandwidth control module, cell frame buffer judges whether to allow described ATM cell sending module to read the step of ATM cell from described ATM cell memory.
The described method that realizes the atm network flow control based on FPGA, wherein, in the described step 52, if the passage of this PVC channel number correspondence allows to read ATM cell, then described ATM cell sending module reads ATM cell from described ATM cell memory, and adds a control word at interval at the head of this ATM cell, forms a cell frame and deposits to described cell frame buffer, cell flag of frame position is set, waits for that described cell frame sending module reads; Pvc state after will upgrading simultaneously writes back described pvc state cache module, continues next PVC passage of inquiry.
The described method that realizes the atm network flow control based on FPGA, wherein, comprised also that before described step 53 a described cell frame sending module is to judge the step that whether contains the cell frame in the described cell frame buffer by the cell flag of frame position of inquiring about described flow-control module.
The described method that realizes the atm network flow control based on FPGA wherein, comprised also that before described step 53 one judges whether to allow described cell frame sending module to read the step of cell frame from described cell frame buffer.
The described method that realizes the atm network flow control based on FPGA, wherein, in the described step 53, described cell frame sending module obtains the counter currency by starting an interval counter, and read the cell frame head by inquiry cell frame buffer and obtain an ATM cell spacing parameter, the mode by more described counter currency and described ATM cell spacing parameter realizes that ATM cell controls at interval again.
The described method that realizes the atm network flow control based on FPGA, wherein, if described ATM cell spacing parameter value allows to send ATM cell less than described counter currency and described physical interface module, then described cell frame sending module is sent to described physical interface module with ATM cell.
The invention provides a kind of method and apparatus of simply realizing the atm network flow control based on FPGA, the atm network flow control that solves in the router that exists in the prior art is realized by special-purpose SAR chip, causes system complex, too high problem and the defective of cost; Compared with prior art, beneficial effect of the present invention is:
Adopt the method for the invention and device to obtain and use FPGA to replace the technological progress that special-purpose SAR chip is realized flow control, reached the effect of accurate control ATM cell speed, saved system cost, improved system reliability and market competitiveness or the like.
Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
Description of drawings
Fig. 1 is atm line interface board system module figure in the prior art;
Fig. 2 is atm network flow-control module figure of the present invention;
The PVC band width configuration parameter schematic diagram of Fig. 3 for using among the present invention;
The cell frame encapsulation schematic diagram of Fig. 4 for using among the present invention;
Fig. 5 is a PVC bandwidth chahnel control and treatment flow chart of the present invention;
Fig. 6 is an ATM cell process chart of the present invention.
Embodiment
Below in conjunction with accompanying drawing the enforcement that realizes atm network flow control technique scheme based on FPGA is described in further detail.
See also shown in Figure 2ly, be atm network flow-control module figure of the present invention; The PVC band width configuration parameter schematic diagram of Fig. 3 for using among the present invention; The cell frame encapsulation schematic diagram of Fig. 4 for using among the present invention.The present invention is based on FPGA and realize that the device of atm network flow control comprises: hardware module part, software module part.
Hardware module partly comprises: ATM cell memory 201 comprises External memory equipment 202 and memory interface module 203.Wherein, External memory equipment 202 is big capacity RAM (RandomAccess Memory, random asccess memory), is used for storing ATM cell; Memory interface module 203 is interface modules that external RAM and FPGA internal logic carry out exchanges data; ATM cell memory 201 is subjected to pvc management module 204 and flow-control module 211 control read-write operations.
Software module partly comprises as lower module:
Pvc management module 204, for providing, ATM cell memory 201 writes address ram, and ATM cell memory 201 pressed PVC (Permanent Virtual Circuits, the permanent virtual link) invents a plurality of FIFO (First-In First-Out, first in first out) formation, and each fifo queue state managed, to treat flow-control module 211 inquiries.
Pvc state cache module 205 is FPGA internal RAM, stores next ATM cell delivery time Time0 of each PVC passage, to treat flow-control module 211 inquiries; Receive the state initialization command that flow-control module 211 sends simultaneously, the state of each PVC is carried out clear operation.
PVC band width configuration module 206, it is a FPGA internal RAM, be used for disposing the bandwidth parameter of each PVC passage, bandwidth parameter is to be reference with reference clock 19.44MHz, be close to (as shown in Figure 3) that two ATM cell clock intervals (Step) obtain by calculating same PVC passage, and the parameter that obtains is arrived PVC band width configuration module 206 by CPU (primary processor) interface configuration.
Flow-control module 211 is nucleus modules of realizing the control of ATM cell flow, when sends the ATM cell of which PVC passage by these module 211 decisions, also determine simultaneously two adjacent between the interval of ATM cell.Flow-control module 211 comprises four modules such as ATM cell sending module 207, cell frame buffer 208, bandwidth control module 209 and benchmark moment generation module 210 again.Wherein,
Wherein, ATM cell sending module 207 is state machines, continuous each PVC passage of poll, produce the operation of modules such as inquiry pvc management module 204, pvc state cache module 205, PVC band width configuration module 206 and bandwidth control module 209, read address ram to 201 transmissions of ATM cell memory, the parameter S tep0 that ATM cell of coming reading back and bandwidth control module 209 are returned forms the cell frame according to the form of Fig. 4, deposit in the cell frame buffer 208, parameter S tep0 is the ATM cell spacing parameter.
Wherein, cell frame buffer 208 is fifo queues that are used for storing the ATM cell frame.
Wherein, bandwidth control module 209 is arithmetic elements, safeguards two variablees simultaneously, and one is the delivery time Time1 of a last ATM cell, and another is time interval of the maximum bandwidth of system configuration to count Step1.Bandwidth control module 209 will inquire about Time0 value that pvc state cache module 205 returned respectively with benchmark constantly the value of the delivery time Time1 of the Counter_1 value of generation module 210 and a last ATM cell compare, whether decision allows ATM cell sending module 207 constantly to read an ATM cell from ATM cell memory 201 at this, and the PVC channel status is safeguarded.
Wherein, benchmark generation module 210 constantly is counter Counter_1, is the reference clock parameter, 19.440MHz clock is its clock source, one second circulation primary, the benchmark as bandwidth control module 209 judgement produces initialization pvc state cache module 205 signals simultaneously.
Cell frame sending module 212 is Executive Modules of realizing the control of ATM cell flow, and it safeguards that is used for calculating an adjacent ATM cell counter Counter_2 at interval.Cell frame sending module 212 continuous query flows control modules 211 if flow-control module 211 allows to read a cell frame, then at first read cell frame head Step0, and Counter_2 compares with frame head Step0 sum counter; If the Step0 value allows to send ATM cell less than Counter_2 value and physical interface module 213, ATM cell is sent to physical interface module 213, otherwise wait for that physical interface module 213 allows to send ATM cell.
See also shown in Figure 5ly, be PVC bandwidth chahnel control and treatment flow chart of the present invention.And in conjunction with Fig. 2, as follows for the step of bandwidth control module 209 data processing of the present invention:
Step a, read PVC channel status parameter, after ATM cell sending module 207 sends querying command, bandwidth control module 209 is from read back next ATM cell delivery time Time0 of this PVC passage of pvc state cache module 205, simultaneously from the read back PVC bandwidth chahnel configuration parameter Step of system of PVC band width configuration module 206.
Step b, Time0 and Counter_1 and Time1 are compared, bandwidth control module 209 compares next ATM cell delivery time Time0 respectively with reference clock parameters C ounter_1 and the last ATM cell delivery time Time1 of system, judge whether to allow ATM cell sending module 207 to send ATM cell.
Whether step c judges Time0 smaller or equal to Counter_1, carries out if next ATM cell delivery time Time0, then forwards steps d to smaller or equal to reference clock parameters C ounter_1, carries out otherwise forward step I to.
Whether steps d judges Time0 smaller or equal to Time1, carries out if next ATM cell delivery time Time0, then forwards step e to smaller or equal to the last ATM cell delivery time Time1 of system, and this does not forward the step g execution to.
Whether step e judges Time1 smaller or equal to Counter_1, carries out if the last ATM cell delivery time Time1 of system, then forwards step f to smaller or equal to reference clock parameters C ounter_1, carries out otherwise forward step h to.
Step f upgrades each parameter, undated parameter Time0 and Time1, and return ATM cell spacing parameter Step0, use for ATM cell sending module 207.At this moment the value of next ATM cell delivery time Time0 is Counter_1 and Step sum, and the value of a last ATM cell delivery time Time1 is the value of current C ounter_1 just.ATM cell spacing parameter Step0 is zero.
Step g is upgraded each parameter, undated parameter Time0 and Time1, and return ATM cell spacing parameter Step0, use for ATM cell sending module 207.At this moment the value of next ATM cell delivery time Time0 is Counter_1 and Step sum, and the value of a last ATM cell delivery time Time1 is the value of current C ounter_1 just.ATM cell spacing parameter Step0 is zero.
Step h upgrades each parameter, undated parameter Time0 and Time1, and return ATM cell spacing parameter Step0, use for ATM cell sending module 207.At this moment the value of next ATM cell delivery time Time0 is Time1 and Step sum, and the value of a last ATM cell delivery time Time1 is constant.ATM cell spacing parameter Step0 is zero.
Whether step I judges Time0 smaller or equal to Time1, carries out if next ATM cell delivery time Time0, then forwards step n to smaller or equal to the last ATM cell delivery time Time1 of system, carries out otherwise forward step j to.
Whether step j judges Time1 smaller or equal to Counter_1, carries out if the last ATM cell delivery time Time1 of system, then forwards step k to smaller or equal to reference clock parameters C ounter_1, otherwise forwards step to.Carry out.
Step k, undated parameter Step0, the value of ATM cell spacing parameter Step0 is the poor of next ATM cell delivery time Time0 and reference clock parameters C ounter_1.
Whether step 1 judges Step0 smaller or equal to Step1, if ATM cell spacing parameter Step0 counts Step1 smaller or equal to the time interval of the maximum bandwidth of system configuration, then forwards step m to and carries out, and carries out otherwise forward step q to.
Step m upgrades each parameter, undated parameter Time0 and Time1, and return ATM cell spacing parameter Step0, use for ATM cell sending module 207.At this moment the value of next ATM cell delivery time Time0 is Time0 and Step sum, and the value of a last ATM cell delivery time Time1 is the Time0 value before upgrading.ATM cell spacing parameter Step0 remains unchanged.
Step n upgrades each parameter, undated parameter Time0 and Time1, and return ATM cell spacing parameter Step0, use for ATM cell sending module 207.At this moment the value of next ATM cell delivery time Time0 is Time1 and Step sum, and the value of a last ATM cell delivery time Time1 remains unchanged.ATM cell spacing parameter Step0 is zero.
Step o, undated parameter Step0, the value of ATM cell spacing parameter Step0 is the poor of next an ATM cell delivery time Time0 and a last ATM cell delivery time Time1.
Step p is provided with and allows the transmission sign, and bandwidth control module 209 is provided with a flag bit, shows to allow ATM cell sending module 207 to read an ATM cell from ATM cell memory 201.
Step q returns, and judgement is finished, and next ATM cell delivery time Time0 is deposited back in the pvc state cache module 205, and return step a, waits for next operation.
See also shown in Figure 6ly, be ATM cell process chart of the present invention.As follows for the treatment step that enters ATM cell of the present invention:
Step 2 judges whether to carry out initialization operation, and the inquiry benchmark is generation module 210 states constantly, if second timing finishes, then returns step 1 and carries out initialization operation, otherwise continue to carry out next step operation.
Step 3 produces the PVC channel number, and ATM cell sending module 207 generates the PVC channel number that needs inquiry.
Step 4, inquiry PVC passage is inquired about pvc management module 204 according to the PVC channel number that step 3 produces.
Step 5 judges whether the PVC passage of being inquired about has ATM cell to send, and when inquiry pvc management module 204, pvc management module 204 is returned the fifo queue state of corresponding PVC passage.If there is ATM cell to send, then next step changes step 6 execution over to, otherwise returns step 2.
Step 6, the inquiry strip width controller is inquired about bandwidth control module 209 according to the PVC channel number that step 3 produces.
Step 7 judges whether to allow to read, the value that ATM cell sending module 207 returns according to bandwidth control module 209 and cell frame buffer 208, and whether decision reads an ATM cell from ATM cell memory 201.If allow to read an ATM cell, then next step changes step 8 execution over to, otherwise returns step 2.
Step 8, read ATM cell and encapsulated frame, ATM cell sending module 207 read an ATM cell from ATM cell memory 201, and the value Step0 that returns according to inquiry bandwidth control module 209 is assembled into a cell frame from the read back start address of ATM cell of pvc management module 204.
Step 9, storage cell frame, ATM cell sending module 207 deposits the cell frame that assembles in the cell frame buffer 208 in, and cell flag of frame position is set, and has at least one complete cell frame in cell frame sending module 212 expression cell frame buffers 208.
Step 10 is returned, and the encapsulation of cell frame is finished, and returns step 2.
Step 11, inquiry cell frame buffer, the cell flag of frame position of cell frame sending module 212 continuous query flows control modules 211.
Step 12, whether in cell frame buffer 208 have cell frame, if having, then forward next step execution to, otherwise return step 11 if judging.
Step 13 reads the cell frame head, and at first cell frame sending module 212 only reads the cell frame head of a word from cell frame buffer 208, obtains ATM cell spacing parameter Step0.
Step 14, query counts device Counter_2, cell frame sending module 212 reads the currency of counter Counter_2.
Step 15 judges whether to allow to send this ATM cell, and cell frame sending module 212 compares the value of Step0 and Counter_2, if the value of Step0 is less than or equal to the Counter_2 value, then forwards next step execution to, otherwise turns back to step 14.
Step 16 with the zero clearing of counter Counter_2 value, continues counting after the counter Counter_2 zero clearing.
Step 17 sends ATM cell, and cell frame sending module 212 continues to read the further part of cell frame from cell frame buffer 208, does not promptly contain the cell frame of frame head, and ATM cell is sent to physical interface module 213.
Step 18, return, after a cell frame sends, return step 11.
Adopt the method for the invention and device to obtain and use FPGA to replace the technological progress that special-purpose SAR chip is realized flow control, reached the effect of accurate control ATM cell speed, saved system cost, improved system reliability and market competitiveness or the like.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.
Claims (13)
1, a kind of device based on the flow control of FPGA realization atm network comprises network processing unit, physical chip, it is characterized in that, also comprises:
One ATM cell memory is used to receive the ATM cell that described network processing unit transmits, and stores described ATM cell by PVC passage piecemeal;
One pvc management module is used for described ATM cell memory is invented a plurality of fifo queues according to PVC, and described each fifo queue is managed;
One pvc state cache module is used to store next ATM cell delivery time variable of each PVC passage;
One PVC band width configuration module is used to dispose the bandwidth parameter of each PVC passage;
One flow control module, be used to produce the PVC channel number, inquire about described pvc management module, pvc state cache module and PVC band width configuration module, whether the passage that calculates this PVC channel number correspondence has ATM cell and whether allows to read ATM cell, and the assembling ATM cell becomes cell frame and storage;
One cell frame sending module is used for reading the cell frame from described flow-control module, carries out ATM cell and controls at interval, and send the cell frame that does not contain frame head;
One physical interface module is used to receive the cell frame that described cell frame sending module is sent, and it is sent to described physical chip.
2, the device of realizing the atm network flow control based on FPGA according to claim 1 is characterized in that described ATM cell memory comprises again: an External memory equipment and a memory interface module; Described External memory equipment is used to store ATM cell, and described memory interface module is carried out the interface module of exchanges data as External memory equipment and FPGA internal logic.
3, the device of realizing the atm network flow control based on FPGA according to claim 1, it is characterized in that described flow-control module comprises again: an ATM cell sending module, a cell frame buffer, a bandwidth control module and a benchmark be generation module constantly; Wherein
Described ATM cell sending module is used to inquire about described each PVC passage, produce the operation of the described pvc management module of inquiry, pvc state cache module, PVC band width configuration module and bandwidth control module, read address ram to described ATM cell memory transmission, the parameter that the ATM cell of reading back and described bandwidth control module are returned is formed the cell frame according to certain form, and deposit in to described cell frame buffer;
Described cell frame buffer is used to store the fifo queue of cell frame;
Described bandwidth control module is used to safeguard the time interval number variable of the maximum bandwidth of an ATM cell delivery time variable, system configuration, inquire about next ATM cell delivery time variate-value that described pvc state cache module returns respectively with the benchmark count variable value of generation module and the situation that a last ATM cell delivery time variate-value compares constantly, whether decision allows described ATM cell sending module to read ATM cell at this next ATM cell delivery time from described ATM cell memory according to comparative result, and the PVC channel status is safeguarded;
Described benchmark generation module constantly is a counter, is used to produce the described counting variable as described bandwidth control module judgement benchmark, and produces the signal of the described pvc state cache module of initialization.
4, according to claim 1, the 2 or 3 described devices of realizing the atm network flow control based on FPGA, it is characterized in that described physical interface module is a standard Utopia interface.
5, a kind of method based on the flow control of FPGA realization atm network that is applicable to the described device of claim 1 is characterized in that, comprising:
Step 51, the ATM cell memory receives the ATM cell that described network processing unit transmits, and stores described ATM cell by PVC passage piecemeal;
Step 52, flow-control module produces the PVC channel number, constantly inquire about described pvc management module, pvc state cache module and PVC band width configuration module, whether the passage that calculates this PVC channel number correspondence has ATM cell and whether allows to read ATM cell, and the assembling ATM cell becomes cell frame and storage;
Step 53, cell frame sending module reads the cell frame from described flow-control module, carry out ATM cell and control at interval, and send the cell frame that does not contain frame head;
Step 54, physical interface module receive the cell frame that described cell frame sending module is sent, and it is sent to described physical chip.
6, the method that realizes the atm network flow control based on FPGA according to claim 5, it is characterized in that, comprise also between the described step 51,52 that a pvc state initialization command that sends by flow-control module carries out initialized step to described pvc state cache module, be used for next ATM cell pointer of all PVC passages is all pointed to zero.
7, the method that realizes the atm network flow control based on FPGA according to claim 5, it is characterized in that, comprise also in the described step 52 that the fifo queue state of passage by inquiring about this PVC channel number correspondence that described pvc management module returns judges whether the passage of this PVC channel number correspondence has the step of ATM cell.
8, the method that realizes the atm network flow control based on FPGA according to claim 5, it is characterized in that, comprise also in the described step 52 that a value of returning by described bandwidth control module, cell frame buffer judges whether to allow described ATM cell sending module to read the step of ATM cell from described ATM cell memory.
9, according to claim 5,6, the 7 or 8 described methods that realize the atm network flow control based on FPGA, it is characterized in that, in the described step 52, if the passage of this PVC channel number correspondence allows to read ATM cell, then described ATM cell sending module reads ATM cell from described ATM cell memory, and adds a control word at interval at the head of this ATM cell, forms a cell frame and deposits to described cell frame buffer, cell flag of frame position is set, waits for that described cell frame sending module reads; Pvc state after will upgrading simultaneously writes back described pvc state cache module, continues next PVC passage of inquiry.
10, according to claim 5,6, the 7 or 8 described methods that realize the atm network flow control based on FPGA, it is characterized in that, comprised also after the step 52 that before described step 53 a described cell frame sending module judges the step that whether contains the cell frame in the described cell frame buffer by the cell flag of frame position of query flows control module.
11, according to claim 5,6, the 7 or 8 described methods that realize the atm network flow control based on FPGA, it is characterized in that, comprised also after the step 52 that before described step 53 one judges whether to allow described cell frame sending module to read the step of cell frame from described cell frame buffer.
12, according to claim 5,6, the 7 or 8 described methods that realize the atm network flow control based on FPGA, it is characterized in that, in the described step 53, described cell frame sending module obtains the counter currency by starting an interval counter, and read the cell frame head by inquiry cell frame buffer and obtain an ATM cell spacing parameter, the mode by more described counter currency and described ATM cell spacing parameter realizes that ATM cell controls at interval again.
13, the method that realizes the atm network flow control based on FPGA according to claim 12, it is characterized in that, if described ATM cell spacing parameter value allows to send ATM cell less than described counter currency and described physical interface module, then described cell frame sending module is sent to described physical interface module with ATM cell.
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| CN101977155B (en) * | 2010-11-18 | 2012-04-25 | 无锡源清高新技术研究所有限公司 | Virtual bandwidth adaptive control system and control method thereof |
| CN102164095B (en) * | 2011-05-31 | 2014-07-02 | 西安空间无线电技术研究所 | Datagram segmentation and reassembly system and realization method for onboard switching module |
| CN103391329B (en) * | 2013-07-12 | 2017-06-20 | 青岛海信宽带多媒体技术有限公司 | A kind of interface module and its method for supporting multiplex roles standard |
-
2005
- 2005-12-14 CN CNB2005101306034A patent/CN100486224C/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105812282A (en) * | 2016-05-12 | 2016-07-27 | 苏州联视泰电子信息技术有限公司 | ATM (Asynchronous Transfer Mode) branching and combining device based on FPGA |
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