JP4577154B2 - Verification simulator and verification simulation method - Google Patents

Description

  The present invention relates to a verification simulator and a verification simulation method.

  A display driver (LCD driver) is a device for driving a display panel such as a liquid crystal panel. This display driver requires a verification simulation for confirming the operation before actually manufacturing the display driver. In the conventional verification simulation method, a test pattern (test input information) is created as binary data using a description of Verilog, which is one of logic verification languages.

However, the specifications of the display driver, which is a device to be verified, have become more complex year by year, and it has become unrealistic to create a test pattern by inputting binary data signals. There are various types of interface signals input to the display driver, and it is not easy to create test patterns for all of these various types of interface signals.
Japanese Patent Laid-Open No. 11-25140

  The present invention has been made in view of the technical problems as described above, and an object thereof is to provide a verification simulator and a verification simulation method capable of facilitating the creation of test input information.

  The verification simulator according to the present invention includes a storage unit that stores information of a model in which the operation of the device is described, and a simulation processing unit that performs a simulation process of the verification target device based on the model and the test input information, The model includes a verification target device model in which an operation of the verification target device is described, and an external interface circuit model in which an operation of an external interface circuit included in an external device of the verification target device is described, and the test input information Includes a command file in which a command to be set in the register of the verification target device is described, and the simulation processing unit inputs the command file to the external interface circuit model, and the external interface is based on the command file. Times The data given in the form of interface signals generated by the model, relating to verification simulator for simulating processing to be input to the verification target device model.

  According to the present invention, the test input information includes a command file in which commands to be set in the register of the verification target device are described. This command file is input to the external interface circuit model, and interface signal data generated by the external interface circuit model is input to the verification target device model. This makes it easy to create test input information by creating a command file that lists commands and generating interface signal data in various formats and entering it into the verification target device model. Can be

  In the present invention, the interface signal includes at least one of an MPU interface signal, an RGB interface signal, a serial interface signal, and a YUV interface signal, and the simulation processing unit is configured to generate the MPU interface generated by the external interface circuit model. A simulation process may be performed in which data of at least one of the signal, the RGB interface signal, the serial interface signal, and the YUV interface signal is input to the verification target device model.

  In the present invention, the command file includes an interface mode designation command, and the simulation processing unit inputs the data of the interface signal in the format designated by the interface mode designation command to the verification target device model. May be performed.

  In this way, it is possible to generate interface signal data in various formats and input it to the verification target device model simply by changing the interface mode designation command.

  In the present invention, the command file includes an operation mode designation command for a verification target device, and the simulation processing unit sets an interface signal for setting the verification target device to an operation mode designated by the operation mode designation command. A simulation process may be performed in which the above data is input to the verification target device model.

  In this way, it is possible to input the interface signal data for setting the verification target device in various operation modes to the verification target device model and execute the simulation process.

  In the present invention, the verification target device model includes an internal interface circuit model in which an operation of the internal interface circuit included in the verification target device is described, and the simulation processing unit is generated by the external interface circuit model. A simulation process may be performed in which data of the interface signal in a given format is input to the internal interface circuit model.

  In this way, it is possible to input various types of interface signal data generated by the external interface circuit model to the internal interface circuit model and execute simulation processing.

  In the present invention, the model includes a display driver model in which an operation of a display driver that is the verification target device is described, and a display panel model in which an operation of a display panel driven by the display driver is described, The simulation processing unit may perform a simulation process based on the test input information, the external interface circuit model, the display driver model, and the display panel model.

  In this way, it is possible to facilitate the creation of test input information in the simulation process of the display driver that is the verification target device. In addition, a system simulation can be realized with a mounting image with a display panel model added.

  In the present invention, the display driver model includes a logic circuit model in which an operation of a logic circuit that generates a display control signal is described, and the simulation processing unit uses a netlist of the logic circuit as the logic circuit model. You may make it do.

  In this way, the verification simulation method of the present invention can be easily applied to display drivers of various specifications.

  In the present invention, the display driver model includes a data driver model in which an operation of a data driver that outputs a data signal is described, and the simulation processing unit includes N-bit (N> 2) data for each data line. You may make it perform the simulation process which inputs the data of a signal from the said data driver model to the said display panel model.

  In this way, even when the display driver includes an analog circuit, the operation of the display driver can be verified by digital logic simulation.

  In the present invention, the display driver model includes a display memory model in which an operation of a display memory for storing gradation data as image data is described, and the simulation processing unit includes an N-bit from the display memory model. Grayscale data is stored in each internal register of the data driver model provided for each data line, and the N-bit grayscale data stored in each internal register is used as data signal data in the display panel model. You may make it perform the simulation process input into this.

  In this way, the analog operation of the data driver can be simulated in a pseudo manner simply by providing a virtual internal register. Therefore, while using a simple model, analog control operations and the like can be verified by digital logic simulation, and verification efficiency can be improved.

  In the present invention, the model includes a socket model virtually provided between the display driver model and the display panel model, and the display driver model generates a gradation voltage generation circuit that generates a gradation voltage. And a data driver model in which an operation of a data driver that outputs a data signal based on the generated gradation voltage is described, and the simulation processing unit includes the socket Serial grayscale voltage data generated by the model is input to the data driver model via the grayscale voltage generation circuit model, and serial data from the data driver model is input to the socket model to obtain parallel data. The display panel module converts the parallel data obtained by the conversion as data signal data. It may be performed a simulation process of inputting Le.

  In this way, it is possible to effectively prevent a simulation malfunction caused by a defect in the analog operation model. Then, it becomes possible to accurately verify the gradation voltage generation circuit and the data driver at the actual circuit level.

  The present invention is also a verification simulation method for performing simulation processing of a verification target device based on a model in which device operation is described and test input information, wherein the model describes the operation of the verification target device. A verification target device model, and an external interface circuit model in which an operation of an external interface circuit included in the external device of the verification target device is described, and the test input information is a command to be set in a register of the verification target device The command file is input to the external interface circuit model, and the interface signal data of a given format generated by the external interface circuit model based on the command file is input to the verification target. De It related to the verification simulation method for performing a simulation process to be input to the chair model.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Display Driver FIG. 1 shows a configuration example of a display driver 510 which is an example of a verification target device of the verification simulator of this embodiment. The configuration of the display driver 510 is not limited to that shown in FIG. 1, and various modifications can be made. Further, the verification target device of the verification simulator of the present embodiment is not limited to the display driver 510, and various devices can be adopted. For example, the verification target device may be a host device such as a baseband engine, an application processor, or an image processing controller.

  The display panel 512 includes a plurality of data lines (source lines), a plurality of scanning lines (gate lines), and a plurality of pixels specified by the data lines and the scanning lines. A display operation is realized by changing the optical characteristics of the electro-optical element (in a narrow sense, a liquid crystal element) in each pixel region. This display panel 512 can be constituted by an active matrix type panel using switching elements such as TFT and TFD. Note that the display panel 512 may be a panel other than the active matrix method, or may be a panel other than the liquid crystal panel (such as an organic EL panel).

  The display memory 520 (RAM) stores image data. The memory cell array 522 includes a plurality of memory cells and stores image data (display data) for at least one frame (one screen). A row address decoder 524 (MPU / LCD row address decoder) performs a decoding process on the row address and performs a word line selection process of the memory cell array 522. A column address decoder 526 (MPU column address decoder) performs a decoding process on the column address and performs a selection process of a bit line of the memory cell array 522. The write / read circuit 528 (MPU write / read circuit) performs image data write processing to the memory cell array 522 and image data read processing from the memory cell array 522.

  The logic circuit 540 (for example, automatic placement and routing circuit) generates a display control signal for controlling display timing and data processing timing. The logic circuit 540 can be formed by automatic placement and routing such as a gate array (G / A). The control circuit 542 generates various control signals and controls the entire apparatus. A display timing control circuit 544 generates a display timing control signal and controls reading of image data from the display memory 520 to the display panel 512 side.

  The internal interface circuit 545 (driver-side interface circuit) is a circuit that performs interface processing with an external device (such as a host device), and includes a host interface circuit 546 and an RGB interface circuit 548. A host (MPU) interface circuit 546 implements a host interface that generates an internal pulse and accesses the display memory 520 for each access from the host. The RGB interface circuit 548 realizes an RGB interface that writes moving image RGB data to the display memory 520 using a dot clock. Note that only one of the host interface circuit 546 and the RGB interface circuit 548 may be provided. Alternatively, a YUV interface circuit that realizes an interface with a camera device or the like may be provided. Alternatively, a high-speed serial interface circuit that realizes high-speed serial transfer via a serial bus may be provided. In this high-speed serial transfer, high-speed serial transfer with an external device (such as a host device) is realized by current driving or voltage driving the differential signal line of the serial bus.

  The data driver 550 is a circuit that generates a data signal for driving the data lines of the display panel 512. Specifically, the data driver 550 receives gradation data as image data from the display memory 520 and receives a plurality of (for example, 64 levels) gradation voltages (reference voltages) from the gradation voltage generation circuit 610. Then, a voltage corresponding to the gradation data is selected from the plurality of gradation voltages and is output to each data line of the display panel 512 as a data signal (data voltage).

  The scan driver 570 is a circuit that generates a scan signal for driving the scan lines of the display panel. Specifically, a signal (enable input / output signal) is sequentially shifted in a built-in shift register, and a signal obtained by converting the level of the shifted signal is output to each scanning line of the display panel 512 as a scanning signal (scanning voltage). To do. The scan driver 570 includes a scan address generation circuit and an address decoder, the scan address generation circuit generates and outputs a scan address, and the address decoder performs a scan address decoding process to generate a scan signal. Also good.

  The power supply circuit 590 is a circuit that generates various power supply voltages. Specifically, the input power supply voltage and the internal power supply voltage are boosted by a charge pump method using a boosting capacitor and a boosting transistor included in a built-in boosting circuit. The voltage obtained by the boosting is supplied to the data driver 550, the scan driver 570, and the gradation voltage generation circuit 610 as a power supply voltage.

  The gradation voltage generation circuit 610 (γ correction circuit) is a circuit that generates gradation voltages. Specifically, the built-in voltage dividing circuit (selection voltage generating circuit) generates a divided voltage, and the built-in gradation voltage generating circuit has, for example, 64 (64 gradations) among the generated divided voltages. A gradation voltage is selected and output to the data driver 550.

2. Verification Simulator When verifying the operation of a verification target device such as the display driver 510 shown in FIG. 1, the conventional verification simulation technique uses a Verilog description as shown in FIG. (Input information) was created with binary data of (1, 0) and input to the device model 2 to be verified. Alternatively, the signal input of the test pattern is described as a task, and it is used repeatedly to simplify the signal input. The verification target device model 2 is a model in which the operation of the verification target device is described.

  However, the specifications of the display driver, which is a device to be verified, have become more complex year by year, and it has become unrealistic to create a test pattern by inputting binary data signals. Also in the method using task description, if descriptions of interface signals in a plurality of formats are prepared individually, it is necessary to describe different test patterns for each specification. This causes problems such as complicated management of test patterns.

  Therefore, in the present embodiment, as shown in FIGS. 2B and 2C, an external interface circuit model 130 in which the operation of the external interface circuit included in the external device of the verification target device is described is prepared. That is, an external interface circuit model 130 that generates an interface signal input to the internal interface circuit model of the verification target device model 2 is prepared. Further, the test input information 150 (test bench) includes a command file 152 in which commands to be set in the register of the verification target device are described.

  Then, the command file 152 is input to the external interface circuit model 130, and simulation processing is performed in which the interface signal data (binary data) generated by the external interface circuit model 130 based on the command file is input to the verification target device model 2. For example, in FIG. 2B, the interface signal data in the first format is generated by the external interface circuit model 130 and input to the verification target device model 2. On the other hand, in FIG. 2C, the interface signal data in the second format is generated by the external interface circuit model 130 and input to the verification target device model 2.

  As described above, in the method according to the present embodiment, by providing the external interface circuit model 130, data of interface signals in various formats can be generated and input to the verification target device model 2.

  FIG. 3 shows a configuration example of a verification simulator that can realize the method of the present embodiment, and FIG. 4 shows an example of a simulation environment of the verification simulator. In the following description, the case where the verification target device is a display driver will be mainly described as an example.

  In FIG. 3, the storage unit 200 stores model information in which operations of devices such as a display driver, a display panel, and an external device (host device) are described. The function of the storage unit 200 is realized by hardware such as a memory (RAM) or a hard disk incorporated in a verification workstation (computer system in a broad sense). Further, as models for storing the information in the storage unit 200, a behavior level model having a high abstraction level such as a Verilog behavior model, an RTL (Register Transfer Level) model having a lower abstraction level than the behavior level, and the like. A logic level model such as a netlist having a lower abstraction level than RTL can be used.

  The simulation processing unit 210 (simulation execution unit) performs a simulation process for the verification target device based on the model stored in the storage unit 200 and the test input information 150. The function of the simulation processing unit 210 can be realized by hardware such as a CPU incorporated in the verification work system and verification software. As the verification software, logic simulation software such as Verilog may be used, analog simulation software such as SPICE, or a mixture of logic simulation software and analog simulation software is used. May be.

  The test input information 150 (test bench, test data) can include a command file 152. The command file 152 describes a command for operating the display driver (device to be verified in a broad sense) and parameters to be set in the register (command register). That is, these commands are listed and described in the command file 152. The test input information 150 can include image data 154 such as RGB data. The image data 154 can be extracted from the image data file 156 for test input.

  The image data file 160 output by the simulation processing unit 210 displays an image to be displayed on the display panel by the image data 154 included in the test input information 150 on the display device (CRT, monitor) of the verification workstation. Is. As the image data file 160, the simplest PPM (Portable Pix Map) image format in the ASCII format can be used. If PPM is used, image data can be easily displayed on a display device of a workstation by UNIX utility software or the like.

  As shown in FIG. 4, as a model constituting the simulation environment, there are a display driver model 10 in which the operation of the display driver is described, and a display panel model 90 in which the operation of the display panel driven by the display driver is described. There is also an external interface circuit model 130 in which the operation of an external interface circuit (host side interface circuit) included in an external device of the display driver is described. Note that a nonvolatile memory model in which the operation of the nonvolatile memory (EEPROM) for setting the initial state of the display driver is described may be used. Examples of external devices including an external interface circuit include devices (host devices) such as an MPU (Micro Processor Unit), a baseband engine, an application processor, and an image processing controller (display controller).

  In FIG. 4, the display driver model 10 includes a data driver model 20 in which an operation of a data driver that outputs a data signal is described. Also included are a scan driver model 30 in which the operation of a scan driver that outputs a scan signal is described, and a display memory model 40 in which the operation of a display memory that stores gradation data that is image data is described. The display driver model 10 includes a power supply circuit model 50 in which the operation of the power supply circuit is described, a gradation voltage generation circuit model 60 in which the operation of the gradation voltage generation circuit that generates the gradation voltage is described, and a display control signal. Includes a logic circuit model 70 in which the operation of the logic circuit that generates at least is described. Also included is an internal interface circuit model 80 in which operations of internal interface circuits such as an MPU interface circuit, RGB interface circuit, YUV interface circuit, and high-speed serial interface circuit are described.

  In this embodiment, the simulation processing unit 210 in FIG. 3 performs a simulation process based on the test input information 150, the display driver model 10, and the display panel model 90. Specifically, the command file 152 is input to the external interface circuit model 130, and the data of the interface signal of a given format generated by the external interface circuit model 130 based on the command file 152 is displayed as a verification target device model. A simulation process to be input to the driver model 10 is performed.

  In this case, the interface signals that can generate data by the external interface circuit model 130 include an MPU interface signal and an RGB interface signal. Alternatively, there are serial interface signals (CMOS level serial interface signals, differential serial interface signals) and YUV interface signals. The simulation processing unit 210 converts the data of at least one of the MPU interface signal, the RGB interface signal, the serial interface signal, and the YUV interface signal generated by the external interface circuit model 130 into a display driver model that is a verification target device model. The simulation process input to 10 is performed.

  As shown in FIG. 4, according to the present embodiment, it is possible to realize a system simulation with a mounting image in which peripheral device models such as the display panel model 90 and the external interface circuit model 130 are added. In addition, analog blocks (data driver, scan driver, gradation voltage generation circuit, power supply circuit, etc.) inside the display driver are modeled using a Verilog behavior model. In addition, simulation results are converted to enable visual verification of the displayed image.

  Specifically, a command file 152 (MPU command) described as a test bench is input to the external interface circuit model 130 (MPU model), and MPU interface signals, RGB interface signals, etc. are converted by the external interface circuit model 130 conversion processing. The interface signal data is generated. Then, binary data of the interface signal is input to the terminal of the display driver model 10. Similarly, image data 154 to be displayed on the screen is also input to the display driver model 10 via the external interface circuit model 130. For example, RGB format data is used as the image data 154. YUV format data may be used.

  Further, the internal blocks of the display driver are mostly analog blocks including analog circuits except for the logic circuit (gate array). The analog block cannot verify the correct operation by the Verilog logic simulation by the netlist output, so the Verilog behavioral model describing the block level operation is used. Although the verification level of the analog operation varies depending on how to create the behavior model of the analog block, in this embodiment, an analog control operation such as a power-on sequence can be verified by a logic simulation.

  Specifically, there are the following special expressions of the behavior model of the analog block. For example, a data driver D / A converts grayscale data from a display memory to generate a data voltage that is a grayscale voltage. However, the gradation voltage value is an analog value and cannot be expressed by a logic simulator. Therefore, in FIG. 4, for example, 6-bit (N-bit in a broad sense) gradation data that is image data from the display memory model 40 is stored in virtual internal registers provided in the data driver model 20. Then, conversion processing (polarity inversion processing, RGB inversion processing, color reduction mode processing, etc.) is performed on the gradation data stored in each internal register, and the gradation data after the conversion processing is converted into data signal data To the display panel model 90.

  The scanning voltage value output to the scanning signal of the display panel is an analog value and cannot be expressed by logic simulation. Therefore, in the scan driver model 30, the generation of the scan voltage (selection voltage) is expressed by logic “1”.

  Further, the potential difference of the voltage generated by the boosting operation is an analog value and cannot be expressed by logic simulation. Therefore, in the power supply circuit model 50, the boosting condition is determined, and the generation of the boosted voltage is expressed by logic “1”. That is, when the boost condition is satisfied, a logic “1” is output. Similarly, the gradation voltage value obtained by resistance division is an analog value and cannot be expressed by logic simulation. Therefore, in the gradation voltage generation circuit model 60, the operating condition is determined, and the generation of the gradation voltage is expressed by logic “1”. That is, when the operating condition is satisfied, a logic “1” is output. Then, if the power supply circuit and the gradation voltage generation circuit are not operating normally, create a behavior model for the data driver and scan driver so that the data driver and scan driver that operate by receiving signals from these circuits do not operate. . That is, the data driver model 20 and the scan driver model 30 are created so that the operation is not started unless the logic “1” is output from the power supply circuit model 50 or the gradation voltage generation circuit model 60. By doing so, analog control operations such as a power-on sequence can be verified by logic simulation.

  In FIG. 4, a logic circuit (gate array) netlist is used as the logic circuit model 70. That is, the logic circuit (540 in FIG. 1) does not include an analog element and can directly input the net list to a logic simulator such as Verilog. The configuration and operation of the logic circuit are changed as needed according to the specifications. Therefore, for the logic circuit model 70, a logic simulation such as Verilog is performed using the net list of the logic circuit as it is. By doing so, the simulation accuracy can be improved, and the verification simulation method of the present embodiment can be easily applied to display drivers of various specifications. Note that the internal interface circuit model 80 may also use a net list of the internal interface circuit for at least a part thereof.

3. Details of Method Using External Interface Circuit Model Next, details of the method of this embodiment using the external interface circuit model 130 will be described. FIG. 5 shows an example of the command file 152. IMODE indicated by C1 in FIG. 5 is a command for designating an interface mode. In the external interface circuit model 130, interface signal data in a format specified by this IMODE is generated and input to the display driver model 10. For example, in C1 of FIG. 5, a mode of an MPU interface signal capable of reading and writing RAM is specified with a bus width of 16 bits.

  CmdVDDON indicated by C2 in FIG. 5 is a command for setting the VDD regulator in an operating state and starting an internal reference voltage generation circuit. CmdSoftReset shown in C3 is a command for performing a reset (soft reset) similar to a hard reset without performing a hard reset. CmdSetPwrCtl shown in C4 is a command for performing power setting for controlling ON / OFF of the function of the power circuit and capability, and details of the power setting are specified by parameters. CmdSetPtlPwrCtl shown in C5 is a command for setting the power supply in the non-display area and the front porch period at the time of partial display, and details of the power supply setting are specified by parameters.

  CmdSetScanMod shown in C6 is a command for setting the scan mode of the scan driver. For example, forward scan or reverse scan is set by a parameter. CmdSetAltDrv shown in C7 is a command for setting the AC drive state. For example, 1-line inversion drive, 2-line inversion drive, frame inversion drive, and interlace drive are set according to parameters. CmdSleepOut shown in C8 is a command for executing an automatic on sequence. CmdWrRam shown in C9 is a write command to the RAM which is the display memory. TaskFillMem shown in C10 is a command for designating and sending image data. CmdOnDisp shown in C11 is a command for turning on the display panel. By this command, the image data stored in the display memory is converted into a gradation voltage, and image display on the display panel is started. CmdPartialIn shown in C12 and C13 is a command for setting a partial display state, and a partial start line and a partial end line are set by parameters. C14 and C15 are used for designating the wait time.

  The operation mode of the display driver (verification target device) is designated by a command described in the command file 152 as shown in FIG. Then, data of an interface signal for setting the display driver in the operation mode specified by these commands is input to the display driver model 10.

  6A and 6B show examples of MPU interface signals. FIG. 6A shows an example at the time of writing, and FIG. 6B shows an example at the time of reading. As shown in FIGS. 6A and 6B and FIG. 7A, the data / command identification signal A0 is “0” (low level) and the write signal XWR (X represents negative logic) is “0”. In some cases, command write is performed, and when the signal A0 is “0” and the read signal XRD is “0”, revision read is performed. When the signal A0 is “1” (high level) and the signal XWR is “0”, RAM write (write of image data to the display memory) or command parameter write is performed, and the signal A0 is “1”. When the signal XRD is “0”, RAM read (reading of image data from the display memory) is performed.

  FIG. 6C shows an example of a serial interface signal. FIG. 6C shows an example of a serial interface signal at the time of writing. In FIG. 6C, D / C means identification of data and command, and Cn means bit n of the command. Pn means bit n of the command parameter. During the transfer of 9-bit serial data (1 packet), the chip select signal XCS must be kept at “0”. If the signal XCS is set to “1” during the transfer of 1 packet, the packet being transferred is cancelled. The Then, by setting the signal XCS to “0” again, the packet retransfer acceptance state is set.

  FIG. 6D shows an example of the RGB interface signal. The RGB interface is an interface most suitable for moving image display, and image data is written to the display memory. As shown in FIG. 6D, the RGB interface uses DOTCLK as the display timing reference clock signal. Further, after detecting the falling edge of the vertical synchronizing signal VSYNCI, when the falling edge of the horizontal synchronizing signal HSYNC is detected, the frame is forcibly synchronized to the head of the frame (first line of the back porch). The number of back porch lines and the number of display lines are set by a command to the register of the display driver. In the RGB interface, the signals VSYNCI, HSYNC, ENABLE, and image data D17 to D0 are read at the falling edge of the clock signal DOTCLK. Only when the signal ENABLE is “0”, image data of one pixel (RGB) is written in the display memory.

  The interface signals that can be generated by the external interface circuit model 130 are not limited to MPU interface signals, serial interface signals, and RGB interface signals as shown in FIGS. For example, a YUV interface signal (camera interface signal) as shown in FIG. 6E may be generated.

  FIG. 6E shows a waveform example of signals CMVREF, CMHREF, and CMDAT [7: 0] when the camera data is in an 8-bit YUV format. Here, CMVREF and CMHREF correspond to a vertical synchronization signal and a horizontal synchronization signal, respectively. The camera data CMDAT [7: 0] is captured by a clock signal CMCLKIN (not shown).

  When the display driver has a YUV-RGB conversion circuit, the YUV interface signal shown in FIG. 6E is used. Then, YUV data output from the camera device is input to the display driver, converted into RGB data using the YUV-RGB conversion circuit of the display driver, and written into the display memory.

  The serial interface signal is not limited to a CMOS voltage level signal as shown in FIG. 6C, and may be a small amplitude serial signal (LVDS) using a differential signal or the like. As a result, high-speed serial transfer can be realized.

  That is, a general mobile phone includes a first device part provided with buttons for inputting a telephone number and characters, a second device part provided with an LCD (Liquid Crystal Display) and a camera device, and a first device part. , And a connecting portion such as a hinge for connecting the second device portion. Therefore, data transfer between the first circuit board provided in the first device portion and the second circuit board provided in the second device portion is performed by high-speed serial transfer using a small amplitude differential signal. By doing so, it is possible to reduce the number of wirings that pass through the connection portion, to increase the degree of design freedom, and to reduce EMI noise.

  8A and 8B show an example of a high-speed serial transfer method of the MDDI standard. Note that the high-speed serial transfer method in the present embodiment is not limited to FIGS. 8A and 8B, and various methods can be adopted according to the standard adopted.

  In FIG. 8A, the physical layer circuit 340 (transceiver) is built in the host device, and the physical layer circuit 330 is built in the display driver. Reference numerals 336, 342, and 344 denote transmitter circuits, and reference numerals 332, 334, and 346 denote receiver circuits. Reference numerals 338 and 348 denote wake-up detection circuits. The host-side transmitter circuit 342 drives the differential strobe signal STB +/−. The client-side receiver circuit 332 amplifies the voltage generated at both ends of the resistor RT1 by driving, and outputs the strobe signal STB_C to the subsequent circuit. The host-side transmitter circuit 344 drives the data signal DATA +/−. The client-side receiver circuit 334 amplifies the voltage generated at both ends of the resistor RT2 by driving, and outputs the data signal DATA_C_HC to the subsequent circuit.

  As shown in FIG. 8B, the transmission side generates the strobe signal STB by taking the exclusive OR of the data signal DATA and the clock signal CLK, and transmits this STB to the reception side via the high-speed serial bus. To do. Then, the reception side reproduces the clock signal CLK by taking an exclusive OR of the received data signal DATA and the strobe signal STB.

  When a high-speed serial interface circuit as described in FIG. 8A is built in the display driver, the designer needs to create a test pattern as shown in FIG. 8B in order to test this. . However, since data is serialized and transferred in high-speed serial transfer, it is difficult for the designer to intuitively recognize the meaning of the data, and it is difficult to create an effective test pattern.

  In this regard, according to the present embodiment, when a designer creates and inputs a command file as shown in FIG. 5, a high-speed serial interface signal having a waveform as shown in FIG. 8B is automatically generated. As a result, the verification work of the designer can be greatly reduced.

  9A and 9B show configuration examples of the external interface circuit model 130. FIG. FIG. 9A is an example of a model that realizes generation of the MPU interface signal of FIGS. 6A and 6B and the serial interface signal of FIG. 6C. The generation of the RGB interface signal in FIG. 6D can also be realized by a similar model.

  The command processing task unit 132 performs command level task processing based on the test input information 150 (command file, image data). Specifically, command and parameter identification processing is performed. Further, the interface mode designation command (IMODE) is used to identify whether the interface is parallel transfer or serial transfer, or whether the interface is a write or a read.

  The signal generation task unit 134 receives input at the variable level from the command processing task unit 132 and performs processing at the signal level. In other words, the interface signals XCS, XRES, A0, XRD, XWR, IF1, IF2, IF3, DATA [N: 0], SCL, SD are taken into account based on the command and image data of the input command file, taking into account timing and the like. Binary data “1” and “0” are allocated to. As a result, data of MPU interface signals and serial interface signals as shown in FIGS. 6A, 6B, and 6C are generated and input to the display driver model 10.

  FIG. 7B shows the meaning of the interface selection signals IF1, IF2, and IF3. For example, when the interface mode for 16-bit parallel transfer is designated by the interface mode designation command IMODE shown at C1 in FIG. 5, the signals IF1, IF2, and IF3 are set to “0” as shown in FIG. 7B. And input to the display driver model 10. The same applies to the 18-bit parallel, 8-bit parallel, 9-bit parallel, and 9-bit serial shown in FIG.

  FIG. 9B is an example of a model that realizes the generation of the high-speed serial interface signal described with reference to FIGS.

  The command processing task unit 133 performs command level task processing based on the test input information. Specifically, processing for identifying whether the packet is a register access packet (command or command parameter transfer packet) or a video packet (image data transfer packet) is performed. In addition, a process for identifying whether it is a write or a read is performed.

  The signal generation task unit 135 receives input at the variable level from the command processing task unit 133 and performs processing at the signal level. That is, the binary data “1” and “0” are allocated to the high-speed serial interface signals DATA +, DATA−, STB +, STB−, ENABLE based on the command and image data of the input command file, taking into account the timing and the like. I do. As a result, the data of the high-speed serial interface signal described in FIGS. 8A and 8B is generated and input to the display driver model 10.

  The method of the present embodiment using the external interface circuit model 130 as described above has the following advantages. In other words, in the method of generating a test pattern using Verilog description or task description, the test pattern creation becomes unrealistic or the management of the test pattern becomes complicated as the specifications of the verification target device become complex. There was a problem.

  On the other hand, according to the method of the present embodiment using the external interface circuit model 130, various MPU types (C80 system, 68 system), transfer modes (parallel transfer, Serial transfer) and bus width (8, 9, 16, 18 bits) interface signal data is automatically generated and input to the display driver model 10. Therefore, the man-hours for creating test input information (test pattern) can be greatly reduced, and the development period can be shortened.

  Further, the designer can create various types of interface signals as shown in FIGS. 6A to 6E only by creating a command file in which commands as shown in FIG. 5 are listed. Become. In other words, the designer can automatically generate various types of interface signals simply by writing commands according to the design specifications of the display driver and creating a command file as shown in FIG. Therefore, the designer can easily create the test input information even if the designer is not familiar with the Verilog description format, thereby facilitating the creation of the test input information.

  In addition, by simply changing the command description in the command file while using the same image data, various interface signal data in different formats can be automatically generated, so the test input information creation process can be further reduced. .

4). Simulation Using Internal Register FIG. 10 shows a detailed configuration example of the data driver 550 and the gradation voltage generation circuit 610. The data driver 550 includes a driver cell 552 provided for each data line (SS1, SS2,...). The driver cell 552 includes a data latch & conversion circuit 554, a control circuit 556, a D / A conversion circuit 558, an operational amplifier unit 560, and an output circuit 562.

  The data latch & conversion circuit 554 latches the gradation data GD1 [5: 0] from the display memory 520. The data latch & conversion circuit 554 performs RGB inversion processing. That is, processing for changing the arrangement of RGB data from the arrangement in the order of R, G, B to the order of B, G, R is performed. Thereby, it becomes possible to cope with various types of display panels having different mounting forms.

  The control circuit 556 generates various control signals for the D / A conversion circuit 558, the operational amplifier unit 560, and the output circuit 562, and performs data conversion processing on the gradation data. Specifically, power saving processing is performed using the control signals to the D / A conversion circuit 558, the operational amplifier unit 560, and the output circuit 562, and polarity inversion processing and color reduction mode processing are performed on gradation data. For example, in the polarity inversion process, gradation data of “63”, “62”, “61” is set to “0”, “1”, “2”, for example, in the negative polarity period. In the color reduction mode, a process of switching the number of display colors expressed by the gradation data to, for example, 8 colors is performed.

  The D / A conversion circuit 558 is a circuit that D / A converts digital gradation data into an analog data voltage. Specifically, D / A conversion is realized by selecting a voltage corresponding to digital gradation data from the gradation voltages from the gradation voltage generation circuit 610.

  The operational amplifier unit 560 performs an impedance conversion process on the data signal (data voltage). The operational amplifier unit 560 includes, for example, an operational amplifier OP (operational amplifier) and a switching element SW. For example, when the switching element SW is turned on, DAC driving in which the data line SS1 is directly driven by the D / A conversion circuit 558 is performed. Thereby, DAC driving and operational amplifier + DAC driving are realized.

  The output circuit 562 performs voltage setting for the data line SS1. For example, when the display panel display off command is input, if the voltage of the data line SS1 is set using the D / A conversion circuit 558 or the operational amplifier unit 560, it takes time to charge and discharge the charge. It takes a long time for the voltage to be set to a low level or a high level. In such a case, the output circuit 562 directly sets the voltage of the data line SS1 to a low level or a high level. In this way, when the display off command for the display panel is input, the display panel can be immediately displayed in white (in the case of normally white liquid crystal) or the like.

  The gradation voltage generation circuit 610 (γ correction circuit) includes a voltage dividing circuit 612 (selection voltage generation circuit) and a gradation voltage selection circuit 614. The voltage dividing circuit 612 outputs divided voltages VS0 to VS255 (selection voltages) based on the high-voltage power supply voltages VDDH and VSSH generated by the power supply circuit 590 (see FIG. 1). Specifically, the voltage circuit 612 includes a ladder resistor circuit having a plurality of resistor elements connected in series. A voltage obtained by dividing VDDH and VSSH by the ladder resistor circuit is output as divided voltages VS0 to VS255. The gradation voltage selection circuit 614 is based on the gradation characteristic adjustment data set in the adjustment register 616 by the logic circuit 540 (see FIG. 1), for example, in the case of 64 gradations from among the divided voltages VS0 to VS255. Selects 64 voltages and outputs them as gradation voltages V0 to V63. In this way, it is possible to generate a gradation voltage having an optimum gradation characteristic (γ correction characteristic) according to the display panel.

  Now, the data driver 550 and the gradation voltage generation circuit 610 in FIG. 10 include analog circuits. The gradation voltage generated by the gradation voltage generation circuit 610 and the data voltage output to the data line SS1 are analog values and cannot be expressed by digital logic simulation.

  Therefore, in this embodiment, the data driver 550 and the gradation voltage generation circuit 610 are modeled by a Verilog behavior model or the like, and simulation processing is performed.

  Specifically, as shown in FIG. 11, data (binary data) of 6 bits (N bits in a broad sense, N> 2) for each data line is transferred from the data driver model 20 to the display panel model 90. Perform the input simulation process. That is, data of a 6-bit data signal is input to the display panel model 90 for each data line without going through the data line at the actual circuit level. In this way, it becomes possible to verify the display driver using a digital logic simulation such as Verilog, and it is possible to verify the operation close to the actual operation of the display driver.

  More specifically, a virtual internal register 22 is provided in the data driver model 20 as shown in FIG. The internal register 22 is a 6-bit (N-bit) register provided for each data line.

  Then, 6-bit (N-bit) gradation data from the display memory model 40 is stored in each internal register 22 provided for each data line, and the stored 6-bit gradation data is used as data signal data. Then, a simulation process for inputting to the display panel model 90 is performed. Specifically, the display panel model 90 refers to the data in the internal register 22 of the data driver model 20 and transfers 6-bit parallel data from the data driver model 20 to the display panel model 90 for each data line. Such data transfer by reference can be easily realized using Verilog description.

  In FIG. 11, the display panel model 90 includes a data capture unit 92, a polarity inversion unit 94, and an image data file creation unit 96.

  Here, the data capture unit 92 has internal registers for all pixels of the display panel (internal registers corresponding to all pixels). When the data of the scanning signal GS1 from the display driver model 10 changes from “1” to “0”, among the internal registers for all the pixels provided in the data capture unit 92, the internal register corresponding to GS1 is selected. The data (parallel gradation data) from the internal register 22 of the data driver model 20 is stored and captured. Similarly, when the data of the scanning signal GS2 from the display driver model 10 changes from “1” to “0”, among the internal registers for all the pixels provided in the data capture unit 92, the internal register corresponding to GS2 is stored. On the other hand, the data from the internal register 22 of the data driver model 20 is stored and captured.

  The polarity inversion unit 94 performs polarity inversion processing on the data stored in the internal register of the data capture unit 92 based on the signal FR (polarity inversion signal) from the display driver model 10. That is, the polarity of the signal FR is determined, and normal rotation / inversion processing of data (image data) is performed. Then, the image data file creation unit 96 generates and outputs an image data file 160 using the signal VSYNC (vertical synchronization signal) from the display driver model 10 as a trigger.

  FIG. 12 shows a flowchart of the simulation process of FIG. First, the display memory model 40 outputs gradation data (step S1). Then, the gradation data is stored in the internal register 22 of the data driver model 20 using a control signal for the D / A conversion circuit and the operational amplifier as a trigger (step S2).

  Next, conversion processing such as RGB inversion processing, polarity inversion processing, and color reduction mode processing is performed on the gradation data stored in the internal register 22 (step S3). That is, RGB inversion processing (processing for converting RGB to BGR) performed by the data latch & conversion circuit 554 in FIG. 10, polarity inversion processing, and color reduction mode (8-color mode) processing performed by the control circuit 556 are executed. The converted gradation data is stored in the internal register 22 without being output to the data line output terminal (step S4). Then, the gradation data is passed to the display panel model 90 via the internal register 22.

  11 and 12, the analog operation of the data driver can be simulated in a pseudo manner simply by providing the virtual internal register 22. Therefore, the system simulation with the mounting image as shown in FIG. 4 can be realized by using digital logic simulation such as Verilog. Therefore, it becomes possible to verify an analog control operation or the like by digital logic simulation while using a simple model, and the verification efficiency can be improved.

5). Simulation Using Socket Model The methods shown in FIGS. 11 and 12 have an advantage that a simple model using the internal register 22 can be used as the data driver model 20. However, since the net list of the actual circuit of the data driver is not used, there is a disadvantage that the verification accuracy is inferior. In other words, since the behavior model itself is a pseudo model, the designer may misunderstand the operation specifications of the display driver or create an incorrect operation model. There are advantages.

  On the other hand, a method of creating an operation model of an analog block such as a data driver using the analog description language AHDL is also conceivable. In this method, the analog block behaves like an analog, so there is no problem with the creation of the analog operation. However, as long as it is a model, the problem of misidentification of specifications remains. Also, when a system simulation as shown in FIG. 4 is to be realized, the verification simulation must be switched from a digital logic simulation to a mixed signal simulation. The mixed signal simulation is not suitable for verifying all functions of the display driver because the simulation time is enormous.

  Therefore, in the method described with reference to FIG. 13, an analog block is configured by a netlist for digital logic simulation, and gradation voltages that should be handled as analog values are handled as serial data. Is realized by digital logic simulation.

  Specifically, instead of modeling the entire analog block such as a data driver, a method (partial modeling) of modeling only the minimum necessary analog circuit is employed. Even though it is an analog block, the internal control circuit etc. is composed of logic circuits, so that part uses a Verilog netlist output from the schematic, and a pseudo operation model only for the minimum necessary analog circuit Create By doing so, the unit of the analog model becomes smaller, so the probability of misrecognizing the specification and describing the model behavior is reduced, and the verification accuracy can be improved.

  For example, in the data driver 550 shown in FIG. 10, only the operational amplifier OP of the operational amplifier unit 560 is described by a Verilog behavior model, and a simulation is performed. Other circuits (data latch & conversion circuit, control circuit, D / A conversion circuit, output) For the circuit, etc., the simulation is executed using the Verilog netlist and Verilog library output from the schematic. According to this method, the control circuit inside the data driver 550 reliably performs the operation intended by the designer, so that the abnormal operation caused by the model hardly occurs and the verification accuracy can be improved.

  Further, as described above, the gradation voltage from the gradation voltage generation circuit 610 cannot be expressed by Verilog digital logic simulation. Therefore, a model called a socket model 110 is introduced to enable output from the data driver model 20 by using a serial data format as gradation voltage data. Serial gradation voltage data is generated in the socket model 110 by the number of gradation voltages, and the serial gradation voltage data is supplied to the gradation voltage generation circuit model 60 (γ model) via the ladder resistance model. (Virtual connection). Since the gradation voltage generation circuit model 60 supplies gradation voltages to the data driver model 20, the data driver model 20 can handle serial gradation voltage data from the gradation voltage generation circuit model 60. Therefore, the serial gradation voltage data supplied from the gradation voltage generation circuit model 60 is selected in the data driver model 20 based on the gradation data, serial / parallel conversion is performed in the socket model 110, and a display panel model is selected. 90.

  Specifically, as shown in FIG. 13, a socket model 110 that is virtually provided between the display driver model 10 and the display panel model 90 is prepared. The socket model 110 (virtual connection model) is a model for virtually connecting the display driver model 10 and the display panel model 90.

  The serial gradation voltage data generated by the socket model 110 is input to the data driver model 20 via the gradation voltage generation circuit model 60. Then, serial data from the data driver model 20 is input to the socket model 110 and converted into parallel data, and a simulation process is performed in which the parallel data obtained by the conversion is input to the display panel model 90 as data signal data. .

  For example, in FIG. 13, the socket model 110 includes a shift clock generation unit 112, a clock number count unit 114, a serial gradation voltage data generation unit 116, a serial / parallel conversion unit 118, and an internal register 120. The shift clock generator 112 generates a shift clock, and the clock number counter 114 counts the number of shift clocks. The serial grayscale data generation unit 116 operates based on the count value from the clock number counting unit 114 and generates serial grayscale voltage data. That is, binary serial gradation voltage data corresponding to each of the gradation voltages V0 to V63 is generated. For example, (000000), (000001), (0000010), (0000011), and the like are generated as serial gradation voltages corresponding to the gradation voltages V0, V1, V2, and V3, respectively. Then, each of the generated serial gradation voltage data is supplied to each of the nodes V0 to V63. This can be achieved by virtual connection using Verilog.

  The D / A conversion circuit 558 configured by the net list selects a node corresponding to the gradation data from the nodes V0 to V63 based on the gradation data from the display memory model 40. For example, in the positive polarity period, when the gradation data is “63”, the node of V63 is selected, and when the gradation data is “62”, the node of V62 is selected. On the other hand, in the negative polarity inversion period, when the gradation data is “63”, the node of V0 is selected, and when the gradation data is “62”, the node of V1 is selected. Then, the serial grayscale voltage data supplied to the selected node is output to the data line via the D / A conversion circuit 558, the operational amplifier unit 560, and the output circuit 562, and is input again to the socket model 110.

  The serial / parallel conversion circuit 118 of the socket model 110 operates based on the count value from the clock number counting unit 114, performs serial / parallel conversion of the serial gradation voltage data output to the data line, and provides 64 gradations. Restore to parallel data. The obtained parallel data is stored in the internal register 120. The parallel data stored in the internal register 120 is transferred from the socket model 110 to the display panel model 90 by a method similar to the method described with reference to FIGS. That is, when the display panel model 90 refers to the internal register 120, the parallel data in the internal register 120 is stored in the internal register provided in the data capture unit 92 of the display panel model 90.

  In FIG. 13, the serial grayscale voltage data generation unit 116 and the serial / parallel conversion unit 118 operate based on the count value from the clock number counting unit 114. In this way, the serial gradation voltage data generation unit 116 and the serial / parallel conversion unit 118 operate in synchronism, and appropriate serial / parallel conversion can be realized. In other words, the serial / parallel converter 118 can appropriately determine the delimiter of the serial data from the data driver model 20 (delimiter between the serial gradation voltage data and the next serial gradation voltage data) and perform serial / parallel conversion. It becomes like this.

  According to the method of FIG. 13, the circuit of the data driver model 20 is configured by a netlist except for some circuits such as an operational amplifier. Therefore, it is possible to effectively prevent a simulation malfunction caused by a failure of the analog operation model. Further, since the signal of the gradation voltage data can be observed as a signal passing through the data driver circuit from the gradation voltage generation circuit, the gradation voltage generation circuit and the data driver can be accurately verified at the actual circuit level.

  For example, when a display off command of the display panel is input, the output circuit 562 performs an operation of directly setting the voltage of the data line SS1 to a low level or a high level. It is difficult to verify the operation of the output circuit 562 by the method shown in FIGS.

  On the other hand, in the method of FIG. 13, serial gradation voltage data is output from the nodes V0 to V63 to the data line via the D / A conversion circuit 558, the operational amplifier unit 560, and the output circuit 562. Therefore, the operation of the output circuit 562 when the display off command is input can be accurately verified, and the verification accuracy can be improved.

  As shown in FIG. 14A, additional data may be added to the serial gradation voltage data when the serial gradation voltage data is created. That is, as serial data, additional data is prepared in addition to serial gradation voltage data, and packet data combining the serial gradation voltage data and additional data is generated in the socket model 110. Specifically, the serial gradation voltage data generation unit 116 generates packet data. The additional data in this case can include, for example, at least one of RGB identification data and polarity inversion identification data. Here, the RGB identification data is data for identifying whether the serial gradation voltage data is R, G, or B data. The polarity reversal identification data is data for identifying the positive polarity and the negative polarity of polarity reversal.

  The serial grayscale voltage data and additional data from the socket model 110 are input to the data driver model 20 via the grayscale voltage generation circuit model 60, and the socket model 110 performs a simulation process for separating the additional data. That is, the generated serial data (serial gradation voltage data and additional data) is output from the nodes V0 to V63 to the data line via the D / A conversion circuit 558, the operational amplifier unit 560, and the output circuit 562, and is connected to the socket. It is captured in the model 110. Then, packet analysis is performed in the socket model 110, and the gradation voltage data and the additional data are separated from the serial data. Based on the separated additional data, various conversion processes (RGB separation process and polarity inversion process) are performed on the gradation voltage data.

  For example, as shown in FIG. 14B, in the low-temperature polysilicon panel (hereinafter referred to as LTPS panel), R, G, B data is multiplexed into the data signal on the display driver 510 side, and the display is performed. On the panel 512 side, the multiplexed R, G, and B data are separated. Specifically, the switching elements TM1R, TM1G, and TM1B (transistors) that are controlled to be turned on and off by the switching signals SM1R, SM1G, and SM1B allow the R, G, and B data to be time-divided with respect to the data signal on the data line SS1 Multiplexed. The multiplexed R, G, and B data are separated by switching elements TD1R, TD1G, and TD1B (transistors) that are controlled to be turned on and off by switching signals SD1R, SD1G, and SD1B. Of supplied.

  In such an LTPS panel, it is possible to verify the operation of multiplexing processing and separation processing by using RGB identification data as additional data. Specifically, as shown in FIG. 14C, a serial / parallel conversion & separation unit 119 is provided in the socket model 110 instead of the serial / parallel conversion unit 118, and R and G are used instead of the internal register 120. And B internal registers 120R, 120G, and 120B are provided. Then, the serial / parallel conversion & separation unit 119 separates the additional data from the serial data. When the RGB identification data of the additional data indicates R data, the gradation voltage data paired with the additional data is stored in the R internal register 120R. Similarly, when the RGB identification data of the additional data indicates G data and B data, the gradation voltage data paired with the additional data is stored in the G and B internal registers 120G and 120B.

  The display panel model 90 (data capture unit) is also provided with internal registers 93R, 93G, and 93B for R, G, and B. The gradation voltage data (parallel data) stored in the internal registers 120R, 120G, and 120B of the socket model 110 are transferred to and stored in the internal registers 93R, 93G, and 93B of the display panel model 90, respectively. In this case, which of the internal registers 93R, 93G, and 93B stores the gradation voltage data can be realized by using the switching signals SD1R, SD1G, and SD1B in FIG. Note that the polarity reversal identification data, which is additional data, can be used effectively when the display panel model 90 does not have the polarity reversing unit 94 as shown in FIG. That is, in this case, the polarity inversion processing of the gradation voltage data paired with the additional data may be performed based on the polarity inversion identification data included in the additional data.

6). Display Panel Model In the display panel model 90 of the present embodiment, processing for converting data input from the display driver model 10 into display image data is performed. For example, as shown in FIG. 15, the display panel model 90 receives data of data signals SS1, SS2, SS3... And data of scanning signals GS1, GS2,. Based on these data, image data at each pixel (pixel specified by the data signal and the scanning signal) of the display panel is obtained, and an image data file 160 including the image data at each obtained pixel is created. . That is, an image dump file of a display panel image is created as shown in FIG.

  More specifically, as shown in A1 and A2 of FIG. 15, the internal register of the display panel model 90 uses the falling edge of the scanning signal from the scanning driver model 30 as a trigger and the image data R [ 5: 0], G [5: 0], and B [5: 0] are fetched from the display driver model 10. Next, the polarity (positive polarity, negative polarity) of the common signal (signal FR) is determined, and normal rotation / inversion processing of the image data captured in the internal register is performed. Next, an image data file 160 is created and output using a vertical synchronization signal (signal VSYNC) as a trigger.

  FIG. 16 shows an example of the image data file 160. Note that the image data file 160 of the present embodiment is not limited to the format shown in FIG. 16, and various modifications can be made.

  The image data file 160 in FIG. 16 is a file having the simplest image format in ASCII format called PPM (Portable Pix Map). Specifically, the image data file 160 includes a format identifier (P1: binary ASCII, P2: grayscale ASCII, P3: full color ASCII), image size (horizontal, vertical), number of gradations (maximum tone value), image data. (RGB image data represented by decimal gradation values). After the simulation is completed, the created image data file 160 is displayed on the screen of the display device of the workstation using UNIX utility software or the like, and the operation of the display driver is verified. In this way, the simulation result can be visually captured instantaneously in the form of a display image. In addition, since it is not necessary to visually check all the complicated control signals on the waveform display, the design efficiency can be improved. Also, bugs that are difficult to find even for designers who are familiar with the specifications can be found. In addition, even designers who do not understand detailed operation specifications can participate in verification work, and work can be divided.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, a term (display driver, 6-bit, etc.) described together with a different term (verified device, N-bit, etc.) in a broader sense or the same meaning at least once in the specification or drawing is used anywhere in the specification or drawing. Can also be replaced by their different terms.

  Further, the configuration of the verification simulator and the verification simulation method are not limited to those described in the present embodiment. For example, a method that does not output simulation result data as an image data file or a method that does not use an internal register or a socket model may be employed. The simulation method is not limited to a digital logic simulation method such as Verilog.

The structural example of the display driver which is a verification object device. FIG. 2A is an explanatory diagram of a conventional verification simulation method, and FIGS. 2B and 2C are explanatory diagrams of the verification simulation method of the present embodiment. The structural example of the verification simulator of this embodiment. The simulation environment of the verification simulator of this embodiment. Example command file. 6A to 6E show examples of various types of interface signals. 7A and 7B are explanatory diagrams of interface signals. 8A and 8B are explanatory diagrams of high-speed serial transfer. 9A and 9B are configuration examples of the external interface circuit model. 3 is a detailed circuit configuration example of a display driver. Explanatory drawing of the simulation method using an internal register. The flowchart of the simulation method using an internal register. Explanatory drawing of the simulation method using a socket model. 14A, 14B, and 14C are explanatory diagrams of a method using additional data. Explanatory drawing of the production | generation method of an image data file. An example of an image data file.

Explanation of symbols

10 display driver model, 20 data driver model, 22 internal registers,
30 scan driver model, 40 display memory model, 50 power supply circuit model,
60 gradation voltage generation circuit model, 70 logic circuit model,
80 internal interface circuit model, 90 display panel model,
92 data capture unit, 93R, 93G, 93B internal registers,
94 polarity inversion unit, 96 image data file creation unit, 110 socket model,
112 shift clock generation unit, 114 clock number counting unit,
116 serial gradation voltage data generation unit, 118 serial / parallel conversion unit,
119 Serial / parallel conversion & separation unit,
120, 120R, 120G, 120B internal registers,
130 external interface circuit model, 132, 133 command processing task part,
134, 135 Signal generation task section, 150 test input information,
152 command file, 154 image data, 160 image data file,

Claims (8)

A storage unit for storing information of a model in which the operation of the device is described;
A simulation processing unit that performs a simulation process of the verification target device based on the model and the test input information,
The model is
A verification target device model in which an operation of the verification target device is described; and an external interface circuit model in which an operation of an external interface circuit included in an external device of the verification target device is described.
The verification target device model is:
An internal interface circuit model in which an operation of an internal interface circuit that performs interface processing with the external device using an interface signal is described;
The test input information is:
A command file in which at least a command for operating the verification target device is described;
The external interface circuit model is:
A signal generation task unit for allocating binary data to the interface signal based on a command of the command file;
The simulation processing unit
Inputting the command file to the external interface circuit model, the data of the interface signal in the predetermined format generated by the external interface circuit model based on the command file, the simulation processing to be input to the internal interface circuit model A verification simulator characterized by performing. In claim 1,
The interface signal includes at least one of an MPU interface signal, an RGB interface signal, a serial interface signal, and a YUV interface signal,
The simulation processing unit
A simulation process for inputting data of at least one of the MPU interface signal, the RGB interface signal, the serial interface signal, and the YUV interface signal generated by the external interface circuit model to the verification target device model is performed. A verification simulator characterized by that. In claim 1 or 2,
The command file includes an interface mode designation command,
The simulation processing unit
A verification simulator for performing a simulation process for inputting interface signal data in a format specified by the interface mode specifying command to the verification target device model. In any one of Claims 1 thru | or 3,
The command file includes an operation mode designation command of a display driver that is a verification target device,
The simulation processing unit
A verification simulator for performing simulation processing for inputting data of an interface signal for setting the verification target device to an operation mode specified by the operation mode specification command to the verification target device model. In any of claims 1 to 4 ,
The model is
A display driver model in which an operation of a display driver that is the verification target device is described; and a display panel model in which an operation of a display panel driven by the display driver is described;
The simulation processing unit
A verification simulator, wherein simulation processing is performed based on the test input information, the external interface circuit model, the display driver model, and the display panel model. In claim 5 ,
The display driver model is
Including a logic circuit model that describes the operation of the logic circuit that generates the display control signal;
The simulation processing unit
A verification simulator using a net list of the logic circuit as the logic circuit model. In claim 5 or 6 ,
The display driver model is
A data driver model that describes the operation of the data driver that outputs the data signal ;
Including a display memory model describing the operation of a display memory for storing gradation data as image data ;
The simulation processing unit
N-bit gradation data from the display memory model is stored in each internal register of the data driver model provided for each data line, and the N-bit gradation data stored in each internal register is stored as data. A verification simulator characterized by performing a simulation process for inputting signal data to the display panel model. A verification simulation method for a verification simulator , comprising:
The verification simulator is
A storage unit for storing information of a model in which the operation of the device is described;
A simulation processing unit that performs a simulation process of the verification target device based on the model and the test input information,
The model is
A verification target device model in which an operation of the verification target device is described; and an external interface circuit model in which an operation of an external interface circuit included in an external device of the verification target device is described.
The verification target device model is:
An internal interface circuit model in which an operation of an internal interface circuit that performs interface processing with the external device using an interface signal is described;
The test input information is:
A command file in which at least a command for operating the verification target device is described;
The external interface circuit model is:
A signal generation task unit for allocating binary data to the interface signal based on a command of the command file;
The simulation processing unit
The command file is input to the external interface circuit model, and a simulation process is performed to input interface signal data of a given format generated by the external interface circuit model based on the command file to the internal interface circuit model. A verification simulation method characterized by that.

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