JP2000181940A - Analog/digital hybrid logic simulation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently and easily perform the logic simulation of an LSI where a digital part and an analog part coexist. SOLUTION: The operation of respective analog cells to be the constituting elements of an analog circuit is described by a function description language understandable by a logic simulator first. Then, in the input part and output part of the analog cells, register variables for holding an analog signal value are made to correspond to an input terminal and an output terminal. In a connection part between the analog cells, transmission control is performed not by the signal transmission of the input terminal and the output terminal but by the transmission of the signal value between the register variables through an analog value transmission part 24. Thus, this analog/digital coexistent logic simulation method for performing the logic simulation including the analog cells is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a logic verification method in LSI design.

[0002]

2. Description of the Related Art LSI (Large Scale In)
Logic As a means of confirming the operation of the final step of development, logic simulation is widely used. By the way, digital (circuit) part and analog (circuit)
In the case of an LSI in which the analog part is mounted, the analog part cannot be checked by logic simulation. for that reason,
Conventionally, there is only a method of creating some behavioral description and substituting it, and as a result, in the logic simulation, the operational relationship with the analog unit could not always be sufficiently confirmed. Therefore, it is not uncommon for a simple design error to occur at the connection between the analog unit and the digital unit.

As measures against the above problems, the following two are practically used in the prior art. A function model of the analog section that can be understood by the logic simulator is created for each development type LSI in accordance with operation-related check items between the analog section and the digital section. The operation of the analog part is expressed by a circuit simulator,
Then, the logic simulator and the circuit simulator are operated in synchronization with each other to enable mixed simulation.

FIG. 1 is a conceptual diagram of the analog function model. This functional model first reads analog input data 2 as illustrated in FIG. 2 and generates an event for each occurrence time of each value of the input data.
Performs an operation to simulate the analog circuit with
The (analog-to-digital) converter 6 converts the analog signal into a digital signal and transmits it to an output terminal. In this method, since a functional model is created for each product type from the stage of studying the specification of the model, it is difficult to say that the development efficiency is high. In addition, in consideration of development efficiency, a (general-purpose) analog cell which is a component of the analog circuit section is defined, a function description model of the analog cell is prepared in advance, and the connection is made according to the circuit diagram. Although a method was examined, transmission of an analog signal between analog cells cannot be realized by this function description model, and eventually does not reach realization.

[0005] In the case where the scale of the analog section is relatively large, the total execution time of the simulation is controlled by the circuit simulator, and a considerable execution time is required.

Japanese Patent Application Laid-Open No. 9-269885 actually measures the operation of an analog cell which is a unit constituting an analog circuit, and performs a simulation by regarding the analog cell as a digital cell based on its input / output data. It is characterized by: Although it is an effective method because it does not require time in the simulation of the analog section, it cannot cope with data propagation from the digital section to the analog section.

[0007]

As described above, it is not possible to efficiently perform a logic simulation of an LSI in which a digital section and an analog section are mounted together. In the present invention, in advance, a function description model of an analog cell that can propagate analog signals and a logic simulator of a digital circuit,
CAD (Computer-
Achieve efficient and easy mixed digital / analog logic simulation by preparing it in an Aided Design system library and using it in any combination during logic simulation for LSI operation confirmation. It is an object.

[0008]

In a logic simulation of an LSI in which an analog circuit and a digital circuit coexist, first, the operation of each analog cell which is a component of the analog circuit is described in a function description language that can be understood by a logic simulator. Next, in the input unit and the output unit of the analog cell, a register variable holding an analog signal value is associated with the input terminal and the output terminal, and at the connection between the analog cells, the input terminal and the output terminal are connected. Transmission control is performed not by signal transmission but by transmission of signal values between the register variables through an analog value transmission unit. As described above, an analog / digital mixed logic simulation method for performing a logic simulation including an analog cell is realized.

In the mixed analog / digital logic simulation method, when reading an external analog signal, the first analog cell holds the analog signal value in the register variable of the input unit through the analog value transmitting unit. In particular, it allows the analog cells to accept external analog signals.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the method of the present invention will be described with reference to the accompanying drawings.

FIG. 4 shows a conceptual diagram of the analog function model of the present invention. In the conventional analog function model, the entire analog circuit section is represented by a single function model, which is used in logic simulation. However, in the function model of the present invention, the analog circuit section is a function description model of an analog cell as a general-purpose component. And an analog signal can be propagated between the analog cell function description models.

[0012] The function model of the present invention comprises one or more digital function description models, one or more analog function description models, and an analog value transmission unit. The digital function description model forms part of a prior art logic simulator. The analog function description model is a model of an analog cell which is a component of the analog circuit unit. In the modeling, V
It is expressed using a hardware description language such as erilog. Each of the digital function description model and the analog function description model has a digital data output terminal, a digital data input terminal, and an operation condition control terminal. In the functional model of the present invention, these output terminals and input terminals are appropriately connected to form an overall model. As will be described later, the connection between the output terminal and the input terminal not only transmits digital data between the function description models, but also defines the correspondence between register variables for transferring analog signals between the analog function description models. Is also determined. Both the digital function description model and the analog function description model are CA
Registered in the D system library. The analog value transmission unit reads analog / digital attributes of both models when transmitting data from one function description model to another function description model, and if both models have analog attributes, Performs dedicated processing for data transmission between analog function description models.

In FIG. 4, two analog function description models 20, 22 are shown. The analog function description model includes a register variable for holding input analog data (hereinafter, referred to as an input register variable) and a register variable for holding output analog data (hereinafter, referred to as an output register variable). These are not provided in the digital function description model. In particular, each output register variable has a threshold (threshold) condition used in analog / digital conversion described later, and converts an analog value into a digital value according to the condition as necessary, as described later.

The operation of the analog function description model and the analog value transmitting unit will be described with reference to FIG. When an analog value is set in the input register variable 8 in the first analog function description model 20, an operation is performed on the analog value in the operation unit 10. The operation result in the operation unit 10 is an analog value, and the analog value is stored in the output register variable 12. When the analog value is stored in the output register variable 12, the analog value transmitting unit 24 determines the analog / digital attributes of both the first analog function description model 20 and the second analog function description model 22. Is an analog attribute, the analog value stored in the output register variable 12 in the first analog function description model 20 is set to the input register variable 14 in the second analog function description model 22.

The output terminal AOUT01 of the first analog function description model 20 and the second analog function description model 22
Is connected on the model to the input terminal BIN01 of
Output terminal AOUT of first analog function description model 20
When a digital value is stored in 01, the same value is automatically stored in the second
Input terminal B of analog function description model 22
IN01 is set, that is, transmitted. On the other hand, between the output register variable and the output terminal in the analog function description model of the present invention, and between the input terminal and the input register variable inside the analog function description model are not connected on the model. Therefore, even if an analog value is stored in the output register variable 12 of the first analog function description model 20, the same value is automatically set in the input register variable 14 of the second analog function description model 22. Absent. However, each analog function description model may have a first rule for associating an output register variable with an output terminal and an input terminal with an input register variable. In that case, the analog value transmitting unit 24
Determines the first rule and, in addition, determines the above-described connection relationship between the output terminal of the first analog function description model and the input terminal of the second analog function description model, so that the output register variable 12 And the input register variable 14 are determined. Then, the analog value is transmitted as described above without passing between the output terminal and the input terminal (for example, between AOUT01 and BIN01).

FIGS. 5 and 6 are conceptual diagrams of the leading end and the trailing end of the analog function model connection of the present invention.

FIG. 5 shows a configuration for reading the analog input data 26. The analog value transmitting section 24 converts analog signal information as shown in FIG.
, And determines the analog / digital attribute of the function description model 28, and then determines the corresponding input register variable 30
Set the signal value to. The condition of which input register variable 30 corresponds is provided in the analog function description model 28.

FIG. 6 shows an operation configuration of a connection portion from the analog function description model to the digital function description model. When connected to the function description model having no analog attribute, the analog value transmitting unit 24 outputs the digital function description model 3
8 is determined to be connected. An analog value is converted into a digital value according to the threshold condition provided for each output register variable, and the digital value is set to a corresponding output terminal. Here, the second rule for associating the output register variable with the output terminal is provided in each analog function description model as in the first rule, but may be different from the first rule.

The simulation operation of the simple circuit of FIG. 3 will be specifically described below with reference to the flowchart of FIG. The circuit of FIG. 3 selectively takes in two analog input data, amplifies it, and converts it into 10-bit digital data. IN1 is a first converted analog input signal, and IN2 is a second converted analog input signal. ck1 is a switch circuit that transmits the first non-converted analog input signal to the next amplifier under control of the signal of the operation condition control terminal CLK1, and ck2 is a signal of the CLK2 that is the operation condition control terminal. Under the control of the second
Is a switch circuit section for transmitting the non-converted analog input signal to the next amplification section. The amplifier circuit amp1 is a circuit that amplifies the analog signal input to the resistor r by (R / r) times and outputs the amplified analog signal after a certain delay time (here, 1 μs).
An A / D (analog / digital) converter adc1 converts the analog signal input from the amplifier circuit amp1 into a 10-bit digital signal according to a predetermined operation rule, and outputs it after a fixed A / D conversion time (here, 10 μs). Circuit. Each of the above analog cells (ck1, ck
2, amp1 and adc1) are shown in FIG.

FIG. 9 shows an example of input analog data. When the simulation is started, the analog value transmitting unit 24,
The analog cells ck1 and ck2 read the input analog data and perform scheduling. That is, the signal to ck1 shown in FIG. 9 is set to the input register variable 42 of the analog cell ck1 (see FIG. 7A) for each schedule time, and the signal to ck2 shown in FIG. A variable 42 (see FIG. 7A) is set for each schedule time (FIG. 8A). Analog cell ck
When an analog value is set in the input register variable 42 (, 42) of 1, ck2, the operation unit 52 of the analog cells ck1, ck2 performs an operation according to the function description specification FIG. 7A (FIG. 8 (2)). ). The clock signals of the operation condition control terminals CLK1 and CLK2 of the analog cells ck1 and ck2 are shown in FIG.
Is shown in According to the figure, CL is applied for the first 10 μs.
K1 is on (high state), CLK2 is off (low state), CLK1 is off (low state), CLK2 is on (high state) during the next 10 μs, and so on.
The states of CLK1 and CLK2 are switched every 0 μs. Therefore, the function description of the analog function description model ck1 is executed until the first 10 μs. The analog value of the input register variable 42 is stored.

When the set value of the output register variable 44 of the analog function description model ck1 changes, (3) in FIG.
The processes of (4) and (5) are performed. Here, ck1 and amp
8 (3), the analog value transmitting unit 24 determines that 1 is a function description model having an analog attribute, and the process of FIG. 8 (5) is executed. In two analog function description models ck1 and amp1,
The output terminal AOUT and the input terminal AI are connected.
Further, the analog function description model ck1 has a rule for associating the output register variable of the analog function description model ck1 with the output terminal of the analog function description model ck1, and the input terminal of the analog function description model amp1 and the input of the analog function description model amp1. The analog function description model amp1 has rules for associating register variables. For these reasons, the analog value transmitting unit 24 sets the output register variable 44 of the analog function description model ck1 and the input register variable 46 of the analog function description model amp1.
Is determined and the analog signal value is transferred.

When an analog value is set in the input register variable 46 of the analog function description model amp1, the calculation unit 54 of the analog function description model amp1 performs a calculation according to the function description specification FIG. )). According to the function description specification FIG. 7B, the value of the input register variable 46 of the analog function description model
Thereafter, the value is doubled and stored in the output register variable 48.

When the set value of the output register variable 48 of the analog function description model amp1 changes, (3) in FIG.
The processes of (4) and (5) are performed. Here, amp1 and ad
The analog value transmitting unit 24 determines that c1 is a function description model having an analog attribute in the determination of FIG. 8 (3), and the processing of FIG. 8 (5) is executed. In the two analog function description models amp1 and adc1, the output terminal AO and the input terminal ADIN are connected. Further, a rule for associating the output register variable of the analog function description model amp1 with the output terminal of the analog function description model amp1 is defined in the analog function description model amp1.
And a rule for associating the input terminal of the analog function description model adc1 with the input register variable of the analog function description model adc1 is provided.
1 is provided. From these, the analog value transmission unit 2
Reference numeral 4 determines the correspondence between the output register variable 48 of the analog function description model amp1 and the input register variable 50 of the analog function description model adc1, and transfers the analog signal value.

When an analog value is set in the input register variable 50 of the analog function description model adc1, the operation unit 56 of the analog function description model adc1 performs an operation according to the function description specification FIG. )). According to this function description specification FIG. 7 (c), the value of the input register variable 50 of the analog function description model
After m, the value is subjected to a predetermined operation, converted to a 10-bit digital value, and set to the terminals D0, D1, D2... D9 one bit at a time.

FIG. 10 below shows a specific simulation example of the above simple circuit from 0 second to 22000.
Nanoseconds (10 ^{- 9} seconds, ns) to the respective register variables, a transition of the voltage value at the terminals.

In the above-described embodiment, the analog value transmitting unit is, for example, a PLI (Pro
Grammable Language Interf
ace).

In the above embodiment, the connection from the analog function description model to the analog function description model and the connection from the analog function description model to the digital function description model have been mainly described. A connection from the digital function description model to the analog function description model can also be set. When the connection is made from the function description model having no analog attribute, the analog value transmitting unit 24 determines that the connection is made from the digital function description model 38. The digital value is converted into an analog value according to the condition of each input register variable, and the analog value is set in the corresponding input register variable. Here, the third rule for associating an input terminal with an input register variable is provided in each analog function description model as in the first and second rules, but is different from the first and second rules. May be.

[0028]

As apparent from the above description, the following effects can be obtained according to the logic simulation method of the present invention.

L where analog circuits and digital circuits coexist
In the logic simulation of the SI, first, the operation of each analog cell that is a component of the analog circuit is described in a function description language that can be understood by a logic simulator. next,
In the input unit and the output unit of the analog cell, the input terminal and the output terminal are associated with a register variable that holds an analog signal value.
The transmission control is performed not by the signal transmission between the input terminal and the output terminal but by the transmission of the signal value between the register variables through the analog value transmission unit. As described above, an analog / digital mixed logic simulation method for performing a logic simulation including an analog cell can be efficiently and easily realized.

In the above analog / digital mixed logic simulation method, when reading an analog signal from the outside, the analog signal value is converted into the register variable of the input unit through the analog value transmitting unit in the first analog cell. Hold. This makes it possible in particular for the analog cells to accept external analog signals. Therefore, the above-described analog / digital mixed logic simulation method can input an external analog signal.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram of a conventional analog function model.

FIG. 2 is an example of analog input data that can be input to the analog function model of FIG. 1;

FIG. 3 is a block diagram of an example of a simple circuit in which an analog circuit and a digital circuit are mixed.

FIG. 4 is a conceptual diagram of an analog function model according to the present invention.

FIG. 5 is a conceptual diagram of the tip of the analog function model connection of the present invention.

FIG. 6 is a conceptual diagram of the termination of the analog function model connection of the present invention.

FIG. 7 is a conceptual diagram of a function description specification of individual analog cells constituting the circuit of FIG. 3;

FIG. 8 is a flowchart of the operation of the analog function description model of the present invention shown in FIGS. 4, 5 and 6;

FIG. 9 is an example of analog input data that can be input to the simple circuit of FIG. 3;

10 shows a part of the transition of the voltage value at each register variable and terminal when the data of FIG. 9 is input in the simulation of the circuit of FIG. 3 using the present invention.

[Explanation of symbols]

BIN01, AI, ADIN ... input terminal, AOUT
01, AOUT, AO ... output terminals, IN1, IN2
... Analog input signals to be converted, ck1, ck2 ...
Switch circuit analog cell, amp1 ... Amplifier circuit analog cell, adc1 ... A / D (analog / digital) converter analog cell, CLK1, CLK2
..Operation condition control terminals, D0, D1, D2, D3, and D
4, D5, D6, D7, D8, D9 ... terminals, 2, 2
6 ... analog input data, 4, 10, 16, 52,
54, 56... Arithmetic unit, 6... AD (analog-digital) conversion unit, 8, 14, 30, 42, 46, 50,.
· Input register variables, 12, 18, 44, 48 ··· Output register variables, 20, 22, 28 ··· Analog function description model, 24 ··· Analog value transmission unit, 38 ···
Digital function model

Claims (2)

[Claims] In a logic simulation of an LSI in which an analog circuit and a digital circuit coexist, the operation of each analog cell that is a component of the analog circuit is described in a function description language that can be understood by a logic simulator. And in the output unit, the input terminal and the output terminal are associated with a register variable holding an analog signal value. In a connection portion between the analog cells, the signal is not transmitted between the input terminal and the output terminal, but through the analog value transmission unit. An analog / digital mixed logic simulation method for performing a logic simulation including an analog cell by controlling transmission by transmitting a signal value between the register variables. 2. The mixed analog / digital logic according to claim 1, wherein, when reading an external analog signal, the analog signal value is held in a register variable of an input unit through said analog value transmitting unit in a first analog cell. Simulation method.