JP2007058586A - Verification simulator and verification simulation method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a verification simulator and a verification simulation method with high simulation accuracy. <P>SOLUTION: The verification simulator includes a storing part which stores information of a model in which operation of a device is described, and a simulation processing part which performs simulation processing of a verifying object device based on the model and test input information. The model includes a display driver model 10, a display panel model 90, and a socket model 110. The display driver model 10 includes a gradation voltage generating circuit model 60 and a data driver model 20. The simulation processing part inputs the serial gradation voltage data generated by the socket model 110 to the data driver model 20 through the gradation voltage generating circuit model 60, inputs serial data from the data driver model 20 to the socket model 110 and converts it to parallel data, and inputs parallel data obtained by the conversion to the display panel model 90. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a verification simulator and a verification simulation method.

  A display driver (LCD driver) is a device for driving a display panel such as a liquid crystal panel. This display driver requires a verification simulation for confirming the operation before actually manufacturing the display driver.

  As a display driver verification simulation method, there is a method of verifying each block individually, such as verifying an analog block of a display driver by an analog simulator and verifying a digital block by a digital simulator.

However, in such single verification of analog blocks and digital blocks, the operation verification of the entire display driver chip cannot be performed, and there is a risk that problems such as control between blocks may occur.
Japanese Patent Laid-Open No. 11-25140

  The present invention has been made in view of the above technical problems, and an object of the present invention is to provide a verification simulator and a verification simulation method with high verification accuracy.

  The verification simulator according to the present invention includes a storage unit that stores information of a model in which the operation of the device is described, and a simulation processing unit that performs a simulation process of the verification target device based on the model and the test input information, The model includes a display driver model in which an operation of a display driver is described, a display panel model in which an operation of a display panel driven by the display driver is described, and the display driver model and the display panel model. The display driver model includes a gradation voltage generation circuit model in which an operation of a gradation voltage generation circuit for generating a gradation voltage is described, and the generated gradation voltage. A data driver model describing the operation of a data driver that outputs a data signal based on the The serial processing unit inputs serial grayscale voltage data generated by the socket model to the data driver model via the grayscale voltage generation circuit model, and converts serial data from the data driver model to the socket model. The present invention relates to a verification simulator that performs a simulation process of inputting and converting into parallel data and inputting the parallel data obtained by the conversion into the display panel model as data signal data.

  According to the present invention, the socket model is provided between the display driver model and the display panel model. The serial gradation voltage data generated by the socket model is input to the data driver model via the gradation voltage generation circuit model, and is input from the data driver model to the socket model. Then, it is converted into parallel data in the socket model and input to the display panel model. By doing so, it is possible to effectively prevent a simulation malfunction caused by a defect in the analog operation model, and to improve verification accuracy.

  In the present invention, the display driver model includes a display memory model in which an operation of a display memory that stores gradation data that is image data is described, and the simulation processing unit receives the gradation voltage generation circuit model from the gradation voltage generation circuit model. You may make it perform the simulation process which inputs the gradation voltage data selected by the gradation data from the said display memory model from the serial said gradation voltage data to the said socket model.

  In this way, it is possible to accurately verify D / A conversion and the like based on the gradation data in the data driver at the actual circuit level.

  In the present invention, the simulation processing unit includes, among the data drivers, a data latch circuit that latches gradation data, a control circuit that generates a control signal, and a D / A conversion circuit that performs D / A conversion of gradation data. The output circuit provided between the operational amplifier unit and the data line may be simulated using a netlist.

  This makes it possible to verify the data latch circuit, the control circuit, the D / A conversion circuit, and the output circuit at the actual circuit level, thereby improving the verification accuracy.

  In the present invention, the simulation processing unit adds additional data to the serial gradation voltage data in the socket model, and the serial gradation voltage data and the additional data from the socket model are converted into the gradation data. A simulation process for separating the additional data in the socket model may be performed by inputting the data driver model via a voltage generation circuit model.

  In this way, it is possible to perform processing based on the additional data on the gradation voltage data, and the simulation efficiency can be improved.

  In the present invention, the additional data may include at least one of RGB identification data and polarity inversion identification data.

  However, the additional data is not limited to RGB identification data or polarity inversion identification data.

  In the present invention, the socket model includes an internal register for R, an internal register for G, and an internal register for B. The simulation processing unit is configured such that the RGB identification data as additional data includes R data. If the RGB identification data indicates G data, the gradation voltage data paired with the additional data is stored in the R internal register. When the voltage regulation data is stored in the G internal register and the RGB identification data indicates B data, the gradation voltage data paired with the additional data is stored in the B internal register. It may be.

  In this way, using the RGB identification data of the additional data, the R, G, and B gradation voltage data can be stored in the R, G, and B internal registers, respectively. Therefore, an efficient simulation process can be performed in a display panel of a type in which R, G, and B data are multiplexed and input to the data line.

  The verification simulator according to the present invention includes a storage unit that stores information on a model in which device operation is described, and a simulation processing unit that performs a simulation process on the verification target device based on the model and the test input information. The model includes a display driver model in which an operation of a display driver is described, and a display panel model in which an operation of a display panel driven by the display driver is described. The display driver model outputs a data signal. A data driver model in which an operation of the data driver is described, and the simulation processing unit transfers data of N-bit (N> 2) data signals for each data line from the data driver model to the display panel model. It relates to a verification simulator that performs input simulation processing.

  According to the present invention, N-bit data signal data is output from the data driver model for each data line and input to the display panel model. Therefore, even when the display driver includes an analog circuit, the operation of the display driver can be verified by digital logic simulation, and verification efficiency can be improved.

  In the present invention, the display driver model includes a display memory model in which an operation of a display memory for storing gradation data as image data is described, and the simulation processing unit includes an N-bit from the display memory model. Gray scale data is stored in each internal register of the data driver model provided for each data line, and the N-bit gray scale data stored in each internal register is used as data signal data in the display panel model. You may make it perform the simulation process input into this.

  In this way, the analog operation of the data driver can be simulated in a pseudo manner simply by providing a virtual internal register. Therefore, while using a simple model, analog control operations and the like can be verified by digital logic simulation, and verification efficiency can be improved.

  In the present invention, the simulation processing unit performs conversion processing on the N-bit gradation data stored in the internal register, and uses the gradation data after the conversion processing as data signal data. You may make it perform the simulation process input into the said display panel model.

  In this way, it becomes possible to simulate the conversion process in the data driver in a pseudo manner.

  The present invention also relates to a verification simulation method for performing a simulation process of a verification target device based on a model in which device operation is described and test input information, wherein the model is a display driver in which operation of a display driver is described A display panel model describing the operation of the display panel driven by the display driver, and a socket model virtually provided between the display driver model and the display panel model, The driver model describes a gradation voltage generation circuit model that describes the operation of a gradation voltage generation circuit that generates a gradation voltage, and an operation of a data driver that outputs a data signal based on the generated gradation voltage. Serial grayscale voltage data generated by the socket model. The grayscale voltage generation circuit model is input to the data driver model, serial data from the data driver model is input to the socket model and converted to parallel data, and the parallel data obtained by the conversion is converted to parallel data. The present invention relates to a verification simulation method for performing a simulation process for inputting data as data signal to the display panel model.

  The present invention also relates to a verification simulation method for performing a simulation process of a verification target device based on a model in which device operation is described and test input information, wherein the model is a display driver in which operation of a display driver is described A display panel model describing an operation of a display panel driven by the display driver, and the display driver model includes a data driver model describing an operation of a data driver that outputs a data signal, The present invention relates to a verification simulation method for performing a simulation process in which data of an N-bit (N> 2) data signal is input from the data driver model to the display panel model for each data line.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Display Driver FIG. 1 shows a configuration example of a display driver 510 that is a verification target device of the verification simulator of the present embodiment. The configuration of the display driver 510 is not limited to that shown in FIG. 1, and various modifications can be made.

  The display panel 512 includes a plurality of data lines (source lines), a plurality of scanning lines (gate lines), and a plurality of pixels specified by the data lines and the scanning lines. A display operation is realized by changing the optical characteristics of the electro-optical element (in a narrow sense, a liquid crystal element) in each pixel region. This display panel 512 can be constituted by an active matrix type panel using switching elements such as TFT and TFD. Note that the display panel 512 may be a panel other than the active matrix method, or may be a panel other than the liquid crystal panel (such as an organic EL panel).

  The display memory 520 (RAM) stores image data. The memory cell array 522 includes a plurality of memory cells and stores image data (display data) for at least one frame (one screen). A row address decoder 524 (MPU / LCD row address decoder) performs a decoding process on the row address and performs a word line selection process of the memory cell array 522. A column address decoder 526 (MPU column address decoder) performs a decoding process on the column address and performs a selection process of a bit line of the memory cell array 522. The write / read circuit 528 (MPU write / read circuit) performs image data write processing to the memory cell array 522 and image data read processing from the memory cell array 522.

  The logic circuit 540 (for example, automatic placement and routing circuit) generates a display control signal for controlling display timing and data processing timing. The logic circuit 540 can be formed by automatic placement and routing such as a gate array (G / A). The control circuit 542 generates various control signals and controls the entire apparatus. A display timing control circuit 544 generates a display timing control signal and controls reading of image data from the display memory 520 to the display panel 512 side.

  The internal interface circuit 545 (driver-side interface circuit) is a circuit that performs interface processing with an external device (such as a host device), and includes a host interface circuit 546 and an RGB interface circuit 548. A host (MPU) interface circuit 546 implements a host interface that generates an internal pulse and accesses the display memory 520 for each access from the host. The RGB interface circuit 548 realizes an RGB interface that writes moving image RGB data to the display memory 520 using a dot clock. Note that only one of the host interface circuit 546 and the RGB interface circuit 548 may be provided. Alternatively, a YUV interface circuit that realizes an interface with a camera device or the like may be provided. Alternatively, a high-speed serial interface circuit that realizes high-speed serial transfer via a serial bus may be provided. In this high-speed serial transfer, high-speed serial transfer with an external device (such as a host device) is realized by current driving or voltage driving the differential signal line of the serial bus.

  The data driver 550 is a circuit that generates a data signal for driving the data lines of the display panel 512. Specifically, the data driver 550 receives gradation data as image data from the display memory 520 and receives a plurality of (for example, 64 levels) gradation voltages (reference voltages) from the gradation voltage generation circuit 610. Then, a voltage corresponding to the gradation data is selected from the plurality of gradation voltages and is output to each data line of the display panel 512 as a data signal (data voltage).

  The scan driver 570 is a circuit that generates a scan signal for driving the scan lines of the display panel. Specifically, a signal (enable input / output signal) is sequentially shifted in a built-in shift register, and a signal obtained by converting the level of the shifted signal is output to each scanning line of the display panel 512 as a scanning signal (scanning voltage). To do. The scan driver 570 includes a scan address generation circuit and an address decoder. The scan address generation circuit generates and outputs a scan address, and the address decoder performs a scan address decoding process to generate a scan signal. Also good.

  The power supply circuit 590 is a circuit that generates various power supply voltages. Specifically, the input power supply voltage and the internal power supply voltage are boosted by a charge pump method using a boosting capacitor and a boosting transistor included in a built-in boosting circuit. The voltage obtained by the boosting is supplied to the data driver 550, the scan driver 570, and the gradation voltage generation circuit 610 as a power supply voltage.

  The gradation voltage generation circuit 610 (γ correction circuit) is a circuit that generates gradation voltages. Specifically, the built-in voltage dividing circuit (selection voltage generating circuit) generates a divided voltage, and the built-in gradation voltage generating circuit has, for example, 64 (64 gradations) among the generated divided voltages. A gradation voltage is selected and output to the data driver 550.

2. Verification Simulator FIG. 2 shows a configuration example of the verification simulator of this embodiment, and FIGS. 3 and 4 show examples of the simulation environment of the verification simulator.

  In FIG. 2, the storage unit 200 stores model information describing the operation of devices such as a display driver, a display panel, and an external device (host device). The function of the storage unit 200 is realized by hardware such as a memory (RAM) or a hard disk incorporated in a verification workstation (computer system in a broad sense). Further, as models for storing the information in the storage unit 200, a behavior level model having a high abstraction level such as a Verilog behavior model, an RTL (Register Transfer Level) model having a lower abstraction level than the behavior level, and the like. A logic level model such as a netlist having a lower abstraction level than RTL can be used.

  The simulation processing unit 210 (simulation execution unit) performs a simulation process for the verification target device based on the model stored in the storage unit 200 and the test input information 150. The function of the simulation processing unit 210 can be realized by hardware such as a CPU incorporated in the verification work system and verification software. As the verification software, logic simulation software such as Verilog may be used, analog simulation software such as SPICE, or a mixture of logic simulation software and analog simulation software is used. May be.

  The test input information 150 (test bench, test data) can include a command file 152. The command file 152 describes a command for operating the display driver (device to be verified in a broad sense) and parameters to be set in the register (command register). That is, these commands are listed and described in the command file 152. The test input information 150 can include image data 154 such as RGB data. The image data 154 can be extracted from the image data file 156 for test input.

  The image data file 160 output by the simulation processing unit 210 displays an image to be displayed on the display panel by the image data 154 included in the test input information 150 on the display device (CRT, monitor) of the verification workstation. Is. As the image data file 160, the simplest PPM (Portable Pix Map) image format in the ASCII format can be used. If PPM is used, image data can be easily displayed on a display device of a workstation by using utility software of UNIX (registered trademark).

  As shown in FIG. 3, as a model constituting the simulation environment, there are a display driver model 10 in which the operation of the display driver is described, and a display panel model 90 in which the operation of the display panel driven by the display driver is described. There is also an external interface circuit model 130 in which the operation of an external interface circuit (host side interface circuit) included in an external device of the display driver is described.

  In FIG. 4, a virtual socket model 110 (virtual interface model) is provided between the display driver model 10 and the display panel model 90.

  Note that a nonvolatile memory model in which the operation of the nonvolatile memory (EEPROM) for setting the initial state of the display driver is described may be used. Examples of external devices including an external interface circuit include devices (host devices) such as an MPU (Micro Processor Unit), a baseband engine, an application processor, and an image processing controller (display controller).

  3 and 4, the display driver model 10 includes a data driver model 20 in which an operation of a data driver that outputs a data signal is described. Also included are a scan driver model 30 in which the operation of a scan driver that outputs a scan signal is described, and a display memory model 40 in which the operation of a display memory that stores gradation data that is image data is described. The display driver model 10 includes a power supply circuit model 50 in which the operation of the power supply circuit is described, a gradation voltage generation circuit model 60 in which the operation of the gradation voltage generation circuit that generates the gradation voltage is described, and a display control signal. Includes a logic circuit model 70 in which the operation of the logic circuit that generates at least is described. Also included is an internal interface circuit model 80 in which operations of internal interface circuits such as an MPU interface circuit, RGB interface circuit, YUV interface circuit, and high-speed serial interface circuit are described.

  In this embodiment, the simulation processing unit 210 in FIG. 2 performs a simulation process based on the test input information 150, the display driver model 10, the display panel model 90, and the socket model 110. Specifically, serial gradation voltage data generated by the socket model 110 is input to the data driver model 20 via the gradation voltage generation circuit model 60, and serial data (gradation data) from the data driver model 20 is input. Voltage data) is input to the socket model 110. In the socket model 110, serial data is converted into parallel data. Then, a simulation process for inputting the parallel data obtained by the conversion to the display panel model 90 is performed. More specifically, the gradation selected from the gradation data from the display memory model 40 out of the serial gradation voltage data (gradation voltage data corresponding to the number of gradations) from the gradation voltage generation circuit model 60. Control voltage data (gradation voltage data selected by D / A conversion) is input to the socket model 110. In this case, the simulation processing unit 210 includes, among data drivers (data driver models), a data latch circuit that latches gradation data, a control circuit that generates control signals, and a D / A that performs D / A conversion of gradation data. For the output circuit provided between the conversion circuit, the operational amplifier unit and the data line, simulation processing is executed using a netlist. In the socket model 110, additional data is added to the serial gradation voltage data, and the serial gradation voltage data and the additional data from the socket model 110 are converted into the data driver model 20 via the gradation voltage generation circuit model 60. To enter. Then, analysis is performed in the socket model 110 to separate the additional data.

  Further, the simulation processing unit 210 may perform a simulation process in which data of an N-bit (N> 2) data signal is input from the data driver model 20 to the display panel model 90 for each data line. In this case, N-bit gradation data from the display memory model 40 is stored in a virtual internal register provided for each data line, and the stored N-bit gradation data is used as data signal data. Input to the display panel model 90. The N-bit gradation data stored in the internal register provided in the data driver model 20 is converted, and the converted gradation data is input to the display panel model 90.

  As shown in FIGS. 3 and 4, according to the present embodiment, it is possible to realize a system simulation with a mounting image in which peripheral device models such as the display panel model 90 and the external interface circuit model 130 are added. The analog block inside the display driver is modeled by Verilog's behavior model. In addition, simulation results are converted to enable visual verification of the displayed image.

  Specifically, a command file 152 (MPU command) described as a test bench is input to the external interface circuit model 130 (MPU model), and MPU interface signals, RGB interface signals, etc. are converted by the external interface circuit model 130 conversion processing. The interface signal data is generated. Then, binary data of the interface signal is input to the terminal of the display driver model 10. Similarly, image data 154 to be displayed on the screen is also input to the display driver model 10 via the external interface circuit model 130. For example, RGB format data is used as the image data 154. YUV format data may be used.

  Further, the internal blocks of the display driver are mostly analog blocks including analog circuits except for the logic circuit (gate array). Since the analog block cannot verify the correct operation in the Verilog logic simulation based on the netlist output, for example, the Verilog behavior model describing the block level operation is used. Although the verification level of the analog operation varies depending on how to create the behavior model of the analog block, in this embodiment, an analog control operation such as a power-on sequence can be verified by a logic simulation.

  Specifically, there are the following special expressions of the behavior model of the analog block. For example, a data driver D / A converts grayscale data from a display memory to generate a data voltage that is a grayscale voltage. However, the gradation voltage value is an analog value and cannot be expressed by a logic simulator. Therefore, in FIG. 3, for example, 6-bit (N-bit in a broad sense) gradation data that is image data from the display memory model 40 is stored in virtual internal registers provided in the data driver model 20. Then, conversion processing (polarity inversion processing, RGB inversion processing, color reduction mode processing, etc.) is performed on the gradation data stored in each internal register, and the gradation data after the conversion processing is converted into data signal data To the display panel model 90.

  Alternatively, instead of providing such an internal register, a socket model 110 is provided between the display driver model 10 and the display panel model 90 as shown in FIG. The serial grayscale voltage data generated by the socket model 110 is input to the data driver model 20 via the grayscale voltage generation circuit model 60 of the display driver model 10, and the data driver model 20 returns to the socket model 110. Then, the serial data is converted into parallel data in the socket model 110 and input to the display driver model 90.

  The scanning voltage value output to the scanning signal of the display panel is an analog value and cannot be expressed by logic simulation. Therefore, in the scan driver model 30, the generation of the scan voltage (selection voltage) is expressed by logic “1”.

  Further, the potential difference of the voltage generated by the boosting operation is an analog value and cannot be expressed by logic simulation. Therefore, in the power supply circuit model 50, the boosting condition is determined, and the generation of the boosted voltage is expressed by logic “1”. That is, when the boost condition is satisfied, a logic “1” is output. Similarly, the gradation voltage value obtained by resistance division is an analog value and cannot be expressed by logic simulation. Therefore, in the gradation voltage generation circuit model 60, the operating condition is determined, and the generation of the gradation voltage is expressed by logic “1”. That is, when the operating condition is satisfied, a logic “1” is output. Then, if the power supply circuit and the gradation voltage generation circuit are not operating normally, create a behavior model for the data driver and scan driver so that the data driver and scan driver that operate by receiving signals from these circuits do not operate. . That is, the data driver model 20 and the scan driver model 30 are created so that the operation is not started unless the logic “1” is output from the power supply circuit model 50 or the gradation voltage generation circuit model 60. By doing so, analog control operations such as a power-on sequence can be verified by logic simulation.

  3 and 4, a logic circuit (gate array) netlist is used as the logic circuit model 70. That is, the logic circuit (540 in FIG. 1) does not include an analog element and can directly input the net list to a logic simulator such as Verilog. The configuration and operation of the logic circuit are changed as needed according to the specifications. Therefore, for the logic circuit model 70, a logic simulation such as Verilog is performed using the net list of the logic circuit as it is. By doing so, the simulation accuracy can be improved, and the verification simulation method of the present embodiment can be easily applied to display drivers of various specifications. Note that the internal interface circuit model 80 may also use a net list of the internal interface circuit for at least a part thereof.

3. Simulation Using Internal Register FIG. 5 shows a detailed configuration example of the data driver 550 and the gradation voltage generation circuit 610. The data driver 550 includes a driver cell 552 provided for each data line (SS1, SS2,...). The driver cell 552 includes a data latch & conversion circuit 554, a control circuit 556, a D / A conversion circuit 558, an operational amplifier unit 560, and an output circuit 562.

  The data latch & conversion circuit 554 (data latch circuit in a broad sense) latches the gradation data GD1 [5: 0] from the display memory 520. The data latch & conversion circuit 554 performs RGB inversion processing. That is, processing for changing the arrangement of RGB data from the arrangement in the order of R, G, B to the order of B, G, R is performed. Thereby, it becomes possible to cope with various types of display panels having different mounting forms.

  The control circuit 556 generates various control signals for the D / A conversion circuit 558, the operational amplifier unit 560, and the output circuit 562, and performs data conversion processing on the gradation data. Specifically, power saving processing is performed using the control signals to the D / A conversion circuit 558, the operational amplifier unit 560, and the output circuit 562, and polarity inversion processing and color reduction mode processing are performed on gradation data. For example, in the polarity inversion process, gradation data of “63”, “62”, “61” is set to “0”, “1”, “2”, for example, in the negative polarity period. In the color reduction mode, a process of switching the number of display colors expressed by the gradation data to, for example, 8 colors is performed.

  The D / A conversion circuit 558 is a circuit that D / A converts digital gradation data into an analog data voltage. Specifically, D / A conversion is realized by selecting a voltage corresponding to digital gradation data from the gradation voltages from the gradation voltage generation circuit 610.

  The operational amplifier unit 560 performs an impedance conversion process on the data signal (data voltage). The operational amplifier unit 560 includes, for example, an operational amplifier OP (operational amplifier) and a switching element SW. For example, when the switching element SW is turned on, DAC driving in which the data line SS1 is directly driven by the D / A conversion circuit 558 is performed. Thereby, DAC driving and operational amplifier + DAC driving are realized.

  The output circuit 562 performs voltage setting for the data line SS1. For example, when the display panel display off command is input, if the voltage of the data line SS1 is set by using the D / A conversion circuit 558 or the operational amplifier unit 560, it takes time to charge and discharge the charge. It takes a long time for the voltage to be set to a low level or a high level. In such a case, the output circuit 562 directly sets the voltage of the data line SS1 to a low level or a high level. In this way, when the display off command for the display panel is input, the display panel can be immediately displayed in white (in the case of normally white liquid crystal) or the like.

  The gradation voltage generation circuit 610 (γ correction circuit) includes a voltage dividing circuit 612 (selection voltage generation circuit) and a gradation voltage selection circuit 614. The voltage dividing circuit 612 outputs divided voltages VS0 to VS255 (selection voltages) based on the high-voltage power supply voltages VDDH and VSSH generated by the power supply circuit 590 (see FIG. 1). Specifically, the voltage circuit 612 includes a ladder resistor circuit having a plurality of resistor elements connected in series. A voltage obtained by dividing VDDH and VSSH by the ladder resistor circuit is output as divided voltages VS0 to VS255. The gradation voltage selection circuit 614 is based on the gradation characteristic adjustment data set in the adjustment register 616 by the logic circuit 540 (see FIG. 1), for example, in the case of 64 gradations from among the divided voltages VS0 to VS255. Selects 64 voltages and outputs them as gradation voltages V0 to V63. In this way, it is possible to generate a gradation voltage having an optimum gradation characteristic (γ correction characteristic) according to the display panel.

  Now, the data driver 550 and the gradation voltage generation circuit 610 in FIG. 5 include analog circuits. The gradation voltage generated by the gradation voltage generation circuit 610 and the data voltage output to the data line SS1 are analog values and cannot be expressed by digital logic simulation.

  Therefore, in this embodiment, the data driver 550 and the gradation voltage generation circuit 610 are modeled by a Verilog behavior model or the like, and simulation processing is performed.

  Specifically, as shown in FIG. 6, data (binary data) of 6 bits (N bits in a broad sense, N> 2) for each data line is transferred from the data driver model 20 to the display panel model 90. Perform the input simulation process. That is, data of a 6-bit data signal is input to the display panel model 90 for each data line without going through the data line at the actual circuit level. In this way, it becomes possible to verify the display driver using a digital logic simulation such as Verilog, and it is possible to verify the operation close to the actual operation of the display driver.

  More specifically, a virtual internal register 22 is provided in the data driver model 20 as shown in FIG. The internal register 22 is a 6-bit (N-bit) register provided for each data line.

  Then, 6-bit (N-bit) gradation data from the display memory model 40 is stored in each internal register 22 provided for each data line, and the stored 6-bit gradation data is used as data signal data. Then, a simulation process for inputting to the display panel model 90 is performed. Specifically, the display panel model 90 refers to the data in the internal register 22 of the data driver model 20 and transfers 6-bit parallel data from the data driver model 20 to the display panel model 90 for each data line. Such data transfer by reference can be easily realized using Verilog description.

  In FIG. 6, the display panel model 90 includes a data capture unit 92, a polarity inversion unit 94, and an image data file creation unit 96.

  Here, the data capture unit 92 has internal registers for all pixels of the display panel (internal registers corresponding to all pixels). When the data of the scanning signal GS1 from the display driver model 10 changes from “1” to “0”, among the internal registers for all the pixels provided in the data capture unit 92, the internal register corresponding to GS1 is selected. The data (parallel gradation data) from the internal register 22 of the data driver model 20 is stored and captured. Similarly, when the data of the scanning signal GS2 from the display driver model 10 changes from “1” to “0”, among the internal registers for all the pixels provided in the data capture unit 92, the internal register corresponding to GS2 is stored. On the other hand, the data from the internal register 22 of the data driver model 20 is stored and captured.

  The polarity inversion unit 94 performs polarity inversion processing on the data stored in the internal register of the data capture unit 92 based on the signal FR (polarity inversion signal) from the display driver model 10. That is, the polarity of the signal FR is determined, and normal rotation / inversion processing of data (image data) is performed. Then, the image data file creation unit 96 generates and outputs an image data file 160 using the signal VSYNC (vertical synchronization signal) from the display driver model 10 as a trigger.

  FIG. 7 shows a flowchart of the simulation process of FIG. First, the display memory model 40 outputs gradation data (step S1). Then, the gradation data is stored in the internal register 22 of the data driver model 20 using a control signal for the D / A conversion circuit and the operational amplifier as a trigger (step S2).

  Next, conversion processing such as RGB inversion processing, polarity inversion processing, and color reduction mode processing is executed on the gradation data stored in the internal register 22 (step S3). That is, RGB inversion processing (processing for converting RGB to BGR) performed by the data latch & conversion circuit 554 of FIG. 5, polarity inversion processing, and color reduction mode (8-color mode) processing performed by the control circuit 556 are executed. Then, the gradation data after the conversion process is stored in the internal register 22 without being output to the data line output terminal (step S4). Then, the gradation data is passed to the display panel model 90 via the internal register 22.

  6 and 7, the analog operation of the data driver can be simulated in a pseudo manner simply by providing the virtual internal register 22. Therefore, the system simulation with the mounting image as shown in FIGS. 3 and 4 can be realized by using digital logic simulation such as Verilog. Therefore, it becomes possible to verify an analog control operation or the like by digital logic simulation while using a simple model, and the verification efficiency can be improved.

4). Simulation Using Socket Model The method shown in FIGS. 6 and 7 has an advantage that a simple model using the internal register 22 can be used as the data driver model 20. However, since the net list of the actual circuit of the data driver is not used, there is a disadvantage that the verification accuracy is inferior. In other words, since the behavior model itself is a pseudo model, the designer may misunderstand the operation specifications of the display driver or create an incorrect operation model, and the validity of verification cannot be sufficiently guaranteed. There are advantages.

  On the other hand, a method of creating an operation model of an analog block such as a data driver using the analog description language AHDL is also conceivable. In this method, the analog block behaves like an analog, so there is no problem with the creation of the analog operation. However, as long as it is a model, the problem of misidentification of specifications remains. Also, when trying to realize a system simulation as shown in FIGS. 3 and 4, the verification simulation must be switched from a digital logic simulation to a mixed signal simulation. The mixed signal simulation is not suitable for verifying all functions of the display driver because the simulation time is enormous.

  Therefore, in the method described with reference to FIG. 8, an analog block is configured by a netlist for digital logic simulation, and gradation voltages that should be handled as analog values are handled as serial data. Is realized by digital logic simulation.

  Specifically, instead of modeling the entire analog block such as a data driver, a method (partial modeling) of modeling only the minimum necessary analog circuit is employed. Even though it is an analog block, the internal control circuit is composed of logic circuits, so that part uses a Verilog netlist output from the schematic, and a pseudo operation model for only the minimum necessary analog circuit Create By doing so, the unit of the analog model becomes smaller, so the probability of misrecognizing the specification and describing the model behavior is reduced, and the verification accuracy can be improved.

  For example, in the data driver 550 of FIG. 5, only the operational amplifier OP of the operational amplifier unit 560 is described by a Verilog behavior model and simulation is performed, and other circuits (data latch & conversion circuit, control circuit, D / A conversion circuit, output) For the circuit, etc., the simulation is executed using the Verilog netlist and Verilog library output from the schematic. According to this method, the control circuit inside the data driver 550 reliably performs the operation intended by the designer, so that the abnormal operation caused by the model hardly occurs and the verification accuracy can be improved.

  Further, as described above, the gradation voltage from the gradation voltage generation circuit 610 cannot be expressed by Verilog digital logic simulation. Therefore, a model called a socket model 110 is introduced to enable output from the data driver model 20 by using a serial data format as gradation voltage data. Serial gradation voltage data is generated in the socket model 110 by the number of gradation voltages, and the serial gradation voltage data is supplied to the gradation voltage generation circuit model 60 (γ model) via the ladder resistance model. (Virtual connection). Since the gradation voltage generation circuit model 60 supplies gradation voltages to the data driver model 20, the data driver model 20 can handle serial gradation voltage data from the gradation voltage generation circuit model 60. Therefore, the serial gradation voltage data supplied from the gradation voltage generation circuit model 60 is selected in the data driver model 20 based on the gradation data, serial / parallel conversion is performed in the socket model 110, and a display panel model is selected. 90.

  Specifically, as shown in FIG. 8, a socket model 110 that is virtually provided between the display driver model 10 and the display panel model 90 is prepared. The socket model 110 (virtual connection model) is a model for virtually connecting the display driver model 10 and the display panel model 90.

  The serial gradation voltage data generated by the socket model 110 is input to the data driver model 20 via the gradation voltage generation circuit model 60. Then, serial data from the data driver model 20 is input to the socket model 110 and converted into parallel data, and a simulation process is performed in which the parallel data obtained by the conversion is input to the display panel model 90 as data signal data. .

  For example, in FIG. 8, the socket model 110 includes a shift clock generation unit 112, a clock number counting unit 114, a serial gradation voltage data generation unit 116, a serial / parallel conversion unit 118, and an internal register 120. The shift clock generator 112 generates a shift clock, and the clock number counter 114 counts the number of shift clocks. The serial grayscale data generation unit 116 operates based on the count value from the clock number counting unit 114 and generates serial grayscale voltage data. That is, binary serial gradation voltage data corresponding to each of the gradation voltages V0 to V63 is generated. For example, (000000), (000001), (0000010), (0000011), and the like are generated as serial gradation voltages corresponding to the gradation voltages V0, V1, V2, and V3, respectively. Then, each of the generated serial gradation voltage data is supplied to each of the nodes V0 to V63. This can be achieved by virtual connection using Verilog.

  The D / A conversion circuit 558 configured by the net list selects a node corresponding to the gradation data from the nodes V0 to V63 based on the gradation data from the display memory model 40. For example, in the positive polarity period, when the gradation data is “63”, the node of V63 is selected, and when the gradation data is “62”, the node of V62 is selected. On the other hand, in the negative polarity inversion period, when the gradation data is “63”, the node of V0 is selected, and when the gradation data is “62”, the node of V1 is selected. Then, the serial gradation voltage data supplied to the selected node is output to the data line via the D / A conversion circuit 558, the operational amplifier unit 560, and the output circuit 562, and is input again to the socket model 110.

  The serial / parallel conversion circuit 118 of the socket model 110 operates based on the count value from the clock number counting unit 114, performs serial / parallel conversion of serial gradation voltage data output to the data line, and provides 64 gradations. Restore to parallel data. The obtained parallel data is stored in the internal register 120. The parallel data stored in the internal register 120 is transferred from the socket model 110 to the display panel model 90 by a method similar to the method described with reference to FIGS. That is, when the display panel model 90 refers to the internal register 120, the parallel data in the internal register 120 is stored in the internal register provided in the data capture unit 92 of the display panel model 90.

  In FIG. 8, the serial gradation voltage data generation unit 116 and the serial / parallel conversion unit 118 operate based on the count value from the clock number counting unit 114. In this way, the serial gradation voltage data generation unit 116 and the serial / parallel conversion unit 118 operate in synchronism, and appropriate serial / parallel conversion can be realized. That is, the serial / parallel converter 118 can determine serial data parallel from the data driver model 20 (separation between serial grayscale voltage data and the next serial grayscale voltage data) and perform serial / parallel conversion. It becomes like this.

  According to the method of FIG. 8, the circuit of the data driver model 20 is configured by a netlist except for some circuits such as an operational amplifier. Therefore, it is possible to effectively prevent a simulation malfunction caused by a failure of the analog operation model. Further, since the signal of the gradation voltage data can be observed as a signal passing through the data driver circuit from the gradation voltage generation circuit, the gradation voltage generation circuit and the data driver can be accurately verified at the actual circuit level.

  For example, when a display off command of the display panel is input, the output circuit 562 performs an operation of directly setting the voltage of the data line SS1 to a low level or a high level. It is difficult to verify the operation of the output circuit 562 by the method shown in FIGS.

  On the other hand, in the method of FIG. 8, serial gradation voltage data is output to the data line from the node of V0 to V63 via the D / A conversion circuit 558, the operational amplifier unit 560, and the output circuit 562. Therefore, the operation of the output circuit 562 when the display off command is input can be accurately verified, and the verification accuracy can be improved.

  As shown in FIG. 9A, additional data may be added to the serial gradation voltage data when the serial gradation voltage data is created. That is, as serial data, additional data is prepared in addition to serial gradation voltage data, and packet data combining the serial gradation voltage data and additional data is generated in the socket model 110. Specifically, the serial gradation voltage data generation unit 116 generates packet data. The additional data in this case can include, for example, at least one of RGB identification data and polarity inversion identification data. Here, the RGB identification data is data for identifying whether the serial gradation voltage data is R, G, or B data. The polarity reversal identification data is data for identifying the positive polarity and the negative polarity of polarity reversal.

  The serial grayscale voltage data and additional data from the socket model 110 are input to the data driver model 20 via the grayscale voltage generation circuit model 60, and the socket model 110 performs a simulation process for separating the additional data. That is, the generated serial data (serial gradation voltage data and additional data) is output from the nodes V0 to V63 to the data line via the D / A conversion circuit 558, the operational amplifier unit 560, and the output circuit 562, and is connected to the socket. It is captured in the model 110. Then, packet analysis is performed in the socket model 110, and the gradation voltage data and the additional data are separated from the serial data. Based on the separated additional data, various conversion processes (RGB separation process and polarity inversion process) are performed on the gradation voltage data.

  For example, as shown in FIG. 9B, in the low-temperature polysilicon panel (hereinafter referred to as LTPS panel), the display driver 510 side multiplexes the R, G, and B data into the data signal to display the data. On the panel 512 side, the multiplexed R, G, and B data are separated. Specifically, the switching elements TM1R, TM1G, and TM1B (transistors) that are controlled to be turned on and off by the switching signals SM1R, SM1G, and SM1B allow the R, G, and B data to be time-divided with respect to the data signal on the data line SS1. Multiplexed. The multiplexed R, G, and B data are separated by switching elements TD1R, TD1G, and TD1B (transistors) that are controlled to be turned on and off by switching signals SD1R, SD1G, and SD1B. Of supplied.

  In such an LTPS panel, it is possible to verify the operation of multiplexing processing and separation processing by using RGB identification data as additional data. Specifically, as shown in FIG. 9C, in the socket model 110, a serial / parallel conversion & separation unit 119 is provided instead of the serial / parallel conversion unit 118, and R and G are used instead of the internal register 120. And B internal registers 120R, 120G, and 120B are provided. Then, the serial / parallel conversion & separation unit 119 separates the additional data from the serial data. When the RGB identification data of the additional data indicates R data, the gradation voltage data paired with the additional data is stored in the R internal register 120R. Similarly, when the RGB identification data of the additional data indicates G data and B data, the gradation voltage data paired with the additional data is stored in the G and B internal registers 120G and 120B.

  The display panel model 90 (data capture unit) is also provided with internal registers 93R, 93G, and 93B for R, G, and B. The gradation voltage data (parallel data) stored in the internal registers 120R, 120G, and 120B of the socket model 110 are transferred to and stored in the internal registers 93R, 93G, and 93B of the display panel model 90, respectively. In this case, which of the internal registers 93R, 93G, and 93B stores the gradation voltage data can be realized by using the switching signals SD1R, SD1G, and SD1B in FIG. 9B. Note that the polarity reversal identification data, which is additional data, can be used effectively when the display panel model 90 does not have the polarity reversing unit 94 as shown in FIG. That is, in this case, the polarity inversion processing of the gradation voltage data paired with the additional data may be performed based on the polarity inversion identification data included in the additional data.

5. Display Panel Model In the display panel model 90 of the present embodiment, processing for converting data input from the display driver model 10 into display image data is performed. For example, as shown in FIG. 10, the display panel model 90 receives data signals SS1, SS2, SS3... And data of scanning signals GS1, GS2,. Based on these data, image data at each pixel (pixel specified by the data signal and the scanning signal) of the display panel is obtained, and an image data file 160 including the image data at each obtained pixel is created. . That is, an image dump file of a display panel image is created as shown in FIG.

  More specifically, as indicated by A1 and A2 in FIG. 10, the internal register of the display panel model 90 uses the image data R [ 5: 0], G [5: 0], and B [5: 0] are fetched from the display driver model 10. Next, the polarity (positive polarity, negative polarity) of the common signal (signal FR) is determined, and normal rotation / inversion processing of the image data captured in the internal register is performed. Next, an image data file 160 is created and output using a vertical synchronization signal (signal VSYNC) as a trigger.

  FIG. 11 shows an example of the image data file 160. Note that the image data file 160 of the present embodiment is not limited to the format shown in FIG. 11, and various modifications can be made.

  An image data file 160 in FIG. 11 is a file having the simplest image format in the ASCII format called PPM (Portable Pix Map). Specifically, the image data file 160 includes a format identifier (P1: binary ASCII, P2: grayscale ASCII, P3: full color ASCII), image size (horizontal, vertical), number of gradations (maximum tone value), image data. (RGB image data represented by decimal gradation values). After the simulation is completed, the created image data file 160 is displayed on the screen of the workstation display device using UNIX (registered trademark) utility software or the like, and the operation of the display driver is verified. In this way, the simulation result can be visually captured instantaneously in the form of a display image. In addition, since it is not necessary to visually check all the complicated control signals on the waveform display, the design efficiency can be improved. Also, bugs that are difficult to find even for designers who are familiar with the specifications can be found. In addition, even designers who do not understand detailed operation specifications can participate in verification work, and work can be divided.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are included in the scope of the present invention. For example, a term (display driver, 6-bit, etc.) described together with a different term (verified device, N-bit, etc.) in a broader sense or the same meaning at least once in the specification or drawing is used anywhere in the specification or drawing. Can also be replaced by their different terms.

  Further, the configuration of the verification simulator and the verification simulation method are not limited to those described in the present embodiment. For example, a method that does not output simulation result data as an image data file or a method that does not use an external interface circuit model may be employed. The simulation method is not limited to a digital logic simulation method such as Verilog.

The structural example of the display driver which is a verification object device. The structural example of the verification simulator of this embodiment. The simulation environment of the verification simulator of this embodiment. The simulation environment of the verification simulator of this embodiment. 3 is a detailed circuit configuration example of a display driver. Explanatory drawing of the simulation method using an internal register. The flowchart of the simulation method using an internal register. Explanatory drawing of the simulation method using a socket model. FIGS. 9A, 9B and 9C are explanatory diagrams of a method using additional data. Explanatory drawing of the production | generation method of an image data file. An example of an image data file.

Explanation of symbols

10 display driver model, 20 data driver model, 22 internal registers,
30 scan driver model, 40 display memory model, 50 power supply circuit model,
60 gradation voltage generation circuit model, 70 logic circuit model,
80 internal interface circuit model, 90 display panel model,
92 data capture unit, 93R, 93G, 93B internal registers,
94 polarity inversion unit, 96 image data file creation unit, 110 socket model,
112 shift clock generation unit, 114 clock number counting unit,
116 serial gradation voltage data generation unit, 118 serial / parallel conversion unit,
119 Serial / parallel conversion & separation unit,
120, 120R, 120G, 120B internal registers,
130 external interface circuit model, 150 test input information,
152 command file, 154 image data, 160 image data file,

Claims (11)

A storage unit for storing information of a model in which the operation of the device is described;
A simulation processing unit that performs a simulation process of the verification target device based on the model and the test input information,
The model is
A display driver model in which the operation of the display driver is described, a display panel model in which the operation of the display panel driven by the display driver is described, and virtually provided between the display driver model and the display panel model Socket model, and
The display driver model is
A gradation voltage generation circuit model that describes the operation of a gradation voltage generation circuit that generates gradation voltages, and a data driver model that describes the operation of a data driver that outputs a data signal based on the generated gradation voltages Including
The simulation processing unit
Serial grayscale voltage data generated by the socket model is input to the data driver model via the grayscale voltage generation circuit model, and serial data from the data driver model is input to the socket model to receive parallel data. A verification simulator which performs a simulation process of converting data into data and inputting parallel data obtained by the conversion as data signal data to the display panel model. In claim 1,
The display driver model is
Including a display memory model describing the operation of a display memory for storing gradation data as image data;
The simulation processing unit
Performing a simulation process of inputting, to the socket model, gradation voltage data selected from gradation data from the display memory model among serial gradation voltage data from the gradation voltage generation circuit model; Verification simulator characterized by In claim 1 or 2,
The simulation processing unit
Among the data drivers, a data latch circuit that latches gradation data, a control circuit that generates control signals, a D / A conversion circuit that performs D / A conversion of gradation data, and an operational amplifier section and a data line are provided. A verification simulator characterized by performing a simulation process using a netlist for the output circuit. In any one of Claims 1 thru | or 3,
The simulation processing unit
In the socket model, additional data is added to the serial gradation voltage data, and the serial gradation voltage data and the additional data from the socket model are converted into the data driver model via the gradation voltage generation circuit model. And performing a simulation process for separating the additional data in the socket model. In claim 4,
The verification simulator, wherein the additional data includes at least one of RGB identification data and polarity inversion identification data. In claim 5,
The socket model includes an internal register for R, an internal register for G, and an internal register for B,
The simulation processing unit
When the RGB identification data as additional data indicates R data, the gradation voltage data paired with the additional data is stored in the R internal register, and the RGB identification data indicates G data. In this case, the gradation voltage data paired with the additional data is stored in the G internal register, and when the RGB identification data indicates B data, the gradation voltage paired with the additional data A verification simulator, wherein data is stored in the B internal register. A storage unit for storing information of a model in which the operation of the device is described;
A simulation processing unit that performs a simulation process of the verification target device based on the model and the test input information,
The model is
A display driver model describing the operation of the display driver, and a display panel model describing the operation of the display panel driven by the display driver,
The display driver model is
Includes a data driver model that describes the operation of the data driver that outputs the data signal,
The simulation processing unit
A verification simulator for performing a simulation process for inputting data of an N-bit (N> 2) data signal for each data line from the data driver model to the display panel model. In claim 7,
The display driver model is
Including a display memory model describing the operation of a display memory for storing gradation data as image data;
The simulation processing unit
N-bit gradation data from the display memory model is stored in each internal register of the data driver model provided for each data line, and the N-bit gradation data stored in each internal register is A verification simulator for performing a simulation process for inputting data to the display panel model as data signal data. In claim 8,
The simulation processing unit
A conversion process is performed on the N-bit gradation data stored in the internal register, and a simulation process is performed in which the gradation data after the conversion process is input to the display panel model as data signal data. A verification simulator characterized by that. A verification simulation method for performing simulation processing of a device to be verified based on a model in which device operation is described and test input information,
The model is
A display driver model in which the operation of the display driver is described, a display panel model in which the operation of the display panel driven by the display driver is described, and virtually provided between the display driver model and the display panel model Socket model, and
The display driver model is
A gradation voltage generation circuit model that describes the operation of a gradation voltage generation circuit that generates gradation voltages, and a data driver model that describes the operation of a data driver that outputs a data signal based on the generated gradation voltages Including
Serial grayscale voltage data generated by the socket model is input to the data driver model via the grayscale voltage generation circuit model, and serial data from the data driver model is input to the socket model to receive parallel data. A verification simulation method characterized by performing a simulation process of converting data into data and inputting parallel data obtained by the conversion as data signal data to the display panel model. A verification simulation method for performing simulation processing of a device to be verified based on a model in which device operation is described and test input information,
The model is
A display driver model describing the operation of the display driver, and a display panel model describing the operation of the display panel driven by the display driver,
The display driver model is
Includes a data driver model that describes the operation of the data driver that outputs the data signal,
A verification simulation method comprising performing a simulation process for inputting data of an N-bit (N> 2) data signal for each data line from the data driver model to the display panel model.

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