JPH11250116A - Procedure for designing integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a design procedure for automatically correcting a circuit and test pattern data in order to prevent the occurrence of malfunction due to the simultaneous operation of output signals at the time of inspecting before the shipment of an integrated circuit. SOLUTION: In the procedure, simulation 103 is executed by using inspecting test pattern data 102 and the simulated result is collated with terminal arrangement data. Consequently detection for the number of simultaneous operations, grouping 107 for dividing output terminals and correction 108, 109 of a circuit and test pattern data corresponding to the grouping 107 can be easily and automatically executed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for designing an integrated circuit.

[0002]

2. Description of the Related Art Conventionally, as a method of avoiding simultaneous operation at the time of testing an integrated circuit, a method of changing test pattern data, a method of reducing the driving capability of an output buffer only at the time of a test, or a method of connecting a plurality of output terminals to a plurality of output terminals are described. There is a method of dividing into groups and operating sequentially.

[0003]

As a measure for avoiding such simultaneous operation, for example, (1) when the test pattern data is changed, an increase in design man-hours, a delay in development delivery, and the like occur. In some cases, the problem cannot be solved only by changing the test pattern data, and (1 ') a circuit change may be required.

In the method of (2) reducing the driving capability only at the time of the test, the number of output terminals may be increased to exceed the simultaneous operation limit number. In this case, (2 ') circuit change,
(2 ") The group must be divided.
The method of dividing the output terminals into a plurality of groups requires operations such as grouping and creating a control circuit.
An increase in design man-hours, a delay in development delivery date, and the like occur.

[0005] Therefore, an object of the present invention is to link the simulation results with the terminal arrangement information so as to automatically perform grouping, control circuit insertion and test pattern data change operations in order to eliminate these drawbacks. It is to provide a simple integrated circuit design method.

[0006]

According to the integrated circuit designing method of the present invention, a simulation is performed using a plurality of test pattern data for inspecting an integrated circuit, and the number of simultaneous operations of output signals is determined based on the result of the simulation. Means for detecting, means for comparing the number of simultaneous operations with a preset number of simultaneous operations, and detecting, when the number of simultaneous operations exceeds the number of simultaneous operations, an external terminal to be exceeded Means, means for grouping the target external terminals according to the simultaneous operation limit number, means for converting the external connection buffer of the control external terminal into a buffer with a control circuit, and the output state of the target external terminal Means for inserting a control circuit and a control external terminal, and means for adding test pattern data for controlling an output state to test pattern data for inspection It is characterized by having a.

According to a second aspect of the present invention, there is provided a design method in which a part of the above-described means is partially corrected, and the external terminals to be controlled are grouped according to the number of simultaneous operations limited. Rather, means for converting the external connection buffer of the target external terminal into a buffer with a control circuit, a circuit for controlling the output state of the target external terminal, and means for inserting the control external terminal, and output state Means for adding test pattern data for controlling the test pattern data to the test pattern data for inspection.

It is preferable that the insertion position of the test pattern data to be added is immediately after the position where the simultaneous operation limit number of the test pattern data for inspection is exceeded, and
It is also preferable that the number of test patterns used is determined by the number of groupings.

In the method of designing the present integrated circuit,
When the number of simultaneous operations is M and the number of simultaneous operations is N, the group number G is an integer when N / M is an integer.
When / M is not an integer, it is preferably an integer obtained by rounding up a value below the decimal point.

It is preferable that the means for grouping is determined by the terminal arrangement status in the chip layout.

That is, according to the present invention, a simulation is performed using test pattern data, and the number of simultaneous operations of the output signal is detected based on the result. The external terminals to be used are divided into groups, the external connection buffer is converted to an external connection buffer with a control circuit, and a control circuit for controlling the output state and a control external terminal are inserted for each group, and data to be supplied to the control circuit. Is provided to the test pattern data.

[0012] Simultaneous operation limit number is determined by simulation, and simultaneous operation countermeasures are taken in a short time by automatically changing a buffer for external connection, inserting a control circuit, and adding test pattern data. Integrated circuit design becomes possible.

[0013]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a flow chart of an embodiment of an integrated circuit design method according to the present invention, FIG. 2 is a part of a result of a simulation initially executed by the design method of the present embodiment, and FIG. FIG. 4 is a diagram showing the layout of the corresponding terminals in FIG. 3 on the chip layout, and FIG. A part of the circuit diagram before correction, (b) is a part of the circuit diagram after correction, FIG. 6 is a part of test pattern data to be added, and FIG. 7 is a test pattern data to be added is inserted. It is a part of test pattern data for inspection. Hereinafter, the case of claim 2 will be mainly described as an example.

As shown in FIG. 1, first, connection information 101 for which circuit design has been completed, and test pattern data 102 for inspection.
To execute the simulation 103. Next, based on the result of the simulation 103, the number of simultaneous operations compared with the pattern immediately before each pattern is detected, and it is determined whether the number of simultaneous operations does not exceed the allowable value (104).

If the result of the determination is OK, the operation ends (105). On the other hand, in the case of NG, the NG pattern number and the target external terminal are detected (10).
6). Next, the target external terminals are grouped based on the terminal arrangement data (107). Grouping 107
Is completed, modify the circuit to take measures against simultaneous operation.
8 and correction 109 of the test pattern data. The circuit correction 108 changes the external connection buffer 110.
The change 110 of the external connection buffer changes the external connection buffer connected to the external terminal to a buffer with a control circuit for simultaneous operation countermeasures. At this time, only the external connection buffer detected in the simultaneous operation determination is changed.
Next, control circuit and terminal insertion 111 is performed. The control circuit controls the output state of the external buffer and is controlled by data supplied to a control external terminal. Next, the circuit connection 112 is performed. The circuit connection 112 connects the control circuit and the external buffer according to the grouping. This completes the circuit modification 108. On the other hand, pattern correction 109
First, additional test pattern generation 113 is performed. The additional test pattern generation 113 creates test pattern data for the number of group divisions based on the corrected circuit. Next, test pattern insertion 114 is performed. The insertion 114 of the test pattern
Insert immediately after the test pattern that exceeds the simultaneous operation limit.
The generation 113 and the insertion 114 of the test pattern are repeatedly executed in all places where the simultaneous operation limit is exceeded, to obtain final test pattern data. Finally, the operation confirmation 115 is performed by simulation using the corrected circuit and test pattern data, and if there is no problem, the process ends.

Next, a case where the determination result is NG will be described with a specific example.

FIG. 2 shows a part of the result of the first simulation. As shown in FIG.
The number of simultaneous operations in pattern No. 1027 of pattern No. 6 is 7, and the limit number of this integrated circuit is determined to be 3 at this time. Is NG.

FIG. 3 shows the result of detecting terminals operating simultaneously at the 1027th pattern. OUT1,2,3
Four, six, eight, and seven of IO1 are external terminals subjected to simultaneous operation.

FIG. 4 shows the terminal layout on the chip layout and the target terminals divided into three groups based on the terminal layout.

In FIG. 4, the image of the integrated circuit chip is indicated by reference numeral 1 and the serial number given to the external terminal is indicated by reference numeral 2. As shown in FIG. 4, the grouping is performed by dividing the number of simultaneous operations N by the allowable value M based on the terminal arrangement data on the chip layout.
In this case, since the number of simultaneous operations is 7 and the allowable value is 3, the target terminal is divided into three groups A, B, and C. The division is performed according to the serial number 2 indicating the terminal arrangement information, and groups A, B, and C in ascending order of the numbers. As a result, group A is OUT1, OUT4 and IO1, and group B is O
UT2, OUT6, and group C are OUT3, OUT8.

FIG. 5A shows a part of the circuit diagram before the correction is performed, and FIG. 5B shows a part of the circuit diagram after the circuit correction is performed. FIGS. 5A and 5B show logic circuit blocks 11 and 12. The output buffer 13, the 3-state output buffer 14, and the input / output buffer 15 shown in FIG. 5A are changed to buffers with control circuits in FIG. 5B, respectively.
15a. The external terminals OUT4, OUT1, and IO1 in FIGS. 5A and 5B are denoted by reference numerals 16, 17, and 18, respectively. Output control circuit 1
9 is for controlling the output state of the buffers 13a, 14a and 15a. Control external input terminal CONT
1 and CONT2 are indicated by reference numerals 20a and 20b, respectively. The control terminals 13b, 14b, 15b of the output buffers 13a, 14a, 15a are connected to the terminals D, E, F of the output control circuit 19 in accordance with the grouping.

FIG. 6 shows additional test pattern data corresponding to a circuit changed according to the grouping. FIG.
As shown in the figure, the additional pattern is the same as the number of divisions, ie, three patterns. Control terminals CONT1 and CONT2 are added, and the buffer state is changed from the high impedance (Z) state to the normal operation state in order to measure the groups A, B and C in this order. Mode (0)
Has been changed. Also, the input / output buffers 13a, 13
b and 13c are changed from the high impedance state to the output state by changing the input state and the output buffer to the high impedance state and setting the output state at the time of measurement. The pattern numbers at this time are 1027 ', 1028', and 1029.

FIG. 7 shows test pattern data for inspection whose correction has been completed. FIG. 7 shows a pattern obtained by adding the pattern shown in FIG. 6 to the pattern shown in FIG.
26, the conventional pattern 1027 is deleted, the pattern 1028 is changed to the pattern 1030, and the subsequent patterns are shifted by two patterns. The signals of CNT1 and CNT2 other than the additional pattern are always fixed to the normal operation state (0, 0).

Finally, a simulation is executed based on the changed circuit and test pattern data to confirm that there is no problem, and the flow ends.

As described above, the simulation is performed, and the result is linked to the terminal arrangement data, whereby the system can be formed by CAD, and the generation and change of the control circuit and additional test pattern data can be easily automated. .

[0027]

As described above, according to the present invention, the number of simultaneous operations is detected by simulation, the circuit of the limiting external terminal or the external terminal which has become NG is changed, and the test pattern data is added. In addition, it is possible to minimize the increase of circuits and patterns, and also to take simulations and terminal arrangement data, so that automation can be easily performed, so that simultaneous countermeasures can be performed in a short time without bothering people. There is an effect that it is possible to provide a design method of an integrated circuit subjected to the above.

[Brief description of the drawings]

FIG. 1 is a flowchart of an embodiment of an integrated circuit design method according to the present invention.

FIG. 2 is a part of a result of a simulation first executed by the design method according to the embodiment;

FIG. 3 is a diagram showing a detection result of a pattern and a corresponding terminal that exceed a simultaneous operation restriction allowable value based on a result of the simulation of FIG.

FIG. 4 is an arrangement image of a corresponding terminal in FIG. 3 on a chip layout.

FIG. 5A is a part of a circuit diagram before correction, and FIG. 5B is a part of a circuit diagram after correction.

FIG. 6 shows a part of test pattern data to be added.

FIG. 7 shows a part of test pattern data for inspection into which test pattern data to be added is inserted.

[Explanation of symbols]

 Reference Signs List 1 integrated circuit chip 2 serial number 11, 12 logic circuit block 13 output buffer 13a output buffer with control circuit 13b, 14b, 15b control terminal 14 three-state output buffer 14a three-state output buffer with control circuit 15 input / output buffer 15a control circuit Input / output buffer 16, 17, 18 External terminal 19 Output control circuit 20a, b External input terminal for control 101 Circuit connection information 102 Test pattern data for inspection 103 Simulation 104 Simultaneous operation determination 105 End 106 Applicable pattern and external terminal detection 107 External Terminal grouping 108 Circuit correction 109 Pattern correction 110 External buffer change 111 Control circuit and terminal insertion 112 Circuit connection 113 Additional test pattern generation 114 Test pattern insertion 115 Operation check

Claims (6)

[Claims] In an integrated circuit design method, a simulation is performed using a plurality of test pattern data to check the operation of each output terminal of an integrated circuit, and the number of simultaneous operations of output signals is determined based on a result of the simulation. Means for detecting, means for comparing the number of simultaneous operations with a preset number of simultaneous operations, and when the number of simultaneous operations exceeds the number of simultaneous operations,
Means for detecting the external terminals to be exceeded, means for grouping the external terminals to be subjected to the simultaneous operation limit number, and means for converting the external connection buffer of the control external terminal into a buffer with a control circuit. A circuit for controlling an output state of the target external terminal and a unit for inserting the control external terminal; and a unit for adding test pattern data for controlling the output state to the test pattern data for inspection. And a method for designing an integrated circuit. 2. A method for designing an integrated circuit, comprising: performing a simulation using a plurality of test pattern data in order to check the operation of each output terminal of the integrated circuit; and determining the number of simultaneous operations of output signals based on the simulation result. Means for detecting, means for comparing the number of simultaneous operations with a preset number of simultaneous operations, and when the number of simultaneous operations exceeds the number of simultaneous operations,
Means for detecting the external terminal to be exceeded, means for grouping the external terminals to be subjected to the simultaneous operation limit number, and conversion of the external connection buffer of the external terminal to a buffer with a control circuit. Means for controlling the output state of the target external terminal; means for inserting the control external terminal; and adding test pattern data for controlling the output state to the test pattern data for inspection. Means for designing an integrated circuit. 3. The integrated circuit design method according to claim 1, wherein the insertion position of the added test pattern data is immediately after a position where the simultaneous operation limit number of the test pattern data for inspection is exceeded. 4. The integrated circuit design method according to claim 1, wherein the number of test patterns used is determined by the number of groupings. 5. When the number of simultaneous operations is M and the number of simultaneous operations is N, the number of groups G is an integer when N / M is an integer. When N / M is not an integer, the number of groups is less than the decimal point. 3. The integrated circuit design method according to claim 1, wherein the integrated circuit is determined by rounding up. 6. The integrated circuit design method according to claim 1, wherein said grouping means is determined by a terminal arrangement state in a chip layout.