JP3548922B2 - Circuit design method using boundary scan dummy cells - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a circuit design method using a boundary scan dummy cell, and more particularly to a boundary scan device insertion when designing an integrated circuit.
[0002]
[Prior art]
The boundary scan is described in "HP Boundary Scan Technical Document and BSDL Reference Guide" (May 1991) in Yokogawa Hewlett-Packard. Boundary scan is a test technology for a device designed so that a boundary scan register is arranged in a shift register structure between an external interface and an internal logic circuit, and is standardized by IEEE Standard 1149.1-1990. Have been.
[0003]
FIG. 2 is a schematic diagram of an integrated circuit in which main devices used for boundary scanning are arranged. Reference numeral 21 denotes an internal logic, which is a core of the integrated circuit. Reference numerals 22 and 23 denote input pins and output pins, respectively, which are external terminals. Reference numeral 24 denotes a boundary scan register which is inserted between the input pin 22 and the output pin 23 and the internal logic 21 and is used for controlling and observing the input pin 22 and the output pin 23. The TAP controller 25 receives a clock signal (TCK), a reset signal (TRST), and the like, and performs device control and the like. Reference numeral 26 denotes an instruction register, which causes a device to execute a function. The IDCODE register 27 identifies a device and a manufacturer. The bypass register 28 minimizes the distance from the scan input to the output. What is most important here is a boundary scan register inserted between an external terminal pin and internal logic.
[0004]
Normally, these devices are inserted after a logic simulation of the internal logic is performed after the completion of the internal logic design and it is confirmed that the design is as designed. Thereafter, a circuit check is performed, and for a circuit in which a failure has occurred, the circuit design is started again.
[0005]
[Problems to be solved by the invention]
In the conventional integrated circuit design as described above, after verifying the internal logic of the integrated circuit by logic simulation, the work of inserting the boundary scan circuit is performed, so that the characteristics of the boundary scan register are not considered. When the internal logic is designed, a delay due to the boundary scan register may cause a problem in the subsequent pseudo wiring simulation or actual wiring simulation. In addition, at the insertion point of the boundary scan register, FAN OUT over due to excess drive gates may occur, resulting in an error. Further, since the CAD tool used to insert the boundary scan device is a dedicated tool, unlike a general CAD, it cannot be easily handled by a designer, and furthermore, it is necessary to insert the device. Long execution time.
[0006]
Due to the problems described above, every time the design of the internal logic is reconsidered, the boundary scan device must be inserted by the dedicated CAD, which consumes a lot of time and shortens the design time. Had a problem of inefficiency.
[0007]
Therefore, in order to reduce the circuit design time, there has been a demand for a circuit design method that can reduce the number of times of performing the boundary scan device insertion by the dedicated CAD.
[0008]
[Means for Solving the Problems]
Circuit design method using the boundary scan dummy cell according to the present invention, the internal logic circuit and a circuit design step for designing a composed integrated circuit and boundary scan dummy cell comprised of an interface means and the boundary scan register Performing a predetermined test on the integrated circuit and, if the predetermined requirements are not satisfied, re-designing the integrated circuit again in the circuit design process.If the predetermined requirements are satisfied, the boundary scan dummy cell is Replacing the interface means with a boundary scan device including a boundary scan register when the requirement is satisfied. The process of designing a circuit composed of an internal logic circuit and a boundary scan dummy cell is repeated until a predetermined requirement is satisfied. After the requirements are satisfied, a step of replacing the boundary scan dummy cell with the interface means and the boundary scan device is performed. Therefore, it is not necessary to replace the boundary scan device every time an integrated circuit is designed, and the time is reduced.
[0009]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a flowchart of a circuit design method using a boundary scan dummy cell according to an embodiment of the present invention. The operation of the present embodiment will be described based on FIG. First, a design of an internal logic and a function verification pattern used for performing a logic simulation of the internal logic are performed (S101).
[0010]
When the internal logic is designed, an input buffer 2, an output buffer 5 or an input / output buffer 8 as shown in FIG. 3 is usually inserted, but on a general CAD, these buffers are replaced with an input boundary. The scan dummy cell 1, the output boundary scan dummy cell 4 or the input / output boundary scan dummy cell 7 are temporarily inserted (S102). When the above-described boundary scan dummy cells are collectively referred to, they are simply referred to as boundary scan dummy cells 1, 4, and 7.
[0011]
FIG. 3 is a configuration diagram of the buffer and the boundary scan dummy cell according to the embodiment of the present invention. The input boundary scan dummy cell 1 inserted on the input side as shown in FIG. 1A is one in which the boundary scan register 3 is connected to the output side of the input buffer 2. The output boundary scan dummy cell 4 inserted into the output as shown in FIG. 4B is one in which the boundary scan register 6 is connected to the input side of the output buffer 5. Further, the input / output boundary scan dummy cell 7 shown in (c) is one in which boundary scan registers 9, 10 and 11 are connected to the input side, output side and control side of the input / output buffer 8, respectively. . Therefore, the boundary scan dummy cell takes into account the delay time of the boundary scan register and the number of FAN OUTs, and is actually created rather than inserting the input buffer 2, output buffer 5, and input / output buffer 8. The integrated circuit and the input / output unit of the internal logic are equivalent.
[0012]
Actually, the input buffer 2, the output buffer 5, and the input / output buffer 8 are automatically converted into the input boundary scan dummy cell 1, the output boundary scan dummy cell 4, and the input / output boundary scan dummy cell 7, respectively. By registering them as macros in advance, designers can use these buffers with the same feeling as those conventionally used. If the logic function of the design circuit is input and the design is made using a logic synthesis tool that creates a circuit diagram corresponding to the logic function, the buffer name on the netlist is changed to the boundary scan dummy cell name, and the boundary When the scan dummy cells 1, 4, and 7 are combined, a circuit including the boundary scan dummy cells is generated.
[0013]
When the temporary insertion of the boundary scan dummy cells 1, 4, and 7 is completed, a circuit design criterion check is performed to check whether there is any circuit failure (S103). The circuit design standard check is a program for reading a circuit diagram and checking whether or not the circuit design is correctly performed. If a defect is found in the circuit design standard check, the circuit design is reviewed again. When a FAN OUT error occurs in the insertion portion of the boundary scan dummy cells 1, 4, and 7, a driver cell for preventing FAN OUT over is inserted into the output side of the boundary scan dummy cell, This is addressed by increasing the number of gates that can be driven. When designing using a logic synthesis tool, the logic is optimized at the time of temporarily inserting the boundary scan dummy cells 1, 4, and 7, so that the boundary scan dummy cells 1, 4, and 7 are optimized. Has no problems.
[0014]
If there is no problem in the circuit design standard check, a logic simulation is performed to verify whether the desired logic has been correctly created for the internal logic using the created function verification pattern (S104). . In the logic simulation, if an error occurs due to the influence of the boundary scan dummy cells 1, 4, and 7, the circuit design and the function verification pattern design are modified to make the design such that the boundary scan dummy cell does not affect the design. Is performed, and the circuit design standard check and the logic simulation are performed again.
[0015]
If no problem occurs in the logic simulation, the roles of the boundary scan dummy cells 1, 4, and 7 are completed. Next, in order to permanently insert another device including the boundary scan register by dedicated CAD, the boundary scan dummy cell is deleted (S105), and the input buffer 2, output buffer 5, and input buffer 5 which are normally inserted are deleted. Replace with output buffer 8.
[0016]
Using the dedicated CAD tool, the device used for the boundary scan as shown in FIG. 2 is permanently inserted into the circuit from which the boundary scan dummy cells 1, 4, and 7 have been deleted (S106). The circuit design reference check is performed again on the circuit after the main insertion (S107). If a problem occurs, the circuit design and the function verification pattern design are repeated. If no problem occurs in the circuit after the main insertion, the boundary scan application process is completed, and the process proceeds to a process such as a wiring simulation (S108).
[0017]
As described above, in the present embodiment, the boundary scan dummy cells 1, 4, and 7 in which the delay time by the boundary scan registers 2, 5, or 8 and the FAN OUT are added are inserted in advance by general CAD. In addition, since a logic simulation of the internal logic is performed to solve the problem and then the actual insertion of the device by the dedicated CAD is performed, the number of times of using the dedicated CAD which requires a long execution time is reduced, and the circuit design time can be reduced. .
[0018]
In the above-described embodiment, the use on CAD is illustrated, but the present invention is not limited to this, and can be used in other circuit designs.
[0019]
【The invention's effect】
As described above, according to the present invention, a predetermined inspection is performed on an integrated circuit by using a boundary scan dummy cell, and the boundary scan dummy cell of the integrated circuit that satisfies predetermined requirements is interfaced with: Since the boundary scan device is used, it is not necessary to replace the integrated circuit every time the integrated circuit is redesigned, so that the integrated circuit design time can be shortened.
[Brief description of the drawings]
FIG. 1 is a flowchart of a circuit design method using a boundary scan dummy cell according to an embodiment of the present invention.
FIG. 2 is a schematic diagram of a circuit in which devices for main boundary scan are arranged.
FIG. 3 is a configuration diagram of a buffer and a boundary scan dummy cell according to the embodiment of the present invention.
[Explanation of symbols]
1 Input Boundary Scan Dummy Cell 2 Input Buffer 3, 6, 9, 10, 11, 24 Boundary Scan Register 4 Output Boundary Scan Dummy Cell 5 Output Buffer 7 I / O Boundary Scan Dummy Cell 8 I / O Buffer 21 Logic 22 Input pin 23 Output pin 25 TAP controller 26 Instruction register 27 IDCODE register 28 Bypass register

Claims (2)

An internal logic circuit, and a circuit design step for designing a composed integrated circuit and boundary scan dummy cell comprised of an interface means and the boundary scan register,
Performing a predetermined test on the integrated circuit, when the predetermined requirements are not satisfied, a step of redesigning the integrated circuit in the circuit design step;
Replacing the boundary scan dummy cell with an interface means and a boundary scan device including a boundary scan register when the requirement is satisfied, if the predetermined requirement is satisfied. Circuit design method using boundary scan dummy cells. 2. The circuit according to claim 1, wherein said boundary scan dummy cells corresponding to said interface means are registered in advance, and said interface means is automatically replaced with said boundary scan dummy cells in said circuit designing step. 2. A circuit design method using the boundary scan dummy cell according to 1.

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