JP2774396B2 - Data generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data generator, and more particularly, to a data generator for a test apparatus suitable for use in the field of semiconductor device testing.
In recent years, for example, LSI (Large Scale Integratedcircui
t) and other large-scale integrated circuits, RAM (Rando
m Access Memory), ROM (Read Only Memory), C
In many cases, the design is performed by incorporating a functional block such as a PU (Central Processing Unit) core portion and a multiplier.

As the circuit scale of an integrated circuit increases, it is becoming very difficult to test each of these functional blocks, such as a test for determining the presence or absence of an internal failure. A circuit design for easily performing a test becomes indispensable. However, circuit design for facilitating testing requires special knowledge and a great deal of effort, and even if a circuit is designed in consideration of testing, test data for testing the circuit is required. Creating requires a great deal of effort and time.

Therefore, in order to develop a test automation device, it is necessary to easily create test data.

[0004]

2. Description of the Related Art Conventionally, as a method of facilitating a test in a semiconductor integrated circuit, a method of designing a circuit in consideration of a test is generally used. In this method, a circuit designer designs a circuit in consideration of a test on a semiconductor integrated circuit in advance.

[0005]

However, in such a conventional technique for facilitating the test of a semiconductor integrated circuit, a circuit designer for facilitating the test has been designed by a circuit designer. There was such a problem.
That is, a circuit design for facilitating the test requires special knowledge and a large amount of labor, so that a great burden is imposed on the circuit designer.

[0006] Further, even with a circuit designed with such a heavy burden, test data for testing must be created this time, and it takes a great deal of labor and time to create test data. I need. Therefore, it is not only difficult to realize the test easily in a large-scale integrated circuit, but also a great burden is imposed on a designer.
In many cases, circuit design is not made in consideration of facilitation of testing.

Further, in a scan circuit design which is generally widely used, the circuit scale tends to be large, and a test is performed in synchronization with a predetermined clock, so that many problems such as inapplicability to an asynchronous circuit and a memory element are encountered. I have. [Purpose] Accordingly, an object of the present invention is to provide a data generation apparatus for easily creating test data.

[0008]

Means for Solving the Problems To achieve the above object,
Therefore, the invention according to claim 1 provides an operation of a semiconductor integrated circuit.
Data generation that generates data for test circuits that make decisions
Device, a flip-flop in the semiconductor integrated circuit
Processing for replacing flip-flops with scan flip-flops
Means and functional blocks with specific functions for testing only
Second process of replacing the function block with another functional block
Processing means; the first processing means and the second processing means;
Generates test data based on test circuit information
And a third processing means, wherein the second processing means
Generates data for external pins for functional block test circuits
External pin automatic generation means for functional block test circuit
And I / O to the external pin for the block test circuit.
Functional block test circuit for inserting or replacing buffers
I / O macro generation means and a function block having a predetermined function.
The lock has the same function as the functional block, and
Replace with other functional blocks that have dedicated pins
Processing target functional block test terminal generation processing means;
Replaced function block and said inserted or replaced
Function block for performing connection processing with I / O buffer-I / O
O-macro connection processing means for the block test circuit
Between an external pin and the inserted or replaced I / O buffer
External pin -I for functional block test circuit that performs connection processing
/ O macro connection processing means.
I have. The invention described in claim 2 is the invention described in claim 1.
In the data generation device of the above, the first processing means may
Scan circuit that generates data for external pins for the scan circuit
Means for automatically generating external pins for scanning, and external pins for scanning circuits.
To insert or replace I / O buffers
I / O macro generation means for scan circuit and flip in circuit
Replace flops with scan flip-flops
Flip-flop insertion processing means;
Scan flip-flops or existing switches in the circuit
Can flip-flop and the inserted or replaced I /
Connection with O-buffer and the replaced or
Connection processing between existing scan flip-flops in the road
Flip-flop and I / O macro connection
Processing means, the external pins for the scan circuit and the insertion or
Scan for performing connection processing with the I / O buffer that is substituted
Connection circuit external pin and I / O macro connection processing means.
It is characterized by having.

[0009]

According to the present invention, a flip-flop (hereinafter referred to as a flip-flop)
FF) is replaced by a scan FF.
And a functional block having a predetermined function.
It has the same function as the lock, and retains the dedicated test pin.
Second processing means for replacing with another functional block having
Function without test pins
Place the block on a functional block that has dedicated test pins.
In other words, the function block is tested. Therefore,
The labor and time required to create test data are saved,
Data can be easily created.
Functional blocks of the entire chip or specific devices
Function blocks can be tested.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing an embodiment of a data generation device according to the present invention, and is a block diagram showing a schematic configuration thereof. First, the configuration will be described.

The data generating apparatus 1 of the present embodiment is roughly divided into a first processing means, ie, a scan circuit generating section 2 and a second processing section.
Function block test circuit generating unit 3
3, a test data automatic generation unit 4, which is a processing means,
Storage device 5 . Scan circuit generator 2
2, a scan circuit external pin definition automatic generation unit 6, a scan circuit generation control unit 7, and a scan circuit
External pin for scan circuit, which is an automatic external pin generation means
The automatic generation unit 8 is a scan circuit I / O macro generation unit.
A certain scan circuit I / O macro generator 9, scan F
The scan FF insertion processing unit 10, which is an F insertion processing unit,
Scan FF-I / O macro connection processing means
FF-I / O macro connection processing unit 11, scan circuit
It comprises a scanning circuit external pin-I / O macro connection processing unit 12 and a scan circuit information output unit 13 which are external pin-I / O macro connection processing means .

Automatic external pin definition generator 6 for scan circuit
Is used to determine which external pin is used as an external pin for the scan circuit and output the external pin definition data for the scan circuit. When the external pin for the scan circuit is determined, an LSI package to be used in advance is used. It is also possible to determine the position of the pin for each type. In this case, the external pins for the scan circuit are determined by inputting the position information of the external pins for the scan circuit for each package, but this external pin definition for the scan circuit must be generated not only automatically but also manually. Is also possible.

The scan circuit generation control unit 7 controls each processing unit for generating a scan circuit based on the scan circuit external pin definition, logic data, and library data generated by the scan circuit external pin definition automatic generation unit 6. It controls the operation. Automatic generation of external pins for scan circuit
The forming unit 8 generates data of the scan circuit external pins based on the definition of the scan circuit external pins.

The scan circuit I / O macro generation unit 9
It inserts and replaces an I / O buffer connected to the external pin generated by the scan circuit external pin automatic generation unit 8 . The scan FF insertion processing unit 10 replaces an existing FF in the circuit with a scan FF.

The scan FF-I / O macro connection processing section 11 converts the scan FF replaced by the scan FF insertion processing section 10 and the existing scan FF in the logical data into an I / O macro generation section 9 for a scan circuit. The connection processing of the I / O buffer processed by the above is performed. At this time, the buffer is inserted so that the signal is transmitted correctly.

The scan circuit external pin-I / O macro connection processing unit 12 includes a scan circuit external pin automatic generation unit.
The connection processing of the external pins processed in step 8 and the I / O buffer processed in the scan circuit I / O macro generation unit 9 is performed. The scan circuit information output unit 13 generates a signal line for transmitting a scan signal to the scan FF that has been processed by the scan FF-I / O macro connection processing unit 11. It outputs various circuit information to test circuit information.

[0017] By the way, the library data, scan
External pin automatic generation unit 8 for scan circuit, I / O for scan circuit
Each processing of the macro generation unit 9, the scan FF insertion processing unit 10, the scan FF-I / O macro connection processing unit 11, the scan circuit external pin-I / O macro connection processing unit 12, and the scan circuit information output unit 13 Describes the required rules.

The connection from the external pin of the functional block to the external pin of the chip is processed by the following functional block test circuit generator 3. As shown in FIG. 3, the function block test circuit generation unit 3 includes a function block test circuit external pin definition automatic generation unit 14, a function block test circuit generation control unit 15, and a function block test circuit external pin automatic
External pin automatic for the function block test circuit which is the generation means
Generator 16, I / O macro for functional block test circuit
I / O macro for functional block test circuit
Component 17, processing target functional block test terminal generation processing
Target functional block test terminal generation processing unit 1
8. Function block-I / O macro connection processing means
Function block-I / O macro connection processing section 19, function block
Connection processing between external pin for lock test circuit and I / O macro
External pin-I / O for functional block test circuit as means
It comprises an inter-macro connection processing unit 20 and a functional block test circuit information output unit 21.

The function block test circuit external pin definition automatic generation unit 14 determines which external pin is to be used as the function block test circuit external pin, and outputs the function block test circuit external pin definition. Thus, the external pin definition for the functional block test circuit can be generated not only automatically but also manually.

Functional block test circuit generation controller 15
Is a function block test circuit external pin automatic generation unit 14
The operation of each processing section for generating a functional block test circuit is controlled based on the external pin definition for the functional block test circuit generated by the above. The function block test circuit external pin automatic generation unit 16 generates function block test circuit external pin data based on the function block test circuit external pin definition.

The function block test circuit I / O macro generator 17 is an I / O connected to the external pin generated by the function block test circuit external pin automatic generator 16.
The buffer is inserted and replaced. The processing target functional block test terminal generation processing unit 18 performs a replacement process on the functional block to be processed.

The functional block-I / O macro connection processing section 19 is a processing block for generating a function block test terminal to be processed.
The connection processing is performed between the dedicated test pin of the functional block processed in step 8 and the I / O buffer processed by the functional block test circuit I / O macro generation unit 17. At this time, the signal is transmitted correctly. In this way, a buffer is inserted, and a functional block control circuit for independently testing a functional block is inserted.

External pin -I /
The O-macro inter-connection processing unit 20 performs a connection process between the external pins generated by the function block test circuit external pin automatic generation unit 16 and the I / O buffer generated by the function block test circuit I / O macro generation unit 17. Things. The functional block test circuit information output unit 21 outputs various types of information of the generated functional block test circuit to test circuit information.

Incidentally, the library data includes an external pin automatic generation unit 16 for a function block test circuit, an I / O macro generation unit 17 for a function block test circuit, a function block test terminal generation processing unit 18 to be processed, a function block
Rules necessary for the processing of the I / O macro connection processing unit 19 are described. That is, the functional block test circuit generation unit 3 inputs the logic information and the test circuit information when the test circuit information already exists, thereby obtaining information necessary for connecting each functional block to an external pin. Is extracted and a connection is made.

As shown in FIG. 4, the automatic test data generation unit 4 includes an automatic scan circuit test pattern generation unit 22,
It comprises a test pattern synthesis unit 23 and a function block test circuit automatic generation unit 24. The automatic scan circuit test pattern generation unit 22 includes a scan circuit automatic generation unit 2.
, A test pattern is automatically generated for a circuit that has been processed and a scan circuit that has been manually scanned and designed, and is output as test data.

The test pattern synthesizing unit 23 performs, for each of the functional blocks in which the unit test pattern is registered, the functional block of the random logic circuit among the functional blocks processed by the functional block test circuit generating unit 3. A test data library and test circuit information are input, automatically synthesized into test data for testing from external pins of the LSI, and the synthesized data is output as test data.

Function block test circuit automatic generation unit 24
Is for automatically generating and outputting test data to a memory functional block such as a RAM or a ROM. The scan circuit test pattern automatic generation unit 22, test pattern synthesis unit 23, and function block test circuit automatic generation unit 24 operate independently of each other. That is, the test data automatic generation unit 4 inputs the test circuit information output from the scan circuit generation unit 2 or the function block test circuit generation unit 3, and based on the information, the test data for each functional block and the circuit In addition to inputting test data for function verification of the above, the data is re-synthesized into test data corresponding to the automatically generated circuit and output, that is, logical data, test circuit information, test data for each functional block, By inputting test data for verifying the function of a designed circuit, completed test data corresponding to the generated test circuit is generated.

Next, the operation will be described. FIG. 5 is a block diagram for explaining an operation example of the present embodiment . In this case, only a certain one functional block is targeted for scan circuit generation. 25 is a compiled cell, 26 is R
AM / ROM, 27 is a CPU core, 28 is other functional blocks, and 29 is an I / O buffer.

First, the scan circuit generation control unit 7
Scan circuit external pin automatic generation unit 8 , scan circuit I / O macro generation unit 9, scan circuit external pin -I /
The respective processes of the O-macro connection processing unit 12 are not performed, and the scan FF-I / O inter-macro connection processing unit 11 performs connection processing up to the external pins of the target functional block.
Thereafter, the above-described processing is performed by the functional block test circuit generator 3 on the functional blocks processed by the scan circuit generator 2.

[0030] Thus in treated versus scan circuit generator 2
The test circuit of the functional block that has become the elephant is completed, and the scan circuit and the functional block test circuit are generated.
In this case, even if the processing is performed by operating both the scan circuit generation unit 2 and the functional block test circuit generation unit 3,
The process may be performed by operating only one of them.

The connection between each functional block and the external pins of the chip is performed in parallel, and to which functional block the signal is supplied is selected by the selection signal output from the functional block test circuit generation control unit 15 described above. Is performed. As described above, in the present embodiment, since the test design of the integrated circuit is automatically performed, the circuit designer can concentrate on the logical design of the function, and can realize an efficient design environment.

Further, at the time of testing, each functional block can be directly controlled from external pins of the chip, so that the test time is shortened and a detailed test can be performed. In addition,
The scan circuit generation unit 2 of the above embodiment generates a scan circuit for a designated function block according to a conventional method. In this case, the entire chip is set as a scan circuit generation target or a certain function block is generated. It is possible to select whether to target only inside.

When a scan circuit is generated not for the entire chip but only for a certain functional block, the connection to the external pins of the functional block may be performed without connecting to the external pins of the chip. It is possible.

[0034]

According to the present invention, the FF in the circuit is scanned F
A first processing unit to be replaced with F and a predetermined function
The function block has the same function as the function block, and
Place it on another functional block that has dedicated test pins.
With the second processing means for replacing, the test pins are held
Function blocks that do not have dedicated test pins
Replace with a lock and test the function block
The time and effort required to create test data
Can be omitted and test data can be easily created.
With a simple test circuit configuration,
Can test specific functional blocks.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a data generation device according to the present invention.

FIG. 2 is a block diagram illustrating a schematic configuration of a scan circuit generation unit.

FIG. 3 is a block diagram illustrating a schematic configuration of a functional block test circuit generator.

FIG. 4 is a block diagram illustrating a schematic configuration of a test data automatic generation unit.

FIG. 5 is a block diagram for explaining an operation example of the embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Data generation apparatus 2 Scan circuit generation part (1st processing means) 3 Function block test circuit generation part (2nd processing
4 ) Automatic test data generation section (third processing means) 5 External storage device 6 Automatic pin definition external generation section for scan circuit 7 Scan circuit generation control section 8 Automatic external pin generation section for scan circuit 9 I / O for scan circuit O macro generation unit 10 Scan flip-flop insertion processing unit 11 Scan FF-I / O macro connection processing unit 12 Scan circuit external pin-I / O macro connection processing unit 13 Scan circuit information output unit 14 For functional block test circuit External pin definition automatic generation unit 15 Function block test circuit generation control unit 16 External pin automatic generation unit for function block test circuit 17 I / O macro generation unit for function block test circuit 18 Function block test terminal generation processing unit for processing 19 Function block -I / O macro connection processing unit 20 External for functional block test circuit Connection section between I / O macros 21 functional block test circuit information output section 22 automatic scan circuit test pattern generation section 23 test pattern synthesis section 24 automatic function block test circuit generation section 25 compiled cell 26 RAM / ROM 27 CPU core 28 Other function blocks 29 I / O buffer

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-3-4186 (JP, A) JP-A-5-26984 (JP, A) JP-A-3-81871 (JP, A) JP-A-1- 302850 (JP, A) (58) Field surveyed (Int. Cl. ⁶ , DB name) G01R 31/28 G06F 11/22

Claims (2)

(57) [Claims] 1. A test for judging the operation of a semiconductor integrated circuit.
In a data generation device for generating data for a circuit, a flip-flop in the semiconductor integrated circuit is scanned and scanned.
The first processing means for replacing the flip-flop and a functional block having a predetermined function are provided with dedicated test pins.
Second processing means for replacing with another functional block having
When, with the first processing means and said second processing means outputs
Third Test Data Creation Based on Test Circuit Information
Processing means, wherein the second processing means generates data of an external pin for a functional block test circuit.
A functional block test external pin automatic generation unit circuit, I / O buffer to an external pin the block test circuit
I for functional block test circuits that insert or replace files
/ O macro generation means and a function block having a predetermined function
Other functions that have the same function and have dedicated test pins
Function block test to be replaced with function block
Terminal generation processing means, the replaced functional block and the inserted or replaced
Function block for performing connection processing with the I / O buffer-
I / O macro connection processing means, the block test circuit external pins and the insertion or replacement
Block that performs connection processing with the I / O buffer
A data generating device comprising: an external pin for test circuit-I / O macro connection processing means . 2. The scanning circuit according to claim 1, wherein said first processing means generates data of an external pin for a scanning circuit.
A path external pin automatic generation unit, and an I / O buffer for the scan circuit external pin.
I / O macro generation for scan circuit that inserts or replaces data
Means for scanning flip-flops in a circuit
Scan flip-flop insertion processing means
And the replaced scan flip-flop or circuit.
The existing scan flip-flop and the insertion or
Connection processing with the replaced I / O buffer and the replacement
Scan flip-flops obtained or existing in the circuit
Scan flip-flop -I /
O macro connection processing means, the scan circuit external pin and the inserted or replaced
External for scan circuit that performs connection processing with I / O buffer
2. The data generation apparatus according to claim 1 , further comprising a pin-I / O macro connection processing unit.
apparatus.