JP2624151B2 - Scan path design device and scan path test device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scan path designing apparatus and a test apparatus, and more particularly to a boundary scan path designing apparatus associated with an external terminal of an integrated circuit.

[0002]

2. Description of the Related Art When a package configured by mounting an integrated circuit such as an LSI on a substrate fails, the failed L
The SI must be identified and replaced with a new one.
In general, a function for inspecting the LSI itself is provided inside the LSI in order to easily identify the failed LSI.

As one of the inspection functions, a flip-flop (FF) for holding an input / output signal to each external terminal (input / output terminal) of the LSI is provided in the LSI at a design stage, and each FF forms a scan path. Known boundary scan paths are known. In this method, a scan path is formed by connecting adjacent FFs that hold an input signal from an input terminal of an LSI and FFs that hold an output signal to an output terminal. Then, as shown in FIG. 10, if a scan path is formed by all the LSIs 1 to 6, the test pattern applied to the scan-in terminal SIN is derived from the scan-out terminal SOUT and analyzed, whereby each LSI is analyzed. By performing an operation test, a failed LSI can be specified.

Conventionally, the scan path is designed at the same time as the logical design of the LSI, or scan path order information indicating the order of the scan paths is created and the CAD tool is used based on this information.

By the way, when testing the LSI itself,
Conventionally, a test pattern for a test is created and the test is performed using the test pattern.

[0006]

Generally, a boundary scan path is designed by providing FFs corresponding to each external terminal and cascade-connecting two FFs corresponding to adjacent external terminals. . Therefore, the design cannot be performed without considering the arrangement information (layout) of each external terminal of the semiconductor package. However, the arrangement of each external terminal is determined only when the chip is created based on the logic circuit.After the arrangement of each external terminal is determined, the boundary scan path must be designed. There was a disadvantage that it was complicated and time-consuming.

When a scan path is created at the stage of designing a logic circuit, an F which constitutes the scan path is used.
There is a drawback in that an incorrect connection order of F or a design error due to a connection omission occurs, which causes a significant reduction in the quality of LSI logical design.

On the other hand, even when a scan path is automatically designed by a CAD tool, it is necessary to create scan path order information indicating the order of the scan paths at the stage of designing a logic circuit. However, since the scan path order information is also manually created, there is a disadvantage that the validity of the scan path order based on the created information needs to be verified by some method.

Conventionally, a test pattern for a test is created and a test is performed using the test pattern. Therefore, a test pattern must be created, and it is desired to provide a more efficient test procedure. .

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional disadvantages, and an object of the present invention is to provide a scan path designing apparatus capable of automatically designing a scan path.

Another object of the present invention is to provide a scan path test apparatus capable of simplifying an LSI test operation.

[0012]

A scan path designing apparatus according to the present invention comprises N external terminals (N is an integer of 2 or more, the same applies hereinafter), and corresponding terminals provided corresponding to the N external terminals. In a semiconductor package including N holding circuits for holding signals input / output to / from, and a wiring connected between these circuits and terminals, a scan path in which the N holding circuits are cascade-connected is referred to as a scan path. A scan path designing apparatus for designing, wherein a means for holding external terminal arrangement information indicating an arrangement of each external terminal in the semiconductor package,
A first name indicating a wiring name connected to the N external terminals;
Means for holding wiring information, and wiring names connected to input / output terminals of a holding circuit provided corresponding to the N external terminals and holding signals input / output to / from the corresponding terminals. Means for holding the second wiring information and first and second holding circuits corresponding to the two external terminals indicated to be adjacent by the second wiring information and the external terminal arrangement information. An output terminal of the holding circuit and the second terminal;
And a wiring name determining means for giving the same wiring name to the wirings respectively connected to the input terminals of the holding circuits, and a wiring name giving operation by the wiring name determining means so as to be performed for all of the N holding circuits. And control means.

A scan path test apparatus according to the present invention includes an internal circuit having a predetermined function, and N circuits (N is an integer of 2 or more,
The same applies to the following), N holding circuits provided corresponding to the N external terminals and holding signals input / output to / from the corresponding terminals, and wiring connected between these circuits and the terminals. A scan path test apparatus that performs a function test of the internal circuit using a scan path in which the N holding circuits are connected in cascade in a semiconductor package including: Means for holding the external terminal arrangement information, and means for holding first wiring information indicating the names of the wirings connected to the N external terminals, and means provided for the N external terminals. Means for holding second wiring information indicating a wiring name connected to an input / output terminal of a holding circuit for holding a signal input / output to / from a terminal, the second wiring information and the external terminal arrangement information Wirings respectively connected to the output terminal of the first holding circuit and the input terminal of the second holding circuit for the first and second holding circuits corresponding to the two external terminals shown to be more adjacent to each other Name determining means for assigning the same wiring name to the control means, control means for controlling the wiring name assigning operation by the wiring name determining means for all of the N holding circuits, the control means and the wiring name determining means Means for performing a function test of the internal circuit using the N holding circuits to which the wiring names are assigned.

[0014]

Next, the present invention will be described with reference to the drawings.

FIG. 2 is a schematic block diagram of an embodiment of a scan path designing apparatus according to the present invention.

As shown in FIG. 1, a scan path designing apparatus 10 according to an embodiment of the present invention includes external terminal arrangement information 1 indicating an arrangement of each external terminal in a semiconductor package.
2 and wiring information indicating the name of the wiring connected to each external terminal and the input / output terminals of a holding circuit provided corresponding to each external terminal and holding signals input / output to / from the corresponding terminal. Boundary Scan Connection Circuit 13 Inputting Logic Circuit Information 11 Consisting of Wiring Information Indicating Wiring Name
It is comprised including. Then, the logic circuit information 14 including the connected boundary scan path is output from the boundary scan connection circuit 13.

Hereinafter, after describing the contents of the logic circuit information 11 and the external terminal arrangement information 12, the processing procedure in the boundary scan connection circuit 13 will be described in detail.

First, the contents of the logic circuit information 11 will be described.

In general, an LSI is divided into several sub-blocks, and the design is performed for each sub-block. The sub-block includes an I / O sub-block provided around an internal circuit that realizes an original function of the LSI. This is constituted by a holding circuit for holding signals of input / output terminals of the LSI.

The holding circuit has a data-in terminal DIN and a data-out terminal DOUT, as shown in FIG.
, Scan-in terminal SIN and scan-out terminal SOU
T and The buffer 51 transmits the signal of the data-in terminal DIN to the data-out terminal DOUT, the selector 52 for selectively outputting its output and the signal of the scan-in terminal SIN, and holds the output. The flip-flop 53 is included.

The selector 52 selectively outputs the output of the buffer 51 or the signal of the scan-in terminal SIN according to the level of the input signal at the control terminal SEL. Therefore, the output of the buffer 51 can be held in the flip-flop 53 by the input to the control terminal SEL. Note that the flip-flop 53 is connected to the clock terminal CL.
The output of the buffer 51 is held at the timing of the clock signal to K.

FIG. 4 shows the configuration of an I / O sub-block using this holding circuit. In the figure, I /
The O sub-block includes five holding circuits BLK1 to BLK5.
It is assumed to be constituted by It is assumed that the data-in terminal of each holding circuit is connected to the external terminals A00 to A04. Further, it is assumed that the data-out terminal of each holding circuit is connected to the external terminals B00 to B04, the scan-in terminal is connected to the external terminals C00 to C04, and the scan-out terminals D00 to D04, respectively.

Here, the names of the wires connected to each terminal and each external terminal of each holding circuit are NET11, NET12,
Assuming that NET13, NET14,..., Wiring names connected to the respective external terminals are shown in FIG. FIG. 6 shows the names of the wirings connected to the input / output terminals of the holding circuit that is provided corresponding to each external terminal and holds the signals input / output to / from the corresponding terminal. The information of FIG. 5 and FIG.
1 is the logic circuit information 11 in FIG.

That is, the logic circuit information 11 includes first wiring information (FIG. 5) indicating names of wiring connected to each external terminal, and input / output to / from a corresponding terminal provided for each external terminal. And the second wiring information (FIG. 6) indicating the name of the wiring connected to the input / output terminal of the holding circuit that holds the signal to be output.

That is, the first wiring information is information indicating wiring names NET11, NET12,... Connected to the external terminals IBUF1, IBUF2,. As shown in FIG. 6, the second wiring information includes a holding circuit BLK provided for each external terminal and holding a signal input / output to / from the corresponding terminal.
Wiring names NET11, NET12, connected to the input / output terminals I1, I2, O1, and O2 of 1, BLK2,.
...

Incidentally, the external terminal arrangement information 12 shown in FIG.
Is information indicating the arrangement of each external terminal in the semiconductor package, and as shown in FIG. 7A, is information indicating the correspondence between pin numbers and terminal names. That is, the LS having 1 to 100 pins shown in FIG.
In FIG. 1A, the correspondence between the pin numbers 1 to 100 and the terminal names is shown in FIG. 3A, which is the external terminal arrangement information 12.

In this embodiment, it is assumed that the pin number 1 is the scan-in terminal SIN and the pin number 100 is the scan-out terminal SOUT. Others include a clock terminal and a power supply terminal, which are omitted in the figure.

Next, a processing procedure in the boundary scan connection circuit 13 will be described. FIG. 8 is a flowchart showing a processing procedure in the boundary scan connection circuit 13. As a premise of the processing, it is assumed that external terminal arrangement information and logic circuit information are stored in a file such as a magnetic disk.

In the figure, first, external terminal arrangement information is extracted from a file (step 81).

Then, adjacent external terminals are searched for by referring to the extracted arrangement information, and the names of the wirings (information in FIG. 5) connected to the adjacent external terminals are extracted from the file (step 82). Also, the names of the wirings (information in FIG. 6) connected to the input / output terminals of the holding circuit corresponding to the external terminals are extracted from the file (step 83).

With respect to the wiring names extracted in steps 82 and 83, the wiring names connected to the scan-out terminal of one holding circuit and the wiring names connected to the scan-in terminal of the other holding circuit are rewritten. The same wiring name is given (step 84). For example, the same wiring name (for example, NET0) is assigned to the wiring NET14 connected to the scan-out terminal of the holding circuit BLK1 and the wiring NET22 connected to the scan-in terminal of the holding circuit BLK2 shown in FIG. Give it. The above processing is performed for all external terminals (step 85).

Thus, the wiring NET24 connected to the scan-out terminal of the holding circuit BLK2 and the wiring NE connected to the scan-in terminal of the holding circuit BLK3.
The same wiring name (for example, NET1) is given to T32, and similarly, the same wiring name is given to the scan-out terminal and scan-in terminal of all the holding circuits BLK1 to BLK5. The result is shown in FIG. 1, which is the logic circuit information 14 in FIG.

That is, the holding circuits BLK1 to BLK5 are cascaded by the wirings NET0 to NET3 to form a scan path. The entrance of this scan path is the scan-in terminal SIN, and the exit is the scan-out terminal SOUT
It is.

The terminals C01, C02, C03 in FIG.
And C04 and terminals D00, D01, D02 and D03 are terminals in the middle of the scan path, and thus are not external terminals of the LSI but are deleted from the logic circuit information 14. As a result, these terminals are shown in parentheses in FIG.
Unnecessary wiring portions are indicated by broken lines.

As described above, the I / O sub-block 70 can be automatically designed by rewriting the same wiring name.

Next, a description will be given of a case where an I / O sub-block 70 is used to test an LSI with reference to FIG.

First, the position information and the control value information of the shift control terminal are extracted from the automatically designed logic circuit information (step 91). The control value information is information indicating the relationship between the logic level of the shift control terminal and the operation of the LSI.
In this example, it is assumed that the LSI is in the shift mode when the logic level of the shift control terminal is “1” and is in the normal mode when it is “0”.

Next, referring to the extracted information, the LSI on the package is set to the shift mode and the shift-in terminal S is set.
A test pattern is applied from IN (step 92). As a result, a value is set to the FF in each holding circuit that holds the signal from the input terminal of the LSI.

In this state, the LSI is set to the normal mode and the set value of the FF is output (step 93).
As a result, a predetermined value (test result) is set in the FF in each holding circuit that holds the signal to the output terminal of the LSI.

When the test result is set to FF, the LSI is set to the shift mode and the shift-out terminal SOUT is set.
Derives test results from and observes them (step 9
4).

The same test is performed by changing the test patterns one after another until the test is completed for all the test patterns (steps 95 and 96). The test patterns include all 0, all 1, 0101..., 1010.
Data.

When the LSI is changed to the shift mode, the normal mode, and the shift mode in the same manner as described above using the test pattern for the function test of the LSI, the function test of the internal circuit of the LSI alone can be performed. This allows
It is possible to determine whether the failure location of the package is an LSI or not, and it is easy to analyze the cause of the failure.

If an LSI test is performed using the automatically designed boundary scan path as described above, it is not necessary to create a new test pattern, and the test can be performed easily.

[0044]

As described above, the present invention is applicable to the external terminal arrangement information indicating the arrangement of each external terminal in the semiconductor package, the wiring information indicating the name of the wiring connected to each external terminal, and the external terminals. The scan path is automatically designed by changing the wiring name based on the wiring information indicating the wiring name connected to the input / output terminals of the holding circuit that holds the signals input / output to / from the corresponding terminals. This has the effect of improving design efficiency. In addition, by performing a test using the automatically designed scan path, the test can be easily performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing contents of an I / O sub-block after a scan path is connected.

FIG. 2 is a schematic configuration diagram of a scan path designing apparatus according to an embodiment of the present invention.

FIG. 3 is a block diagram illustrating an example of an internal configuration of a holding circuit.

FIG. 4 is a block diagram showing contents of an I / O sub-block corresponding to contents of logic circuit information.

FIG. 5 is a conceptual diagram showing contents of logic circuit information in FIG.

FIG. 6 is a conceptual diagram showing contents of logic circuit information in FIG.

7A is a conceptual diagram showing the contents of external terminal arrangement information in FIG. 2, and FIG. 7B is a schematic diagram showing an LSI pin arrangement.

FIG. 8 is a flowchart illustrating a processing procedure of the scan path designing apparatus of FIG. 1;

FIG. 9 is a flowchart illustrating a processing procedure of the scan path test apparatus according to the embodiment of the present invention.

FIG. 10 is a schematic diagram showing a case where LSIs are connected by a boundary scan path.

[Explanation of symbols]

 51 Buffer 52 Selector 53 FF 60, 70 I / O Sub-Block BLK1-BLK5 Holding Circuit NET0-NET3, NET11-NET54 Wiring SIN Scan-in Terminal SOUT Scan-out Terminal

Claims (4)

(57) [Claims] 1. N number of external terminals (N is an integer of 2 or more, the same applies hereinafter), and N number of external terminals provided corresponding to the N external terminals and holding signals input / output to / from corresponding terminals. A scan path designing apparatus for designing a scan path in which the N holding circuits are connected in cascade in a semiconductor package including the holding circuit of FIG. 1 and a wiring connected between these circuits and terminals; Means for holding external terminal arrangement information indicating the arrangement of each external terminal in the first embodiment, and a first indicating the name of a wiring connected to the N external terminals.
Means for holding wiring information, and wiring names connected to input / output terminals of a holding circuit provided corresponding to the N external terminals and holding signals input / output to / from the corresponding terminals. Means for holding two pieces of wiring information; and first and second holding circuits corresponding to two external terminals indicated to be adjacent by the second wiring information and the external terminal arrangement information. Wiring name determining means for providing the same wiring name to the wiring connected to the output terminal of the holding circuit and the input terminal of the second holding circuit, respectively; A scan path designing apparatus comprising: a control unit configured to perform control for all the holding circuits. 2. The scan path designing apparatus according to claim 1, wherein said scan path has a boundary scan path function. 3. An internal circuit having a predetermined function and N (N)
Is an integer of 2 or more, the same applies hereinafter), N holding circuits provided corresponding to the N external terminals and holding signals input / output to / from the corresponding terminals, and these circuits and terminals A scan path test apparatus that performs a function test of the internal circuit using a scan path in which the N holding circuits are connected in cascade in a semiconductor package including wiring connected between the semiconductor package and the semiconductor package. Means for holding external terminal arrangement information indicating the arrangement of each external terminal; and first means for indicating wiring names connected to the N external terminals.
Means for holding wiring information, and wiring names connected to input / output terminals of a holding circuit provided corresponding to the N external terminals and holding signals input / output to / from the corresponding terminals. Means for holding two pieces of wiring information; and first and second holding circuits corresponding to two external terminals indicated to be adjacent by the second wiring information and the external terminal arrangement information. Wiring name determining means for providing the same wiring name to the wiring connected to the output terminal of the holding circuit and the input terminal of the second holding circuit, respectively; Control means for performing control for all the holding circuits; and means for performing a function test of the internal circuit using the N holding circuits to which the wiring names are assigned by the control means and the wiring name determining means. Have Scan path test apparatus characterized by. 4. The scan path test apparatus according to claim 3 , wherein the scan path has a boundary scan path function.