JPH09311157A - Electronic circuit tester - Google Patents

Abstract

PROBLEM TO BE SOLVED: To carry out a connection test between electronic circuits without causing unnecessary delay in a normal circuit. SOLUTION: Resistors 11-16, 21-23 directly connected with respective input and output terminals of LSIs 1, 2 are connected vertically to constitute scan paths 110, 120. Scanning operation is instructed from a tester apparatus and clock input in a necessary number of clocks is carried out to house testing information in the resistors 14-16. After that, a tester apparatus instructs normal operation, sends out the testing information housed in the resistors 14-16 to inter-LSI signals, and makes the resistors 21-23 take in the resultant testing information. The tester apparatus again instructs the scanning operation, reads out the information taken in the resistors 21-23, and checks whether the content read out of the resistors 21-23 is the same as the testing information set in the resistors 16, 15, 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic circuit testing device, and more particularly to a method for testing a connection state between a plurality of electronic devices that constitute an information processing device that operates at high speed.

[0002]

2. Description of the Related Art In recent years, with the high integration of LSIs (Large Scale Integrated Circuits), the packaging technology of LSIs has improved, and the number of pins of LSIs has increased remarkably. Is becoming very small. Further, the function and performance of the printed circuit board have been greatly improved, and the area of the LSI has been reduced accordingly.

Therefore, the LS mounted on the printed circuit board
It is becoming difficult to test the I or the printed circuit board itself by the conventional method. That is, since the distance between LSIs and the distance between pins are becoming very small, it is becoming difficult to apply the probe to the pin by the conventional method of testing the LSI or the printed circuit board by applying the probe to the pin. .

In order to solve the above problems, a boundary scan method has been proposed for the purpose of testing the connection between LSIs assembled on a wiring board. For this boundary scan method, see
ndard Test Access Port an
d Boundary-Scan Architect
ure ”(Institue of Collector
ical and Electronics Engi
neers, Inc. , 1987.7.20. , Pp1
-4 to 1-6).

This boundary scan method requires a circuit configuration as shown in FIG. That is, it is necessary to previously incorporate a circuit for boundary scan into the LSI and the package (PKG). The operation of the circuit will be described below with reference to FIG.

When the LSIs 5 and 7 are connected on a package (not shown), the boundary scan is performed on the LSI 5 and LSI 7.
The purpose is to test whether the signal lines 161-163 between 7 are properly connected.

Therefore, scan registers 51 to 56 and 71 to 73 are provided in the LSIs 5 and 7, respectively, and the scan registers 51 to 56 and 71 to 73 are connected in cascade to form scan paths 154 and 174.

The LSI 5 is composed of scan registers 51-5.
6, a scan control circuit 57, an internal circuit 58, flip-flops (hereinafter referred to as FF) 59 to 64, logic circuits 65 and 66, selectors 67 to 69, and an input terminal 5.
0a to 50c, a scan-in terminal 50d, a scan control terminal 50e, a scan-out terminal 50f, and output terminals 50g to 50i.

Further, the LSI 7 includes scan registers 71 to 71.
73, scan control circuit 74, and input terminals 70a-7
0c, a scan-in terminal 70d, and a scan control terminal 70e.

In the scan paths 154 and 174, when the scan operation is instructed by the scan control signal 150, the scan control circuits 54 and 74 output the scan instruction signals 155 and 175, respectively, so that the scan registers 51 to 56 and 71. To 73 perform a shift operation in which the held contents are sequentially passed to the next stage, so that an arbitrary value is set in each of the scan registers 51 to 56, 71 to 73, and each of the scan registers 51 to 56, 71 to 73 is held. The old value that has been read can be read.

In the boundary scan method, a scan operation is instructed by the scan control signal 150, data is set in the scan registers 54 to 56, and then a test operation is instructed by the scan control signal 150. When this test operation is instructed, the scan control circuit 54 instructs the selectors 67 to 69 to output the values of the scan registers 54 to 56 to the signal lines 161 to 163 by the output switching signal 156.

At the same time, the scan control circuit 54 instructs the scan registers 51 to 53 to take in the input signals 151 to 153 from the input terminals 50a to 50c. The scan control circuit 74 also scans the scan register 7 so as to take in the input signals 171 to 173 from the input terminals 70a to 70c.
Instruct 1-73.

If the connection between the LSIs 5 and 7 is normal, the contents of the scan registers 56, 55 and 54 are transferred to the scan registers 71 to 73 by this test operation.

When the test operation is completed, the scan operation is again instructed by the scan control signal 150 to read the contents of the scan registers 71 to 73. The contents read from the scan registers 71 to 73 are the scan registers 56,
By checking whether the data is the same as the data set in 55 and 54, it is possible to know whether the connection between the LSIs 5 and 7 is normal.

Therefore, the connection between the LSIs 5 and 7 is made by connecting each LSI.
It can be checked without applying a probe (not shown) to the pins (input terminals 50a to 50c, 70a to 70c, output terminals 50g to 50i, etc.).

In the above circuit configuration, the FF6 which is the output of the normal circuit is output to the selectors 67 to 69 during the normal operation.
Normal operation can be performed by selecting 0 or the output of the logic circuits 65 and 66.

[0017]

SUMMARY OF THE INVENTION In the above-mentioned conventional method for testing the connection state between electronic circuits, it is possible to use the boundary scan method to set the probe to the LSI pin without placing the probe on the LSI pin.
Although it becomes possible to check the connection between SIs, in this method, since the selector is provided in the preceding stage of the output pin to switch between the normal circuit and the test circuit, the delay of the normal circuit increases by the selector.

In recent electronic circuits, the operating frequency has become higher, but the delay between LSIs has become dominant as compared with the delay inside LSIs. For high-speed devices, we devised a circuit, and for the interface between LSIs, FF
Although I try to input it directly without going through the logic circuit, the delay for the selector is inevitably included when the boundary scan circuit is inserted. Therefore, the boundary scan circuit cannot be used for a high-speed input / output interface.

Therefore, an object of the present invention is to solve the above-mentioned problems and to provide an electronic circuit test apparatus capable of conducting a connection test between electronic circuits without incurring extra delay in a normal circuit. .

[0020]

A first electronic circuit testing device according to the present invention is an electronic circuit testing device for testing a connection state between a plurality of electronic circuits, and is provided in each of the plurality of electronic circuits. An output terminal for outputting a signal to another circuit, a first holding unit provided in each of the plurality of electronic circuits and holding a signal to be output to the output terminal, and provided in each of the plurality of electronic circuits An input terminal for inputting a signal from another circuit, a second holding unit provided in each of the plurality of electronic circuits and holding a signal input to the input terminal, and each of the other circuit and its own circuit. A scan path formed by connecting the first and second holding units in cascade,
Means for storing the test information in the first holding means of the own circuit by using the scan path, and the test information stored in the first holding means of the own circuit from the output terminal of the own circuit Means for outputting to the input terminal of another circuit,
And means for reading the test information held in the second holding means of another circuit by using the scan path.

A second electronic circuit testing device according to the present invention is
In addition to the above configuration, a first logic circuit to which a signal from the input terminal is directly input and a third logic circuit that is cascade-connected to the scan path and holds a signal to be input to the first logic circuit are provided. Holding means.

A third electronic circuit testing device according to the present invention is
In addition to the above configuration, a second logic circuit that directly outputs a signal to the output terminal, and a fourth logic circuit that is cascaded to the scan path and that holds a signal from the scan path and outputs the signal to the logic circuit Holding means for holding the second logic circuit during the scan operation of the scan path.
The holding content of the holding means is selected and output to the output terminal.

A fourth electronic circuit testing device according to the present invention is
In addition to the above configuration, a third logic circuit that directly outputs a signal to the output terminal, a fifth holding unit that is cascade-connected to the scan path and holds a signal from the scan path, and the scan path When the scan operation of
A fourth logic circuit which outputs a value to the third logic circuit such that the third logic circuit outputs the content held by the fifth hold means to the output terminal in response to the signal from the hold means. It has and.

A fifth electronic circuit test apparatus according to the present invention is
An electronic circuit test device for testing a connection state between a plurality of electronic circuits, the output terminal being provided in each of the plurality of electronic circuits and outputting a signal to another circuit, and being provided in each of the plurality of electronic circuits. An input terminal for inputting a signal from another circuit, a logic circuit provided in each of the plurality of electronic circuits and directly receiving a signal from the input terminal, and provided in each of the plurality of electronic circuits And a first holding means for holding a signal to be output to the output terminal, a second holding means provided in each of the plurality of electronic circuits and holding a signal input to the logic circuit, another circuit, A scan path formed by cascading the first and second holding means of each own circuit; means for storing test information in the first holding means of the own circuit using the scan path; Of the first Held in the second holding means of another circuit by using the means for outputting the test information stored in the holding means of the other circuit from the output terminal of the own circuit to the input terminal of the other circuit. And means for reading the test information.

A sixth electronic circuit testing device according to the present invention is
An electronic circuit test device for testing a connection state between a plurality of electronic circuits, the output terminal being provided in each of the plurality of electronic circuits and outputting a signal to another circuit, and being provided in each of the plurality of electronic circuits. An input terminal for inputting a signal from another circuit, first holding means provided in each of the plurality of electronic circuits and holding a signal input to the input terminal, and each of the plurality of electronic circuits A logic circuit for directly outputting a signal to the output terminal, a scan path formed by cascading the first holding means of another circuit and its own circuit, and a scan path provided in each of the plurality of electronic circuits. Second holding means that is connected in cascade to the scan path and holds a signal from the scan path and outputs the signal to the logic circuit; and the second holding means of the own circuit using the scan path. Means for storing test information, and means for outputting a signal outputted from the logic circuit of its own circuit from the output terminal of the self circuit to the input terminal of another circuit,
Means for reading the test information held in the first holding means of another circuit using the scan path,
When the scan operation of the scan path is performed, the logic circuit is configured to select the content held in the second holding unit and output the selected content to the output terminal.

A seventh electronic circuit testing device according to the present invention is
An electronic circuit test device for testing a connection state between a plurality of electronic circuits, the output terminal being provided in each of the plurality of electronic circuits and outputting a signal to another circuit, and being provided in each of the plurality of electronic circuits. An input terminal for inputting a signal from another circuit, first holding means provided in each of the plurality of electronic circuits and holding a signal input to the input terminal, and each of the plurality of electronic circuits And a scan path formed by cascading the first holding means of another circuit and its own circuit, and a plurality of electronic circuits to each of the plurality of electronic circuits. Second holding means provided and cascaded to the scan path, and the first logic circuit having the second holding means in response to a signal from the second holding means during a scan operation of the scan path. of The test information is stored in the second holding unit of the own circuit by using the second logic circuit that outputs a value that outputs the stored content to the output terminal to the first logic circuit and the scan path. Means for outputting a signal output from the first logic circuit of the own circuit to the input terminal of another circuit from the output terminal of the own circuit, and the first circuit of the other circuit using the scan path. And means for reading the test information held by the holding means.

[0027]

First, the operation of the present invention will be described below.

When a register of an LSI directly outputs a signal to an output terminal or a register of an LSI and a register of another LSI directly input a signal from an input terminal, the corresponding registers are connected in cascade to form a scan path. Configure
After setting the test information in the register by the scan operation of scan path, the normal operation is performed, and the scan path is checked again whether the test information set in the register of the LSI is properly set in the register of other LSI through the signal between LSIs. Check by scanning.

Thus, the connection between the LSIs can be tested without applying a probe to the input terminal and the output terminal. Therefore, the selector for the output part used in the conventional example is not required, and the delay restriction can be reduced, and the speed is correspondingly increased.

Further, when it is necessary to insert a logic circuit between the input terminal and the FF, a scan register for holding a signal input to the logic circuit is provided, and this scan register is cascade-connected to the scan path.

Thus, the connection between the LSIs can be tested without inserting more circuits than necessary between the input terminal and the flip-flop (hereinafter referred to as FF).

Further, when it is necessary to insert a logic circuit between the output terminal and the FF, a scan register for holding a signal to be output to the logic circuit is provided, and this scan register is cascade-connected to the scan path.

As a result, the connection between the LSIs can be tested without inserting an unnecessary circuit between the output terminal and the FF.

Furthermore, the first terminal is provided between the output terminal and the FF.
If the selection function for selecting the contents of the scan register cannot be added to the first logic circuit in a delayed manner, it is necessary to insert the logic circuit of A second logic circuit that outputs data such that the same value as the input value is output from the first logic circuit is provided, and the output of the second logic circuit is input to the FF.

Thus, the connection between the LSIs can be tested without inserting an unnecessary circuit between the output terminal and the FF.

Next, an embodiment of the present invention will be described. For example, when one electronic circuit is connected to another electronic circuit, an object of the present invention is to enable testing whether the inter-electronic circuit signal between one electronic circuit and another electronic circuit is properly connected. To do.

In a high-speed circuit, it is possible to output directly from the holding means or input directly to the holding means by devising the circuit, so that it is directly connected to each of the input terminal and the output terminal of an electronic circuit and another electronic circuit. The holding means are connected in cascade to form a scan path.

When a scan operation is instructed by the scan control signal, these holding means perform a shift operation of sequentially passing the held contents to the next stage for each clock, so that an arbitrary value is given to each holding means. It is possible to set or read the old value held in each holding means.

In the present invention, the scan operation is instructed by the scan control signal from the tester device, and the test information is stored in the holding means of a certain electronic circuit by inputting the required number of clocks. After that, the tester device instructs the normal operation by canceling the instruction of the scan operation by the scan control signal, and outputs the test information stored in the holding means of a certain electronic circuit to the inter-electronic circuit signal.

At this time, the tester device inputs the clock and causes the test information output as the inter-electronic circuit signal to be taken into the holding means of another electronic circuit. In that case, if the connection between a certain electronic circuit and another electronic circuit is normal, the test information output to the inter-electronic circuit signal, that is, the content of the holding means of one electronic circuit is the holding means of the other electronic circuit. Be taken into.

Further, the tester device instructs the scan operation again by the scan control signal and reads the information taken in the holding means of another electronic circuit. Therefore, by checking whether the contents read from the holding means of another electronic circuit are the same as the test information set in the holding means of an electronic circuit, the connection between one electronic circuit and another electronic circuit is normal. You can know if

Therefore, the connection between one electronic circuit and another electronic circuit can be tested without applying the terminals of the tester to the respective electronic circuit terminals, and the selection means of the output portion in the conventional example is unnecessary. Therefore, the connection test method according to the present invention can be used for a high-speed electronic circuit.

In the above structure, the holding means exchanges data with a normal logic circuit represented by an internal circuit by canceling the scan operation instruction by the scan control signal during the normal operation. Will be done.

With most of the circuits, it is possible to directly output from the holding means or input directly to the holding means without passing through the logic circuit by devising the circuit, but the logic circuit is inevitably inserted in the input / output portion. You may have to do it.

In such a case, for example, when it is necessary to insert a logic circuit into the input portion, scan holding means for holding an input signal input to the logic circuit from the input terminal is provided. The input signal input from the input terminal is input to the FF through the logic circuit.

These scan holding means are connected in cascade to other holding means directly connected to the input / output terminals to form a scan path. When the scan control signal indicates the scan operation, the shift operation is performed, and the scan control signal is sent. The normal operation is performed when the scan operation is not instructed.

Therefore, if the scan holding means is caused to perform the shift operation by instructing the scan operation by the scan control signal, the input signal can be read and checked. With this configuration, the number of branches of the input signal is increased by 1, so that the influence on the delay can be relatively small.

When it is necessary to insert a logic circuit into the output part, another holding means directly connected to the input / output terminal is cascade-connected to the scan path constituted by cascade-connecting the other holding means. Scan holding means for holding an input signal and outputting it to a logic circuit is provided. still,
The logic circuit takes a certain logic for the signal input from the FF and outputs it.

The scan holding means performs the shift operation when the scan control signal instructs the scan operation, and performs the normal operation when the scan control signal does not instruct the scan operation.

In this case, the logic circuit is configured to select the signal from the scan holding means at the time of test and output it to the output terminal, and to output the value using the value of FF at the time of normal operation.

Therefore, it is necessary to give a signal to the logic circuit to determine whether it is during test or normal operation. This signal may be designated from the outside by providing a dedicated terminal in the electronic circuit, or may be designated by receiving the scan instruction signal once by the scan instruction holding means. Therefore, the logic circuit considers the test operation only for one clock after the scan operation signal is instructed by the scan instruction signal, selects the signal from the scan holding means, and outputs it to the output terminal.

Here, the effect of the present invention cannot be exhibited in the logic circuit simply by providing the selecting means in series with the normal circuit. Although the present invention depends on the complexity of the normal logic in the logic circuit, it becomes an effective solution only when a circuit configuration that requires less delay than the normal logic is possible. For example, when the logic circuit is a selection unit or the like, there is a high possibility that such a circuit configuration will be possible.

Further, when it is difficult to create a logic circuit including the scan holding means as compared with the normal logic, that is, it is necessary to insert a logic circuit in the output portion, and further, the selection of selecting the contents of the scan holding means in the logic circuit. Functions may not be added in a delayed manner.

For example, if the output from the first logic circuit is FF
In the case of a configuration in which the output of the second logic circuit is directly output to the output terminal through the above, the scan holding means for holding the information to be output to the output terminal may be provided. In some cases, the selection function for selecting the contents of the scan holding means cannot be added to the second logic circuit in a delayed manner.

In this case, the value input to the scan holding means is input to the first logic circuit which outputs the information input to the FF. When the scan operation is instructed by the scan instruction signal in the first logic circuit, the value that is eventually input to the scan holding unit when the information entered in the FF is output through the second logic circuit. The same information as is output to the FF.

As an example, when the output of the FF is (0,0), the output of the second logic circuit is "0", and when the output of the FF is (1,1), the output of the second logic circuit is When it is "1", if the input of the scan holding means is "0" when the scan operation is instructed by the scan instruction signal, (0,0) is output from the first logic circuit to FF,
If the input of the scan holding unit is "1", (1, 1) may be output from the first logic circuit to the FF. As a result, the output from the second logic circuit eventually becomes the same value as the scan holding means during the scan operation.

By adopting such a circuit configuration, no additional circuit is required for the path output from the FF through the logic circuit, so that the electronic circuit inspection cannot be performed due to the delay restriction. .

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. In the figure, LSIs 1 and 2 each constituting an electronic device are connected on a package (not shown).

In a high-speed circuit, it is possible to directly output from the register or input directly to the register by devising the circuit. Therefore, in the LSI 1, the interface, that is, the input terminals 10a to 10c and the output terminals 10g to 10i are directly connected. The registers 11 to 16 are connected in cascade to form the scan path 110, and in the LSI 12, the register 2 directly connected to each of the input terminals 20a to 20c.
1 to 23 are connected in cascade to form a scan path 120.

Here, the LSI 1 includes the scan register 11
To 16, the internal circuit 17, and the input terminals 10a to 10c
, Scan-in terminal 10d, and scan control terminal 10
e, the scan-out terminal 10f, and the output terminal 10g-
And 10i. Further, the LSI 2 includes scan registers 21 to 23 and input terminals 20a to 20c.
, Scan-in terminal 20d, and scan control terminal 20
and e.

These registers 11 to 16 and 21 to 23
When the scan operation is instructed by the scan control signal 101, that is, when the scan operation is instructed by the scan control signals 111 and 121 from the scan-in terminals 10d and 20d, the registers 11 to 16 and 21 to 23 are set every clock. Since the shift operation of sequentially passing the held contents to the next stage is performed, it is possible to set an arbitrary value in each of the registers 11 to 16 and 21 to 23 and to set the registers 11 to 16 and 21 to 21.
The old value held in each of the 23 can be read.

In this embodiment, a scan operation is instructed by a scan control signal 100 from a tester device (not shown),
The test information is stored in the registers 14 to 16 by inputting as many clocks as necessary. After that, the tester device instructs the normal operation by canceling the instruction of the scan operation by the scan control signal 100, and the register 14 ...
The test information stored in 16 is used as the inter-LSI signals 101 to 103.
Output to

At this time, the tester device inputs a clock and causes the registers 21 to 23 to capture the test information output to the inter-LSI signals 101 to 103. In that case, LSI
If the connection between 1 and 2 is normal, the signal 101
The test information output to 103, that is, registers 14 to 1
The contents of 6 are taken into registers 21-23.

Further, the tester device uses the scan control signal 1
00 to instruct the scan operation again and register 21
Read the information captured in .about.23. Registers 21-23
By checking whether the contents read from the register are the same as the test information set in the registers 16, 15 and 14,
It is possible to know whether the connection between SI1 and SI2 is normal.

Therefore, the connection between the LSI 1 and the LSI 2
It can be checked without applying a probe (not shown) to the pins (input terminals 10a to 10c, 20a to 20c, output terminals 10g to 10i, etc.). In this case, since the selector of the output part in the conventional example is not required, the connection test method according to the present embodiment can be used in a high-speed electronic circuit.

In the circuit configuration described above, the registers 11 to 16 and 21 to 23 are set to the normal circuit represented by the internal circuit 17 by canceling the scan operation instruction by the scan control signal 100 during the normal operation. Data will be exchanged with the logic circuit.

FIG. 2 is a time chart showing the operation of the embodiment of the present invention. The operation of the embodiment of the present invention will be described with reference to FIGS. In FIG. 2, “X” indicates an indefinite or arbitrary value.

When the scan operation is instructed by the scan control signal 100 from the tester device and the necessary number of clocks are input, the registers 14 to 1 of the LSI 1 are input.
6 shows the scan path 110 for the test information “A”,
“B” and “C” are stored.

After that, the tester device outputs the scan control signal 1
When the scan operation instruction by 00 is canceled and the normal operation is instructed, the test information stored in the registers 14 to 16 is output to the inter-LSI signals 101 to 103.

At this time, when the tester device inputs a clock, the test information output to the inter-LSI signals 101 to 103 is taken in the registers 21 to 23 of the LSI 2. In that case, if the connection between the LSIs 1 and 2 is normal, the test information output to the LSI signals 101 to 103, that is, the contents “A”, “B”, and “C” of the registers 14 to 16 are stored in the registers 21 to 21. 23.

Further, the tester device outputs the scan control signal 1
When the scan operation is instructed again by 00, the information taken in the registers 21 to 23 is read out to the tester device through the scan path 120. Register 2 for tester device
The contents read from 1 to 23 are registers 16, 15, and 14
By checking whether the test information is the same as the test information “A”, “B”, and “C” set in, it is possible to know whether the connection between the LSIs 1 and 2 is normal.

FIG. 3 is a diagram showing a configuration example in the case where it is not necessary to insert a logic circuit into the input portion according to the embodiment of the present invention. In the figure, since it is not necessary to insert a logic circuit in the input portion in this configuration example, the input signal from the input terminal 10a is directly input to the register 11.

Therefore, in this configuration example, similar to the circuit configuration of FIG. 1, the register 11 is cascade-connected to another register (not shown) directly connected to the input terminal and the output terminal to form a scan path, The shift operation is performed when the scan control signal 100 instructs the scan operation, and the normal operation is performed when the scan control signal 100 does not instruct the scan operation.

FIG. 4 is a diagram showing a configuration example in the case where it is not necessary to insert a logic circuit in the output portion according to the embodiment of the present invention. In the figure, in this configuration example, since it is not necessary to insert a logic circuit in the output part, the output signal is directly output from the register 14 to the output terminal 10i.

Therefore, in this configuration example, similarly to the circuit configuration of FIG. 1, the register 14 is cascade-connected to another register (not shown) directly connected to the input terminal and the output terminal to form a scan path, The shift operation is performed when the scan control signal 100 instructs the scan operation, and the normal operation is performed when the scan control signal 100 does not instruct the scan operation.

FIG. 5 is a diagram showing a configuration example in the case where a logic circuit needs to be inserted in the input portion according to another embodiment of the present invention. In the figure, since it is necessary to insert the logic circuit 33 in the input portion in this configuration example, the input terminals 30a, 3
Input signals 131, 1 input to the logic circuit 33 from 0b
Scan registers 31, 32 holding 32 are arranged. The input signals 131 and 132 input from the input terminals 30a and 30b are input to the FF 34 through the logic circuit 33.

These scan registers 31 and 32 are cascade-connected to another register directly connected to the input terminal and the output terminal to form a scan path, and the scan control signal 1
When 00 indicates a scan operation, a shift operation is performed, and when the scan control signal 100 does not instruct a scan operation, a normal operation is performed.

Therefore, by instructing the scan operation by the scan control signal 100, the scan register 3
If the shift operation is performed on the input signals 131, 32,
132 can be read and checked. In this configuration, the fanout of the input signal is increased by 1, so that the influence on the delay is relatively small.

FIG. 6 is a diagram showing a configuration example in the case where it is necessary to insert a logic circuit into the output portion according to another embodiment of the present invention. In the figure, in this configuration example, since it is necessary to insert the logic circuit 39 into the output portion, the output signal is directly output from the logic circuit 39 to the output terminal 40a.

Therefore, the scan is connected to the scan path constituted by the cascade connection of the other register directly connected to the input terminal and the output terminal and holds the signal input from the scan path and outputs it to the logic circuit 39. A register 35 is provided. The logic circuit 39 includes the FF 36,
The signal input from 37 is output with a certain logic.

The scan register 35 performs the shift operation when the scan control signal 100 instructs the scan operation, and performs the normal operation when the scan control signal 100 does not instruct the scan operation.

In the case of this configuration example, the logic circuit 39 is configured to select the signal from the scan register 35 and output it to the output terminal 40a during the test, and to output the value using the values of the FFs 36 and 37 during the normal operation. ing.

Therefore, since it is necessary to give the logic circuit 39 a signal for discriminating during the test or the normal operation, the scan instruction register 38 for holding the scan instruction signal 133 is provided and the logic circuit 39 scans. The contents of the instruction register 38 are used to discriminate the test time or the normal operation time. Note that a dedicated terminal may be provided in the LSI and a signal for determining whether the test is performed or the normal operation is performed may be given to the logic circuit 39 from the terminal.

Therefore, the logic circuit 39 considers the test operation only for one clock after the scan operation is instructed by the scan instructing signal 133, and the scan register 3
The signal from 5 is selected and output to the output terminal 40a.

Here, the logic circuit 39 cannot exert the effect of this embodiment only by providing a selector in series with the normal circuit. Although this embodiment depends on the complexity of the normal logic in the logic circuit 39, it becomes an effective solution only when a circuit configuration that requires less delay than the normal logic is possible. For example, when the logic circuit 39 is a selector or the like, such a circuit configuration is likely to be possible.

FIG. 7 is a diagram showing a configuration example in the case where it is necessary to insert a logic circuit into an output portion according to still another embodiment of the present invention. In the figure, in this configuration example, it is necessary to insert the logic circuit 45 in the output portion, and further, the logic circuit 4
5 shows a configuration in which the selection function for selecting the contents of the scan register 41 cannot be added in a delayed manner.

In this case, the value input to the scan register 41 is input to the logic circuit 42 that outputs the data input to the FFs 43 and 44, and the logic circuit 45 outputs the same value as the value input to the scan register 41. Such a value is output from the logic circuit 42 to the FFs 43 and 44.

That is, when the scan operation is instructed by the scan instructing signal 134, the logic circuit 42 changes the data so that the value output from the logic circuit 45 becomes the same value input to the scan register 41 as a result. FF4
3 and 44.

For example, in the logic circuit 45, FF4
When the outputs from 3,44 are (0,0), the output is "0", and when the outputs from the FFs 43,44 are (1,1), the output is "1". If the value input to the scan register 41 when the scan operation is instructed by the instruction signal 134 is "0", (0, 0) is output from the logic circuit 42 to the FFs 43 and 44 and is input to the scan register 41. If the value is "1", the logic circuit 42 may output (1, 1) to the FFs 43 and 44. As a result, the output from the logic circuit 45 eventually becomes the same value as the scan register 41 during the scan operation.

With the circuit configuration as described above, the FF
Since no additional circuit is required for the path output from the logic circuits 43 and 44 through the logic circuit 45, it is possible to prevent the package inspection due to the delay restriction.

In this way, the registers 14-1 of the LSI 1
6 directly outputs the signal to the output terminals 10g to 10i,
The registers 11 to 13 of the LSI 1 and the registers 21 to 23 of the LSI 2 are input terminals 10a to 10c and 20a to 20c.
In the case of directly inputting the signal from the scan path 110, 120, the corresponding registers 11-16, 21-23 are connected in cascade to form the scan paths 110, 120.
After the test information is set in the registers 14 to 16 by the scan operation of No. 1, normal operation is performed, and whether the test information set in the registers 14 to 16 is properly set in the registers 21 to 23 through the inter-LSI signals 101 to 103, By checking the scan paths 110 and 120 again to perform the scan operation, the input terminals 10a to 10a ...
It is possible to test the connection between the LSIs 1 and 2 without applying a probe to the 10c, 20a to 20c and the output terminals 10g to 10i. Therefore, the selector for the output part used in the conventional example is not required, and the delay restriction can be reduced, and the speed is correspondingly increased.

In addition, the input terminals 30a and 30b and the FF 34
When it is necessary to insert the logic circuit 33 between the input terminal 30a and the scan register 31, a scan register 31 for holding a signal input to the logic circuit 33 is provided and the scan register 31 is cascade-connected to the scan path. 30b
The connection between the LSIs 1 and 2 can be tested without inserting more circuits than necessary between the FF and the FF34.

Further, the output terminal 40a and the FFs 36 and 37
When it is necessary to insert the logic circuit 39 between the scan register 3 and the
5 is provided and the scan register 35 is cascade-connected to the scan path to output the output terminal 40a and the FF3.
Without inserting more circuits than necessary between 6 and 37,
The connection between the LSIs 1 and 2 can be tested.

Furthermore, the output terminal 40b and the FF 43,
If it is necessary to insert the logic circuit 45 between the logic circuit 45 and the logic circuit 44, and the selection function for selecting the contents of the scan register 41 cannot be added to the logic circuit 45 in a delayed manner, the result depending on the value input to the scan register 41 By providing the logic circuit 42 that outputs data such that the same value as that input to the scan register is output from the logic circuit 45, and inputting the output of the logic circuit 42 to the FFs 43 and 44, the output terminal 40b It is possible to test the connection between the LSIs 1 and 2 without inserting more circuits than necessary between the FFs 43 and 44.

[0095]

As described above, according to the present invention, an output terminal for outputting a signal to another circuit, a first holding means for holding a signal to be output to the output terminal, and another circuit An input terminal for inputting the input signal and second holding means for holding the signal input to the input terminal are provided in each of the plurality of electronic circuits, and the first and second holding circuits of the other circuit and the own circuit are provided. The means are connected in cascade to form a scan path, and the test information stored in the first holding means of the own circuit is stored after the test information is stored in the first holding means of the own circuit using the scan path. By outputting the test information held in the second holding means of the other circuit from the output terminal of the own circuit to the input terminal of the other circuit by using the scan path, an extra delay is added to the normal circuit. Without inviting
There is an effect that a connection test between electronic circuits can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a time chart showing the operation of one embodiment of the present invention.

FIG. 3 is a diagram showing a configuration example when it is not necessary to insert a logic circuit into an input portion according to an embodiment of the present invention.

FIG. 4 is a diagram showing a configuration example when it is not necessary to insert a logic circuit into an output portion according to an embodiment of the present invention.

FIG. 5 is a diagram showing a configuration example when it is necessary to insert a logic circuit into an input portion according to another embodiment of the present invention.

FIG. 6 is a diagram showing a configuration example when it is necessary to insert a logic circuit into an output portion according to another embodiment of the present invention.

FIG. 7 is a diagram showing a configuration example when it is necessary to insert a logic circuit into an output portion according to still another embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

 1, 2 LSI 10a-10c, 20a-20c 30a, 30b Input terminal 10d, 20d Scan-in terminal 10e, 20e Scan control signal 10f Scan-out terminal 10g-10i, 40a, 40b Output terminal 11-16, 21-23 Register 31 , 32, 35, 41 scan register 33, 39, 42, 45 logic circuit 34, 36, 37, 43, 44 flip-flop 38 scan instruction register

Claims (7)

[Claims] 1. An electronic circuit testing device for testing a connection state between a plurality of electronic circuits, comprising: an output terminal provided in each of the plurality of electronic circuits and outputting a signal to another circuit; First holding means provided in each electronic circuit and holding a signal to be output to the output terminal; input terminals provided in each of the plurality of electronic circuits and for inputting signals from other circuits; Second holding means provided in each of the plurality of electronic circuits and holding the signal input to the input terminal and the first and second holding means of the other circuit and its own circuit are connected in cascade. Campus and
Means for storing the test information in the first holding means of the own circuit by using the scan path, and the test information stored in the first holding means of the own circuit from the output terminal of the own circuit Means for outputting to the input terminal of another circuit,
An electronic circuit test apparatus comprising: a unit that reads out the test information held in the second holding unit of another circuit by using the scan path. 2. A first logic circuit to which a signal from the input terminal is directly input, and a third holding unit that holds a signal cascade-connected to the scan path and input to the first logic circuit. The electronic circuit testing device according to claim 1, further comprising: 3. A second circuit for directly outputting a signal to the output terminal
And a fourth holding unit that is connected to the scan path in cascade and holds a signal from the scan path and outputs the signal to the logic circuit. The second logic circuit is provided during a scan operation of the scan path. 3. The electronic circuit test apparatus according to claim 1, wherein the circuit is configured to select the content held by the fourth holding means and output it to the output terminal. 4. A third device for directly outputting a signal to the output terminal
Logic circuit, fifth holding means connected in series to the scan path and holding a signal from the scan path, and the fifth holding means according to the signal from the fifth holding means during a scan operation of the scan path. 3. The third logic circuit includes a fourth logic circuit which outputs a value for outputting the content held by the fifth holding means to the output terminal, to the third logic circuit. 4. The electronic circuit test device according to claim 3. 5. An electronic circuit test device for testing a connection state between a plurality of electronic circuits, comprising: an output terminal provided in each of the plurality of electronic circuits and outputting a signal to another circuit; An input terminal provided in each electronic circuit for inputting a signal from another circuit; a logic circuit provided in each of the plurality of electronic circuits and directly inputting a signal from the input terminal; First holding means provided in each circuit and holding a signal to be output to the output terminal, and second holding means provided in each of the plurality of electronic circuits and holding a signal input to the logic circuit. And a scan path formed by cascading the first and second holding means of each of the other circuit and the own circuit, and the test information is stored in the first holding means of the own circuit using the scan path. Means and self Means for outputting the test information stored in the first holding means of the circuit from the output terminal of the own circuit to the input terminal of the other circuit, and the second holding of the other circuit using the scan path Means for reading the test information held by the means. 6. An electronic circuit test apparatus for testing a connection state between a plurality of electronic circuits, comprising: an output terminal provided in each of the plurality of electronic circuits and for outputting a signal to another circuit; An input terminal provided in each electronic circuit and for inputting a signal from another circuit; first holding means provided in each of the plurality of electronic circuits and holding a signal input to the input terminal; A logic circuit provided in each of the plurality of electronic circuits and directly outputting a signal to the output terminal, a scan path formed by cascading the other circuits and the first holding means of each of the own circuits, and the plurality of electronic circuits Second holding means provided in each of them and connected in cascade to the scan path and holding a signal from the scan path and outputting the signal to the logic circuit; and the second holding means of the own circuit using the scan path. 2 means for storing test information in the holding means, means for outputting a signal output from the logic circuit of the own circuit to the input terminal of another circuit from the output terminal of the own circuit, and the scan path Means for reading the test information held in the first holding means of another circuit, and the logic circuit selects the contents held in the second holding means during the scan operation of the scan path. And an electronic circuit testing apparatus configured to output to the output terminal. 7. An electronic circuit test device for testing a connection state between a plurality of electronic circuits, comprising: an output terminal provided in each of the plurality of electronic circuits and outputting a signal to another circuit; An input terminal provided in each electronic circuit and for inputting a signal from another circuit; first holding means provided in each of the plurality of electronic circuits and holding a signal input to the input terminal; A first logic circuit provided in each of the plurality of electronic circuits and directly outputting a signal to the output terminal; a scan path formed by cascading the first holding means of each of the other circuits and the own circuit; Second holding means provided in each of the electronic circuits and cascade-connected to the scan path, and the first holding means in response to a signal from the second holding means during a scan operation of the scan path.
A second logic circuit which outputs a value to the first logic circuit such that the logic circuit of the second logic circuit outputs the content held by the second holding means to the output terminal, and the second path of its own circuit using the scan path. Means for storing test information in the second holding means, means for outputting a signal output from the first logic circuit of the own circuit to the input terminal of another circuit from the output terminal of the own circuit, Means for reading the test information held in the first holding means of another circuit by using scan path.