JP3183244B2 - Test method for integrated circuits - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates to the testing of integrated circuits.
About the method .

[0002]

2. Description of the Related Art Conventionally, as a method of avoiding simultaneous operation at the time of testing an integrated circuit, a method of changing test pattern data, a method of reducing the driving capability of an output buffer only at the time of a test, or a method of connecting a plurality of output terminals to a plurality of output terminals are described. There is a method of dividing into groups and operating sequentially.

[0003]

As a measure for avoiding such simultaneous operation, for example, (1) when the test pattern data is changed, an increase in design man-hours, a delay in development delivery, and the like occur. In some cases, the problem cannot be solved only by changing the test pattern data, and (1 ') a circuit change may be required.

In the method of (2) reducing the driving capability only at the time of the test, the number of output terminals may be increased to exceed the simultaneous operation limit number. In this case, (2 ') circuit change,
(2 ") The group must be divided.
The method of dividing the output terminals into a plurality of groups requires operations such as grouping and creating a control circuit.
An increase in design man-hours, a delay in development delivery date, and the like occur.

[0005] Therefore, an object of the present invention is to link the simulation results with the terminal arrangement information so as to automatically perform grouping, control circuit insertion and test pattern data change operations in order to eliminate these drawbacks. It is an object of the present invention to provide a simple integrated circuit test method .

[0006]

A test method for an integrated circuit according to the present invention performs a simulation using a plurality of test pattern data for testing an integrated circuit, and determines the number of simultaneous operations of output signals based on the result of the simulation. A detecting step, a step of comparing the number of simultaneous operations with a preset number of simultaneous operations, and a step of detecting, when the number of simultaneous operations exceeds the number of simultaneous operations, an external terminal to be exceeded. a step, a step of grouping the external terminal made this subject by the simultaneous operation limit, the subject
External controls converting the external connection buffer of the external terminals to the control circuit buffered, the output state of the external terminals to be the object by controlling the control circuit of the control circuit with a buffer of the external terminals for which the A step of adding a terminal output control circuit and a control external input terminal for controlling the external terminal output control circuit; and sequentially outputting output signals output to the grouped external terminals in a group unit, and Adding the test pattern data for controlling the output state to the test pattern data for controlling the output state so that the output signals of the external terminals of the other groups are not output to the outside; , Is characterized.

[0007]

It is preferable that the insertion position of the test pattern data to be added is immediately before the position where the simultaneous operation limit number of the test pattern data for inspection is exceeded.

Then, the number of test patterns used
Is preferably determined by the number of groupings
No.

Further , in the test method of the present integrated circuit,
Is M, the number of simultaneous operations is N, and the number of simultaneous operations is N,
When N / M is an integer, the group number G is
If N / M is not an integer, round up to the nearest decimal point
Preferably, it is an integer.

That is, according to the present invention, a simulation is performed using test pattern data, and the number of simultaneous operations of the output signal is detected based on the result. The external terminals to be used are divided into groups, the external connection buffer is converted to an external connection buffer with a control circuit, and a control circuit for controlling the output state and a control external terminal are inserted for each group, and data to be supplied to the control circuit. the test side to be added to the test pattern data
It provides the law .

[0012] Simultaneous operation limit number is determined by simulation, and simultaneous operation countermeasures are taken in a short time by automatically changing a buffer for external connection, inserting a control circuit, and adding test pattern data. Integrated circuit design becomes possible.

[0013]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a flowchart of an embodiment of a test method of an integrated circuit according to the present invention, FIG. 2 is a part of a result of a simulation first executed by the test method of the present embodiment, and FIG. FIG. 4 is a diagram showing the layout of the corresponding terminals in FIG. 3 on the chip layout, and FIG. A part of the circuit diagram before correction, (b) is a part of the circuit diagram after correction, and FIG.
FIG. 7 shows a part of the test pattern data to be added, in which the test pattern data to be added is inserted. Hereinafter, embodiments of the present invention will be described.
Will be described.

As shown in FIG. 1, first, connection information 101 for which circuit design has been completed, and test pattern data 102 for inspection.
To execute the simulation 103. Next, based on the result of the simulation 103, the number of simultaneous operations compared with the pattern immediately before each pattern is detected, and it is determined whether the number of simultaneous operations does not exceed the allowable value (104).

If the result of the determination is OK, the operation ends (105). On the other hand, in the case of NG, the NG pattern number and the target external terminal are detected (10).
6). Next, the target external terminals are grouped based on the terminal arrangement data (107). Grouping 107
Is completed, modify the circuit to take measures against simultaneous operation.
8 and correction 109 of the test pattern data. The circuit correction 108 changes the external connection buffer 110.
The change 110 of the external connection buffer changes the external connection buffer connected to the external terminal to a buffer with a control circuit for simultaneous operation countermeasures. At this time, only the external connection buffer detected in the simultaneous operation determination is changed.
Next, control circuit and terminal insertion 111 is performed. The control circuit controls the output state of the external buffer and is controlled by data supplied to a control external terminal. Next, the circuit connection 112 is performed. The circuit connection 112 connects the control circuit and the external buffer according to the grouping. This completes the circuit modification 108. On the other hand, pattern correction 109
First, additional test pattern generation 113 is performed. The additional test pattern generation 113 creates test pattern data for the number of group divisions based on the corrected circuit. Next, test pattern insertion 114 is performed. The insertion 114 of the test pattern
Insert immediately before the test pattern that exceeds the simultaneous operation limit.
The generation 113 and the insertion 114 of the test pattern are repeatedly executed in all places where the simultaneous operation limit is exceeded, to obtain final test pattern data. Finally, the operation confirmation 115 is performed by simulation using the corrected circuit and test pattern data, and if there is no problem, the process ends.

Next, a case where the determination result is NG will be described with a specific example.

FIG. 2 shows a part of the result of the first simulation. As shown in FIG.
The number of simultaneous operations in the pattern No. 1027 of pattern No. 6 is 7, and the limit number of the integrated circuit is determined to be 3. At this time, the pattern No. 1027 exceeds the limit of simultaneous operations. Is NG.

FIG. 3 shows the result of detecting terminals operating simultaneously at the 1027th pattern. OUT1,2,3
Four, six, eight, and seven of IO1 are external terminals subjected to simultaneous operation.

FIG. 4 shows the terminal layout on the chip layout and the target terminals divided into three groups based on the terminal layout.

In FIG. 4, the image of the integrated circuit chip is indicated by reference numeral 1 and the serial number given to the external terminal is indicated by reference numeral 2. As shown in FIG. 4, the grouping is performed by dividing the number of simultaneous operations N by the allowable value M based on the terminal arrangement data on the chip layout.
In this case, since the number of simultaneous operations is 7 and the allowable value is 3, the target terminal is divided into three groups A, B, and C. The division is performed according to the serial number 2 indicating the terminal arrangement information, and groups A, B, and C in ascending order of the numbers. As a result, group A is OUT1, OUT4 and IO1, and group B is O
UT2, OUT6, and group C are OUT3, OUT8.

FIG. 5A shows a part of the circuit diagram before the correction is performed, and FIG. 5B shows a part of the circuit diagram after the circuit correction is performed. FIGS. 5A and 5B show logic circuit blocks 11 and 12. The output buffer 13, the 3-state output buffer 14, and the input / output buffer 15 shown in FIG. 5A are changed to buffers with control circuits in FIG. 5B, respectively.
15a. The external terminals OUT4, OUT1, and IO1 in FIGS. 5A and 5B are denoted by reference numerals 16, 17, and 18, respectively. Output control circuit 1
9 is for controlling the output state of the buffers 13a, 14a and 15a. Control external input terminal CONT
1 and CONT2 are indicated by reference numerals 20a and 20b, respectively. The control terminals 13b, 14b, 15b of the output buffers 13a, 14a, 15a are connected to the terminals D, E, F of the output control circuit 19 in accordance with the grouping.

FIG. 6 shows additional test pattern data corresponding to a circuit changed according to the grouping. FIG.
As shown in the figure, the additional pattern is the same as the number of divisions, ie, three patterns. Control terminals CONT1 and CONT2 are added, and the buffer state is changed from the high impedance (Z) state to the normal operation state in order to measure the groups A, B and C in this order. Mode (0)
Has been changed. Also, the input / output buffers 13a, 13
b and 13c are changed from the high impedance state to the output state by changing the input state and the output buffer to the high impedance state and setting the output state at the time of measurement. The pattern numbers at this time are 1027 ', 1028', and 1029.

FIG. 7 shows test pattern data for inspection whose correction has been completed. FIG. 7 shows a pattern obtained by adding the pattern shown in FIG. 6 to the pattern shown in FIG.
26, the conventional pattern 1027 is deleted, the pattern 1028 is changed to the pattern 1030, and the subsequent patterns are shifted by two patterns. The signals of CNT1 and CNT2 other than the additional pattern are always fixed to the normal operation state (0, 0).

Finally, a simulation is executed based on the changed circuit and test pattern data to confirm that there is no problem, and the flow ends.

The above, to simulate, by linking the result and the terminal arrangement data enables systematization by CA D of <br/>, control circuitry and additional test pattern also generate or modify data easily Automation becomes possible.

[0027]

As described above, according to the present invention, the number of simultaneous operations is detected by simulation, the circuit of the limiting external terminal or the external terminal which has become NG is changed, and the test pattern data is added. In addition, it is possible to minimize the increase of circuits and patterns, and also to take simulations and terminal arrangement data, so that automation can be easily performed, so that simultaneous countermeasures can be performed in a short time without bothering people. Integrated circuit test
There is an effect that can provide a monitoring method .

[Brief description of the drawings]

FIG. 1 is a flowchart of an embodiment of an integrated circuit test method according to the present invention.

FIG. 2 is a part of a result of a simulation first executed by the test method according to the embodiment;

FIG. 3 is a diagram showing a detection result of a pattern and a corresponding terminal that exceed a simultaneous operation restriction allowable value based on a result of the simulation of FIG. 2;

FIG. 4 is an arrangement image of a corresponding terminal in FIG. 3 on a chip layout.

FIG. 5A is a part of a circuit diagram before correction, and FIG. 5B is a part of a circuit diagram after correction.

FIG. 6 shows a part of test pattern data to be added.

FIG. 7 shows a part of test pattern data for inspection into which test pattern data to be added is inserted.

[Explanation of symbols]

 Reference Signs List 1 integrated circuit chip 2 serial number 11, 12 logic circuit block 13 output buffer 13a output buffer with control circuit 13b, 14b, 15b control terminal 14 three-state output buffer 14a three-state output buffer with control circuit 15 input / output buffer 15a control circuit Input / output buffer 16, 17, 18 External terminal 19 Output control circuit 20a, b External input terminal for control 101 Circuit connection information 102 Test pattern data for inspection 103 Simulation 104 Simultaneous operation determination 105 End 106 Applicable pattern and external terminal detection 107 External Terminal grouping 108 Circuit correction 109 Pattern correction 110 External buffer change 111 Control circuit and terminal insertion 112 Circuit connection 113 Additional test pattern generation 114 Test pattern insertion 115 Operation check

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-10-56135 (JP, A) Patent 2899375 (JP, B2) Takahiko Arakawa, 4 others, "Method of reducing simultaneous switching noise in multi-pin ASIC testing""IEICE Technical Report (ICD90 152-157), IEICE, 1990, Vol. 90, No. 350, p. 9-14 (58) Fields surveyed (Int. Cl. ⁷ , DB name) G06F 17/50 666 G06F 17/50 654 G06F 17/50 658 G06F 17/50 670 JICST file (JOIS)

Claims (4)

(57) [Claims] 1. A test method capable of executing an integrated circuit without exceeding a simultaneous operation limit number, wherein a simulation is performed using a plurality of test pattern data in order to check the operation of each output terminal of the integrated circuit. Detecting the number of simultaneous operations of the output signal based on the result of the simulation; comparing the number of simultaneous operations with a preset number of simultaneous operations; and the number of simultaneous operations exceeds the number of simultaneous operations. In case,
A step of detecting the external terminal to be exceeded; a step of grouping the external terminals by the number of simultaneous operations; and converting the external connection buffer of the external terminal into a buffer with a control circuit. And an external terminal output control circuit for controlling the control circuit of the buffer with a control circuit for the external terminal of interest to control the output state of the external terminal of interest and control for controlling the external terminal output control circuit Adding an external input terminal for use, and sequentially outputting output signals output to the grouped external terminals in one group unit, and output signals of external terminals of other groups are not output to the outside. Test pattern data for controlling the output state, and test pattern data for controlling the output state. Adding test pattern data to the test pattern data for inspection. Wherein the insertion position of the test pattern data to be the added is just before part of the portion that exceeds the number of concurrent operation limit of the test the test pattern data, the test method for an integrated circuit of claim 1 Symbol placement. The number of 3. The test pattern used is determined by the number of grouping, a test method for an integrated circuit of claim 1 Symbol placement. 4. When the number of simultaneous operations is M and the number of simultaneous operations is N, the number of groups G is an integer when N / M is an integer. and rounded up integer, it is determined by the test method for an integrated circuit of claim 1 Symbol placement.