JP2003167031A - Ic test device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize an IC test device capable of attaining a high testing rate without any increase in the number of signal conductors. <P>SOLUTION: This IC test device for testing an object to be tested is provided with a plurality of pin electronics cards for giving and receiving signals to and from the tested object, and a daisy chain signal conductor for daisy-chain connecting between the pin electronics cards, thereby performing data transmission. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC tester for testing an object to be tested, such as an IC or an LSI, which is an IC for increasing the test rate without increasing the number of signal lines.
The present invention relates to a test device.

[0002]

2. Description of the Related Art An IC semiconductor test apparatus is an apparatus for applying a test pattern to an IC to be tested, comparing the output of the IC and the expected value pattern, and determining the quality of the IC or the like. Such an apparatus is, for example, "TS6000 20".
MHz Logic LSI Test System "Yokogawa Technical Report, V
ol. 42, 1998, No. 3, p. 89-94 and the like.

An example of such a device will be described below with reference to FIG. In FIG. 6, an object to be tested (hereinafter abbreviated as DUT) 10 is an IC, an LSI or the like. The main body MF is a mainframe, and the capture data memory 40 and the control unit 4
1 is provided. The test head TH is provided with a plurality of pin electronics cards 21 to 2N and a plurality of backplanes 30 to 32 in which the plurality of pin electronics cards 21 to 2N are combined.

The IC pins of the DUT 10 are provided with input pins, output pins and input / output pins. The capture data memory 40 is a storage unit that stores a test result of each IC pin or a plurality of IC pins of the DUT 10. The control unit 41
It outputs a control signal for controlling the flow of signals in the test head TH.

The test head TH has one end connected to the main body MF and the other end connected to the IC pin of the DUT 10. The test head TH intervenes between the main body MF and the IC pin of the DUT 10 to perform signal transfer and signal processing. Further, a detailed configuration of a part of the test result transmission unit of the test head TH is shown in FIG. 7 and will be described.

In FIG. 7, N (N is plural) pin electronics cards 21 to 2N exchange signals with the DUT 10, and m (m is plural) pins PIN, and comparators provided for each pin PIN. CMP, data selector DS, n (n is an integer of 1 or more) signal line L1
To Ln, a driver and the like not shown are provided. The backplane 30 is a pin electronics card 21-2N.
Signal lines B of the same number as the signal lines L1 to Ln provided in
L1 to BLn are provided.

One end of the pin PIN is electrically connected to the IC pin of the DUT 10, and each pin is connected to the IC pin so as not to overlap with other pins.

The comparator CMP has a pin PI on the input side.
The output level from the DUT 10 electrically connected to the other end of N and transmitted through the pin PIN is compared by an analog comparator between "HIGH" and "LOW", and the signal pattern of this comparison result is compared. The expected value pattern is compared with a digital comparator, and the comparison result of the analog comparator or the comparison result of the digital comparator is output.

The input side of the data selector DS is electrically connected to the output side of a plurality of comparators CMP provided for each of the pin electronics cards 21 to 2N. The data selector DS converts the output from the analog comparator of the comparator CMP into capture data which is an n-bit signal, and outputs a desired bit signal according to the control signal of the control unit 41.

Here, the capture data is, for example,
When measuring the linearity of an AD converter with a DUT 10 equipped with an AD converter, first perform AD conversion at full scale, acquire data from the analog comparator, and then perform calculations, but measure at this full scale. It refers to the data that was created. At this time, since the outputs required for measuring the linearity are arbitrary pins of the DUT 10, the data selector D after the comparator CMP is provided.
Selection is made with S.

One end of each of the signal lines L1 to Ln is connected to the output side of each bit of the data selector DS. That is, the output side of the first bit of the data selector DS and one end of the signal line L1 are connected, and the output side of the n-th bit and the signal line L1.
One end of n is connected.

The backplane 30 has a plurality of pin electronics cards 21 to 2N as a set and is electrically connected to each of the pin electronics cards 21 to 2N. One end of each of the signal lines BL1 to BLn is electrically connected to the capture data memory 40, and the other end thereof is electrically connected to each of the other ends of the signal lines L1 to Ln of the plurality of pin electronics cards 21 to 2N. The signals from the pin electronics cards 21 to 2N are transmitted to the capture data memory 40. in this way,
The output signals of the plurality of pin electronics cards 21 to 2N are wired-OR connected by the signal lines BL1 to BLn on the backplane 30.

In such an apparatus, I of the DUT 10
The operation of storing the signal from the C pin in the capture data memory 40 will be described below. The signal from the IC pin of the DUT 10 is input to each comparator CMP via the pin PIN for each pin electronics card 21 to 2N. The comparator CMP uses the analog comparator to "HIGH" or "output" the output level from the pin PIN.
LOW ”and compare the result with the data selector D
Output to S. The data selector DS converts the comparison result into an n-bit signal and outputs the output of the desired bit to the signal lines L1 to Ln according to the signal from the control unit 41.

The signal from the control unit 41 controls the state of the output terminal of the data selector DS provided for each pair of pin electronics cards 21 to 2N. For example, the data selector D provided in the pin electronics card 21
When the output end of the 1st bit of S is set to enable, signals from a plurality of pin electronics cards 21 to 2N are wired-ORed on the backplane 30 and other pin electronics cards 22 to 2N.
The output terminal of the first bit of the data selector DS provided in the above is set to be disabled. Then, the output signals output for each of the paired pin electronics cards 21 to 2N are wired-OR bit by bit on the backplane 30 and transmitted to and stored in the capture data memory 40.

The connection relationship and operation of the other backplanes 31 and 32 are the same as those of the backplane 30, and the description thereof will be omitted.

Output signals from the plurality of backplanes 30 to 32 are stored in the capture data memory 40. Then, the capture data memory 40 may include a data selector function for selecting outputs from the plurality of backplanes 30 to 32.

[0017]

As described above, the DUT1
The signal from the IC pin of 0 is converted into capture data necessary for the test by the data selector DS for each of the pin electronics cards 21 to 2N, and these capture data are signal lines BL1 to B on the back planes 30 to 32.
Wired OR with Ln. In the wired OR connection, there are wiring capacitance and wiring resistance caused by a long wiring length, capacitance generated for each pin electronics card 21 to 2N, reflection of a signal generated at the output terminal of the data selector DS, and the like. Due to these factors, the signal waveform of the capture data, which is the output signal from the pin electronics cards 21 to 2N, is blunted, and if the test rate is increased to increase the signal transmission speed, the signal cannot be transmitted accurately. It was The test rate in such a configuration was, for example, about 20 MHz.

As a method of transmitting a signal at a high test rate, there is a method of transmitting by connecting the output side of the data selector DS and the input side of the capture data memory 40 in a one-to-one manner. However, the pin electronics card 21
A signal line (n x pin electronics card number of cards) is required for each ~ 2N, and the number of signal lines on the backplanes 30 to 32 increases.

There is also a method of providing a logic circuit in the backplanes 30 to 32 instead of a wired OR to OR the outputs of the pin electronics cards 21 to 2N. However, the backplanes 30 to 32 must be provided with almost the same number of active circuits as the pin electronics cards 21 to 2N, which increases the number of components and increases the backplanes 30 to 32.
Will lead to an increase in the mounting area.

Therefore, an object of the present invention is to realize an IC test apparatus capable of transmitting test result data at high speed without increasing the number of signal lines.

[0021]

The invention according to claim 1 is
In an IC test apparatus for testing an object to be tested, a plurality of pin electronics cards for exchanging signals with the object to be tested and a digit chain signal line for connecting the pin electronics cards in a digital chain are provided to perform data transmission. It is characterized by that.

According to a second aspect of the present invention, in the first aspect of the invention, at least one pin electronics card compares the output level of the device under test, and compares the output level comparison result with the expected value pattern. A plurality of comparators, a first timing adjusting unit for inputting data from the daisy chain signal line and adjusting and outputting timing, and a comparison result of the output levels of the plurality of comparators or a comparison result with an expected value pattern are displayed. A second timing adjusting section for inputting, adjusting the timing and outputting, and an output of the first timing adjusting section and an output of the second timing adjusting section in the previous term are inputted, and a logical operation is performed to perform the digit chain signal line. And a logic circuit for outputting to.

According to a third aspect of the present invention, in the second aspect of the invention, the first and second timing adjusting units are at least formed by a FIFO.

The invention according to claim 4 is the same as the invention according to claim 2 or 3, wherein a plurality of comparators and a second comparator are provided.
And a data selector which is provided between the timing adjusting unit and the second timing adjusting unit to select a comparison result of output levels from a plurality of comparators or a comparison result with an expected value pattern. It is what

According to a fifth aspect of the present invention, in the invention according to any one of the second to fourth aspects, it is provided between the digit chain signal line and the first timing adjusting section, and the digit chain signal line is Serial / serial data that is converted to parallel data and output to the first timing adjustment unit
A parallel / serial conversion provided between the parallel converter and the second timing adjustment unit and the digit chain signal line, for converting the parallel data of the second timing adjustment unit into serial data and outputting the serial data to the digit chain signal line. And a container.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram showing a first embodiment of the present invention. Here, the same components as those in FIG. 6 are designated by the same reference numerals, and the description and the illustration thereof will be omitted.

In FIG. 1, the pair of pin electronics cards 21 to 2N are backplanes 30 to 3 respectively.
It is connected in a daisy chain via 2. Digi-chain connection means multiple pin electronics cards 21-2
When Ns are connected to each other, the pin electronics cards 21 to 2N are connected in a daisy chain by individual digit chain signal lines.

That is, the pin electronics card 21
The output side is electrically connected to the input side of the pin electronics card 22 via the backplanes 30 to 32. The output side of the pin electronics card 22 is electrically connected to the input side of the pin electronics card 23 via the backplanes 30 to 32. In this way, the output side of the pin electronics card 2 (N-1) is electrically connected to the input side of the pin electronics card 2N via the backplanes 30 to 32.

Then, the pin electronics card 2N
The output side is electrically connected to the capture data memory 40 via the backplanes 30 to 32. Here, the pin electronics card 21 can be regarded as the most upstream side of the signal flow in the paired pin electronics cards 21 to 2N, and the pin electronics card 2
N can be regarded as the most downstream side.

Next, a specific essential structure of the test head TH according to the present invention will be described with reference to FIG. The same parts as those in FIG. 7 are designated by the same reference numerals, and the description and illustration thereof will be omitted. In FIG. 2, an input signal line 50 including n sets, an output signal line 51 including n sets, and a first FIF.
O (first timing adjustment unit) 52, second FIFO
The (second timing adjustment unit) 53 and the logic circuit 54 are provided for each of the pin electronics cards 21 to 2N. FIFO (First-In-First-Out) is one of the methods of storing and retrieving data, and is a method of retrieving data in the order in which it is stored.

However, the pin electronics card 21, which is the most upstream side of the digital chain connection, may not be provided with any or all of the input side signal line 50 and the FIFOs 52 and 53. FIG. 2 shows a configuration example in which the input side signal line 50 of the pin electronics card 21 is not provided. Also, the digit chain signal line 5 consisting of n
A plurality of 51 to 55N are provided on the backplane 30.

One end of the input side signal line 50 is the input side of the pin electronics cards 22 to 2N. First FI
The input side of the FO 52 is electrically connected to the other end of the input side signal line 50. The input side of the second FIFO 53 is electrically connected to the output side of the data selector DS.

The input side of the logic circuit 54 is the first FIFO.
The output side of 52 and the output side of the second FIFO 53 are electrically connected, and the logical sum of each bit of the signals from the FIFOs 52 and 53 is taken and output. That is, the logical sum of the first bit of the first FIFO 52 and the first bit of the second FIFO 53, the nth bit of the first FIFO 52 and the second FIFO.
The logical sum of the nth bit of 53 is calculated. Output side signal line 51
Has one end connected to the output side of the logic circuit 54 and the other end connected to the output side of the pin electronics cards 21 to 2N.

The digit chain signal lines 551 to 55N provided on the backplane 30 have one end connected to the output side of the pin electronics card 21 to 2N and the other end to the pin electronics card 21 to 2 (N-1). It is connected to the input side of one of the pin electronics cards 22 to 2N on the downstream side. However, the digit chain signal line 55
N has one end connected to the output side of the most downstream pin electronics card 2N and the other end electrically connected to the capture data memory 40.

In such an apparatus, the DUT 10 I
The operation of storing the signal from the C pin in the capture data memory 40 will be described below. The signal from the IC pin of the DUT 10 is input to each comparator CMP via the pin PIN for each pin electronics card 21 to 2N. The comparator CMP uses the analog comparator to set the output level of the DUT 10 to "HIGH" or "LO".
W ”and outputs the comparison result to the data selector DS. The data selector DS converts the comparison results output from the plurality of comparators CMP into an n-bit signal, and outputs the desired result according to the signal from the control unit 41. The output of the bit is input to the second FIFO 53 as capture data.

Here, the pin electronics card 21
Corresponds to the most upstream side of the digit chain connection in the paired pin electronics cards 21 to 2N. First
Since the signal from the DUT 10 is not input to the FIFO 52, the LOW level signal is input in advance.
Then, the first FIFO 52 outputs this signal to the logic circuit 5
Output to 4. Further, the second FIFO 53 outputs the capture data from the data selector DS to the logic circuit 54. Then, the logic circuit 54 uses the first FIFO 52.
The output signal of and the capture data are ORed. Logic circuit 5
The signal logically operated in 4 passes through the output side signal line 51, the digit chain signal line 551, and the input side signal line 50 provided in the pin electronics card 22 one downstream side to the first FIFO 52. Is entered.

Next, the pin electronics card 2
2 is the output signal of the first FIFO 52 and the second FIFO
Synchronize so that the time series of the output signals of 53 are matched,
The signals of the FIFOs 52 and 53 are output to the logic circuit 54.
The logic circuit 54 performs an OR for each bit. Logic circuit 5
The signal logically operated in 4 passes through the output side signal line 51, the digit chain signal line 552, and the input side signal line 50 provided on the pin electronics card 23 which is the downstream side of the own card 22 as described above. The first FIFO 52
Entered in.

Similarly, the pin electronics card 22
The pin electronics cards 23 to 2N on the further downstream side operate until the logic circuit 54 provided in the pin electronics card 2N outputs a signal obtained by logical operation. Signals from the logic circuit 54 of the pin electronics card 2N are output side signal lines 51 and digit chain signal lines 5.
It is transmitted to the capture data memory 40 via 5N.

FIG. 3 is a diagram showing the timing of data among some of the pin electronics cards 21 to 23 (abbreviated as PE cards in FIG. 3). In FIG.
A), C), and G) are pin electronics cards 21.
23 shows the time series data of the capture data output by each of the data selectors DS. B), F)
Represents time-series data in which the signals logically operated by the respective logic circuits 54 of the pin electronics cards 21 and 22 are transmitted by the output side signal line 51. D) and H) are pin electronics cards 22,
23 shows the time series data of the signals output from the respective first FIFOs 52 of 23. E) and I) are the second FIFs of the pin electronics cards 22 and 23, respectively.
The time series data of the signal output by O53 is shown.

As shown in A), C) and G), dat10, dat20 output from the data selector DS.
~, Dat30 ~ are synchronized. As shown in B), dat10 is logically operated by the logic circuit 54 and A).
Is output from the pin electronics card 21 as CD10 after a certain time delay from the time of
It is input to the IFO 52. Therefore, as shown in D) and E), the first FIFO 52 and the second FIFO 53 output so as to synchronize the signals CD10 and dat20.
As a result, the logic circuit 54 can perform a logical operation in synchronization. Then, as shown in F), after a certain time delay from the times of D) and E), it is output from the pin electronics card 22 as CD20-, and the first FIF on the downstream side.
Input to O52. Further, as shown in H) and I), F
The time series data can be synchronized via the IFOs 52 and 53. In this way, the pin electronics card 2N can be synchronized.

The other backplanes 31 and 32 have the same connection relationship and operation as the backplane 30, and therefore their explanations are omitted.

In this way, the paired pin electronics cards 21 to 2N are connected in a daisy chain, and the logic of the signal of the upstream pin electronics card 21 to 2 (N-1) and the capture data of the own card 22 to 2N. The calculation is performed up to the most downstream pin electronics card 2N, and the signal is stored in the capture data memory 40. As a result, each pin electronics card 21-
The number of signal lines connecting between the 2N's does not need to be increased and only n lines are required. Further, since extra capacitance and resistance can be removed, deterioration of the transmission signal can be prevented. Therefore, the test rate can be increased, the high-speed device can be tested, and the test time can be shortened. Specifically, the test rate can be set to 100 MHz or more, high-speed devices of more than 100 HMz can be tested, and the test time can be shortened.

FIG. 4 is a block diagram of a concrete essential part showing a second embodiment of the present invention. 2 that are the same as those in FIG. 2 are denoted by the same reference numerals, and the description and the illustration thereof will be omitted. In FIG. 4, the serial / parallel converter 56, the parallel / serial converter 57, n ′ (n ′ <n) input side signal lines 50 ′, and n ′ output side signal lines 51 ′ are pins. It is provided for each of the electronic cards 21 to 2N.
The n'digit chain signal lines 551 'to 55N' are
A plurality of backplanes 30 are provided.

Here, the input side signal line 50 'and the output side signal line 51' are provided in place of the input side signal line 50 and the output side signal line 51, respectively. In addition, the digit chain signal lines 551 ′ to 55N ′ are the same as the digit chain signal lines 5
It is provided instead of 51-55N.

The serial / parallel converter 56 has an input side electrically connected to the other end of the input side signal line 50 ', and an output side electrically connected to the input side of the first FIFO 52,
The serial signal is converted into an n-bit parallel signal and output. The parallel / serial converter 57 has an input side electrically connected to the logic circuit 54 and an output side connected to the output side signal line 5.
It is electrically connected to one end of 1'and converts an n-bit parallel signal into a serial signal and outputs it.

However, the pin electronics card 21, which is the most upstream side of the digital chain connection, is serial /
The parallel converter 56 may not be provided. FIG. 4 shows a configuration example in which the serial / parallel converter 56 of the pin electronics card 21 is not provided.

One end of each of the digit chain signal lines 551 'to 55N' of the backplane 30 is electrically connected to the other end of the output side signal line 51 'of the pin electronics card 21 to 2N, and the other end is connected to this pin. It is electrically connected to one end of the input side signal line 50 'of the pin electronics cards 22 to 2N downstream of the electronics cards 21 to 2 (N-1).

In such a device, an n-bit parallel signal output from the logic circuit 54 of the pin electronics cards 21 to 2N is converted into a serial signal by the parallel / serial converter 57. The converted signal is output to the output side signal line 51 'and the output side signal line 5
1'is provided in the pin electronics cards 22 to 2N downstream of the pin electronics cards 21 to 2 (N-1) via the digit chain signal lines 551 'to 55N' of the backplane 30. The serial / parallel converter 56 converts the original n-bit parallel signal into the first FIFO 52. The operation other than the signal transmission between the pin electronics 21 to 2N is the same as that of the first embodiment of the present invention, and thus the description thereof is omitted.

In this way, the serial / parallel converter 5
6. Digi-chain connected pin electronics cards 21 to 2 using the parallel / serial converter 57
For signal transmission between N, serial converted data is used.
Accordingly, the digit chain signal lines 551 ′ to 55N ′ on the back planes 30 to 32 can be configured by n ′ lines, which is smaller than n lines, and the number of signal lines can be reduced. Therefore, the backplanes 30 to 32 can be downsized.

FIG. 5 is a specific main part configuration diagram showing a third embodiment of the present invention. Here, the same parts as those in FIG. 7 are designated by the same reference numerals, and the description and the illustration thereof will be omitted. In FIG. 5, the input side signal line 60, the output side signal line 61, the first FIFO (first timing adjustment unit) 62, the second FIFO (second timing adjustment unit) 63, and the OR gate 64 are respectively Pin electronics cards 21-2
It is provided for each N. However, the FIFO 63 is provided for each comparator CMP.

The digit chain signal lines 631 to 63N are
A plurality of backplanes 30 are provided. The pass / fail memory is provided in the main body MF. Furthermore, the pass / fail memory is a capture data memory 4 serving as a storage unit that stores a pass / fail signal indicating whether the DUT 10 has passed or failed.
It is provided instead of 0.

However, the pin electronics card 21, which is the most upstream side of the digital chain connection, need not be provided with any or all of the input side signal line 60 and the FIFOs 62, 63. FIG. 5 shows a configuration example in which the input side signal line 60 of the pin electronics card 21 is not provided.

The configuration shown in FIG. 5 is used, for example, when the information for each IC pin of the DUT 10 is not required and only the pass / fail of the DUT 10 is required. That is, FIG. 2 shows a configuration in which the comparison result of the analog comparator of the comparator CMP is converted into the n-bit capture data required for the test by the data selector DS and is output to the logic circuit 54. However, in FIG. A configuration is shown in which the comparison result of the digital comparator of the comparator CMP is output to the OR gate 64 via the FIFO 53, and the OR gate 64 collectively performs the OR.

Next, the structure of such an apparatus will be described below. One end of the input side signal line 60 is the input side of the pin electronics cards 22 to 2N. FIFO62
Has an input side electrically connected to the other end of the input side signal line 60. The input side of the FIFO 63 is electrically connected to the output side of the comparator CMP.

The input side of the OR gate 64 is the FIFO 62.
Output side and the output sides of the plurality of FIFOs 63 are electrically connected, and the output side is connected to one end of the output side signal line 61. One end of the output side signal line is connected to the output side of the OR gate 64, and the other end is the output side of the pin electronics cards 21 to 2N.

One end of each of the digit chain signal lines 631 to 63N of the backplane 30 is electrically connected to the output side of the pin electronics card 21 to 2N,
The other end is the pin electronics card 21-2 (N-
1) Pin electronics cards 22 to 2 on the downstream side
It is electrically connected to the N input side. However, one end of the digit chain signal line 63N is electrically connected to the output side of the pin electronics card 2N, and the other end is electrically connected to the pass / fail memory.

In such an apparatus, I of the DUT 10
The operation of storing the signal from the C pin in the pass / fail memory will be described below. The signal from the IC pin of the DUT 10 is input to each comparator CMP via the pin PIN for each pin electronics card 21 to 2N. The comparator CMP uses the analog comparator to "HIGH" or "LOW" the output level of the DUT 10.
Then, compare the signal pattern of this comparison result and the expected value pattern with a digital comparator,
The comparison result of this digital comparator is output to the FIFO 63.

Here, the pin electronics card 21
Corresponds to the most upstream side of the digit chain connection in the paired pin electronics cards 21 to 2N. FI
Since the signal from the DUT 10 is not input to the FO 62, a LOW level signal is input, for example. Then, the FIFO 62 outputs this signal to the OR gate 64. Further, the FIFO 63 outputs the comparison result of the digital comparator to the OR gate 64. The OR gate 64 collectively ORs the outputs from the FIFOs 62 and 63.
To do. The signal ORed by the OR gate 64 is the output side signal line 61, the digit chain signal line 631 of the backplane 30, and the pin electronics card 2 on the downstream side.
2 through the input side signal line 60 provided in
62 is input.

Next, the pin electronics card 2
2 is synchronized so that all the time series of the output signals of the FIFO 62 and the output signals of the plurality of FIFOs 63 are synchronized,
The signals of the FIFOs 62 and 63 are output to the OR gate 64. The OR gate 64 collectively ORs the signals. OR
The signal ORed by the gate 64 passes through the output side signal line 61, the digit chain signal line 632, and the input side signal line 60 provided in the pin electronics card 23 which is the downstream side of the own card 22 as described above. And is input to the FIFO 62.

Similarly, the pin electronics card 22
The pin electronics cards 23 to 2N on the further downstream side operate until the OR gate 64 provided in the pin electronics card 2N outputs a logically ORed signal. OR gate 64 of pin electronics card 2N
Is stored in the pass / fail memory via the output side signal line 61 and the digit chain signal line 63N.

The connection relationship and operation of the other backplanes 31 and 32 are the same as those of the backplane 30, and the description thereof will be omitted.

In this way, the paired pin electronics cards 21 to 2N are connected in a daisy chain, and the signals of the upstream pin electronics cards 21 to 2 (N-1) and the output signal of the FIFO 63 of the own card 22 to 2N are connected. Is performed to the pin electronics card 2N on the most downstream side, and the signal is stored in the pass / fail memory.
As a result, each pin electronics card 21 to 2N
The signal line connecting between them is not increased, and the extra capacitance and resistance can be removed, so that the deterioration of the transmission signal can be prevented. Therefore, the test rate can be increased, the high-speed device can be tested, and the test time can be shortened.

The present invention is not limited to this, but may be as follows. The IC test apparatus has various configurations and is not limited to the present embodiment. For example, the present invention includes all of the configurations in which a plurality of outputs are connected by wired OR and are replaced by a daisy chain connection.

The first timing adjusting section and the second timing adjusting section
The timing adjustment unit of the FIFO 52, 53, 62, 6
Although the example using 3 is shown, the FIFO 52, 53, 62,
A flip-flop may be used instead of 63.
In addition, the FIFO 52, 53, 62, 63 and flip
Both flops may be used.

The OR gate 64 has a plurality of FIFs.
Although the output results of O63 are collectively ORed (logical sum), they may be logical circuits that perform logical operations such as AND (logical product) and NAND (negative product).

Further, in this embodiment, as an example, DUT1
An example in which 0 is 1 and the number of backplanes is 3 has been described, but any number (any number) may be used.

Further, the pin electronics cards 21 to 21
The required number of 2N is increased or decreased depending on the number of pins of the DUT 10. For example, when the pin electronics card 22 becomes unnecessary and the pin electronics card 22 is disconnected from the daisy chain signal lines 551 and 552, a switch unit for connecting each of the disconnected daisy chain signal lines 551 and 552 is provided, This switch connects the pin electronics cards 21 and 23,
It may be a daisy chain connection.

2 and 4, the comparator C
The MP outputs the comparison result of the analog comparator to the data selector DS, but it may output the comparison result of the digital comparator to the data selector DS and store the pass / fail signal for each pin of the DUT 10.

[0069]

The present invention has the following effects. According to the first aspect of the present invention, the pin-chain electronic cards are connected by the daisy chain signal lines, so that the test rate can be increased without increasing the number of data transmission signal lines. As a result, a high speed device can be tested and the test time can be shortened.

According to the second to fourth aspects, since the comparison result of the comparator is data-transmitted by the digit chain signal line, the test rate can be increased without increasing the number of data transmission signal lines. . As a result, a high speed device can be tested and the test time can be shortened.

According to the fifth aspect, since the transmission of the digit chain signal line is serial data transmission by the serial / parallel converter and the parallel / serial converter, the number of digit chain signal lines can be further reduced. .

[0072]

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a specific configuration diagram of a main part showing the first embodiment of the present invention.

FIG. 3 is a diagram showing timings of time-series data of a digit chain connection.

FIG. 4 is a specific main part configuration diagram showing a second embodiment of the present invention.

FIG. 5 is a specific main part configuration diagram showing a third embodiment of the present invention.

FIG. 6 is a diagram showing a schematic configuration of a conventional IC test apparatus.

FIG. 7 is a diagram showing in detail the configuration of part of a conventional IC test apparatus.

[Explanation of symbols]

50, 50 ', 60 Input side signal lines 51, 51', 61 Output side signal lines 52, 62 First FIFO 53, 63 Second FIFO 54 Logic circuit 56 Serial / parallel converter 57 Parallel / serial converter 551 ~ 55N, 551 'to 55N', 631 to 63N
Digi-chain signal line 64 OR gate

Continued front page    F term (reference) 2G132 AE10 AE11 AE14 AL05 AL09                 5B061 BA01 BB24 RR03 SS01

Claims (5)

[Claims] 1. An IC test apparatus for testing an object to be tested, comprising a plurality of pin electronics cards for exchanging signals with the object to be tested, and a digit chain signal line for connecting the pin electronics cards in a digital chain. , An IC test apparatus for performing data transmission. 2. The at least one pin electronics card inputs data from a plurality of comparators for comparing output levels of a device under test and comparing an output level comparison result with an expected value pattern. Then, the first timing adjusting section for adjusting and outputting the timing and the second timing for adjusting and outputting the timing by inputting the comparison result of the output levels of the plurality of comparators or the comparison result with the expected value pattern It has an adjusting part and a logic circuit which inputs the output of the first timing adjusting part and the output of the second timing adjusting part in the previous term, performs a logical operation, and outputs the result to a digit chain signal line. Item 1. The IC test apparatus according to Item 1. 3. The IC test apparatus according to claim 2, wherein the first and second timing adjustment sections are configured by at least a FIFO. 4. A second timing adjusting section which is provided between the plurality of comparators and the second timing adjusting section, and selects a comparison result of output levels from the plurality of comparators or a comparison result with an expected value pattern. The IC test apparatus according to claim 2 or 3, further comprising a data selector that outputs the data to the IC tester. 5. A serial / parallel conversion provided between the digit chain signal line and the first timing adjusting section, converting serial data of the digit chain signal line into parallel data, and outputting the parallel data to the first timing adjusting section. And a parallel / serial converter that is provided between the second timing adjustment unit and the digit chain signal line, converts the parallel data of the second timing adjustment unit into serial data, and outputs the serial data to the digit chain signal line. The IC test apparatus according to any one of claims 2 to 4, further comprising: