JP2882743B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device. In particular, the present invention relates to a semiconductor integrated circuit device capable of easily performing a function test and a test method for the semiconductor integrated circuit device.

[0002]

2. Description of the Related Art In recent years, the density and function of semiconductor integrated circuit devices have been remarkably increased, and as a result, the function test of semiconductor integrated circuits has become a major problem. Various test facilitation methods have been proposed to facilitate testing of semiconductor integrated circuit devices. For example, various methods such as a scan path method and a boundary scan method have been proposed and realized.

In recent years, a test facilitation method called a matrix probing method has been proposed. In the matrix probing method, a switch element for reading / writing data is provided at an output terminal of each gate constituting a semiconductor integrated circuit device, and the output signals of all gates are to be observed. ON of each switch element
To control / OFF, a probe line is provided, and a sense line for reading data is provided so as to be orthogonal to the probe line.

FIG. 3 is a plan view of a chip of a semiconductor integrated circuit device using such a matrix probing method. In FIG. 3, P1, P2,... PN denote N probe lines, which are orthogonal to the probe lines P1 to PN, and sense lines S1, S2.
2,... Sm are provided. As shown in FIG. 3, a switch element 10 is provided at each intersection of the probe lines P1 to PN and the sense lines S1 to Sm. As shown in FIG. 3, each switch element 1
0 is controlled ON / OFF by the probe lines P1 to PN, and outputs the output signal of each gate to the sense lines S1 to Sm.

FIG. 4 shows probe lines P1 to PN and sense lines S1 to Sm in a matrix probing method.
A circuit diagram of an example in which a shift register is used for handling is shown. As shown in FIG.
The PN is driven by data held in the shift register 27. The data supplied to the shift register 27 is input via an input terminal 33. The signals appearing on each of the sense lines S1 to Sm are input to the shift register 28, and are serially output from the output terminal 32 by the shift register 28. As described above, by using the shift registers 27 and 28, the number of terminals required for the semiconductor integrated circuit device can be reduced. The shift register 28 connected to the sense lines S1 to Sm is used not only for inputting data but also for writing an initial value to an internal circuit. Such an initial value is stored in the shift register 28 via the input terminal 31, for example.

As described above, in the test by the matrix probing method, since all the output signals of the gates are basically read, the amount of test results becomes enormous.
Therefore, a method of compressing data read from the sense lines S1 to Sm and then reading the data to the outside has been proposed. FIG. 5 shows the sense line S1 for such a purpose.
To Sm, a linear feedback shift register (LF)
(SR) is shown. As shown in FIG. 5, a linear feedback shift register 36 is connected to each of the sense lines S1 to Sm.
As shown in FIG. 5, the linear feedback shift register has a configuration in which feedback is applied to a first stage from a predetermined stage of the shift register. Depending on how this feedback is applied, the linear feedback shift register (hereinafter referred to as LFSR) represents a predetermined so-called generator polynomial. As a result, the value output from the output terminal 43 is the remainder obtained by dividing the signals appearing on the sense lines S1 to Sm by the generator polynomial. With such a configuration, data can be compressed,
Efficient testing becomes possible.

A semiconductor integrated circuit device using the matrix probing method as described above is disclosed in, for example, US Pat.
No. 49947. A similar semiconductor integrated circuit device is also described in JP-A-1-179338.

Further, in US Pat. No. 5,157,627,
In the matrix probing method, there is a description about a method of setting a predetermined initial value in an internal circuit. Also, US Pat. No. 5,179,534 describes a technique for making it easier to set an initial value in an internal circuit in a matrix probing method.

[0009]

As described above, in the conventional semiconductor integrated circuit device of the matrix flowing method, all the output signals from the output terminals of the gates of the internal circuit which is the circuit to be inspected are LFSR ( Generally, since a plurality of sense lines S1 to Sm are connected, M
ISR. Therefore, the data is supplied to the MISR, a predetermined data compression is performed, and a predetermined signature is output from the MISR.

[0010] For this reason, it is necessary to set a specific value for test data for such a conventional semiconductor integrated circuit device in all parts of the internal circuit. If there is inappropriate data or indefinite data, MISR
Tests with signatures output from are unreliable.

Therefore, the test data created for this semiconductor integrated circuit has to determine the value of the whole circuit, and thus becomes an enormous amount of test data.

On the other hand, in the design of a semiconductor integrated circuit,
In many cases, a function is determined for each block. As a result, it is extremely convenient if test data can be created for each block. Further, if test data can be set for each block constituting a circuit, it is expected that test data can be easily created and the total amount of test data is reduced.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a semiconductor integrated circuit device which can output a signature for each block of a circuit in a semiconductor integrated circuit device employing a matrix probing method It is to provide a circuit device.

[0014]

According to the present invention, there is provided a semiconductor device comprising a probe line and a sense line and having a test function by a matrix probing method for reading out a signal value at a measurement point in a circuit. In the integrated circuit device, the MI supplied with the signal on the sense line is
SR, and masking means for masking a signal on the sense line supplied to the MISR for each sense line based on an external control signal, wherein the MISR includes a signal other than the masked sense line. A semiconductor integrated circuit device for calculating a signature for a sense line.

[0015]

According to the present invention, the masking means operates based on a control signal.
A predetermined sense line is masked and is not sent to the MISR. Therefore, the MISR calculates the signature based only on the signal of the unmasked sense line and outputs the signature to the outside.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a semiconductor integrated circuit device according to a preferred embodiment of the present invention. As shown in FIG. 1, a circuit composed of two blocks, a block A and a block B, is provided on a chip of the semiconductor integrated circuit device. In the matrix probing method, probe wires are provided over blocks A and B. On the other hand, sense lines that intersect the probe lines at right angles are provided independently for each of the blocks A and B. A plurality of probe lines and sense lines are provided, respectively.
Are omitted and only one is shown.

A feature of this embodiment is that the sense lines are not directly connected to the MISR 100 but are connected via mask circuits 102a and 102b. This mask circuit 102a is a block A
, And the mask circuit 102b is provided for the block B. That is, all the sense lines arranged in the block A are connected to the mask circuit 102a, and all the sense lines arranged in the block B are connected to the mask circuit 102b.

The mask circuits 102a and 102b are controlled by enable signals EN1 and EN2 from a control circuit 104. The mask circuit 102a is controlled by the enable signal EN1, and the enable signal EN1
Is “High”, the signal on the connected sense line is transmitted to the MISR 100 as it is. Similarly, the mask circuit 102b sets the enable signal EN2 to “Hi”.
gh ”is connected to“ on block B ”
The signal on the sense line is sent to the MISR 100 as it is.
When the enable signals EN1 and EN2 are “Low”, the respective mask circuits 102a and 102
b always supplies a signal of “Low” value to the MISI 100.

The control circuit 104 is a 2-bit register, and a value is externally set in this register.
Then, the two-bit values set from the outside are supplied as they are as enable signals EN1 and EN2 to the mask circuits 102a and 102b, respectively.

As described above, in the semiconductor integrated circuit device according to the present embodiment, the block A
Alternatively, the value of the signal of the sense line from any of the blocks B can be forcibly set to “Low”. Therefore, when creating test data for this semiconductor integrated circuit device, it is possible to independently create test data for only block A and test data for only block B. as a result,
Test data can be created quickly, and the amount of test data can be prevented from becoming enormous. Accordingly, the time required for testing the semiconductor integrated circuit device can be reduced.

FIG. 2 is a circuit diagram of the mask circuits 102a and 102b, which are characteristic configurations of the present embodiment. As shown in FIG. 2, the mask circuit 102a,
Each 102b is composed of a plurality of AND gates 106. One terminal of each AND gate 106 is connected to the enable signal EN1 or EN2,
The other is connected to a sense line from block A or block B. The output signal of each AND gate 106 is supplied to the MISR 100. With such a configuration, the enable signals EN1 and EN2 are set to “High”.
h ", the value of the signal on each sense line is supplied to the MISR 100 as it is, but when the values of the enable signals EN1, EN2 are" Low ", Is not transmitted to the MISR 100, and the signal of the value of “Low” is always supplied to the MISR 100.

A characteristic of this embodiment is that the value of the sense line on the block A or B is forcibly set to "Low" by setting a control signal from the outside, and the value of the "Low" is stored in the MISR 100. Can be supplied. As a result, for example, block A
If it is desired to perform a test on only the block A, the test data is supplied to the block A, and the value of the signal of the sense line on the block B is set to "Low" by setting the enable signal EN2 to "Low". It is possible to have MISR 100 calculate the signature only for the sense lines from block A. When the signature is calculated only for the block B, the enable signal EN2
Is set to “High” and the enable signal EN1 is set to “Lo”.
w ".

As described above, according to the present embodiment, in the semiconductor integrated circuit device employing the matrix probing method, a circuit for masking a sense line from a predetermined block of an internal circuit is provided. It is now possible to calculate a signature for only a desired sense line. Therefore, it is possible to create test data for each block, making it easy to create test data and preventing an enormous amount of test data.

[0025]

As described above, according to the present invention, since the means for masking the sense line is provided, it is possible to calculate the signature only for the desired sense line. As a result, it is possible to create test data for each desired block, for example, so that test data can be easily created and the amount of test data can be prevented from becoming enormous.

Further, by reducing the amount of test data, the time required for the test itself can be shortened.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit device according to a preferred embodiment of the present invention.

FIG. 2 is a detailed circuit diagram of the mask circuits 102a and 102b.

FIG. 3 is a plan view of a semiconductor integrated circuit device using a conventional matrix probing method.

FIG. 4 is an explanatory diagram showing how a shift register is used in a conventional semiconductor integrated circuit device using a matrix probing method.

FIG. 5 is a diagram illustrating a conventional semiconductor integrated circuit device using a matrix probing method.
FIG. 4 is an explanatory diagram showing a state in which an LFSR is connected to a.

[Explanation of symbols]

 100 MISR 102a, 102b Mask circuit 104 Control circuit 106 AND gate

Claims (1)

(57) [Claims] 1. A semiconductor integrated circuit device comprising a probe line and a sense line, and having a test function by a matrix probing method for reading out a signal value at a measurement point inside the circuit, comprising: Masking means for masking a signal on the sense line supplied to the MISR for each sense line based on an external control signal, wherein the MISR comprises a sense line other than the sense line being masked. A semiconductor integrated circuit device for calculating a signature for