JP2638293B2 - LSI and mask layout method for logic circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit LSI / mask layout method for laying out an LSI / mask of a logic circuit in a PLA (Programmable Logic Array) format, and more particularly, to a clock delay inside a logic circuit. The present invention relates to an LIS / mask layout method for a logic circuit including a circuit.

[Prior Art] Conventionally, as a general logic circuit design process for laying out a logic LSI based on a random logic circuit diagram,
Adopt a design process of creating a logic circuit diagram from logic specifications by logic design, then creating an electronic circuit diagram from the logic circuit diagram by electronic circuit design, and creating a layout diagram from the electronic circuit diagram by placement and wiring design. There are many. These design steps are performed in a somewhat automated manner using, for example, a CAD system or the like.

[Problem to be Solved by the Invention] However, in the conventional automatic layout method of random logic, there is a problem that an algorithm for determining wiring routing is complicated and has to rely to some extent on humans. In addition, when a test circuit or the like is incorporated in an LSI, wiring from a measurement point of the logic circuit to the test circuit becomes complicated, and as a result, there is a disadvantage that the circuit cannot be effectively verified.

SUMMARY OF THE INVENTION The present invention has been made to solve such a conventional problem, and provides an LSI / mask layout method of a logic circuit suitable for automation which can regularly lay out a logic circuit including a clock delay circuit. The purpose is to provide.

[Means for Solving the Problems] An LSI / mask layout method for a logic circuit according to the present invention represents an input signal to a plurality of clock delay circuits included in a logic circuit to be laid out and an output signal of the logic circuit, respectively. A step of obtaining a logical expression; a step of converting the obtained logical expression into a product term sum form for simplification; and a step of converting the plurality of product term sum circuits obtained in this step into a programmable logic array form. Laying out and laying out the plurality of clock delay circuits collectively on the output side of the product-term sum circuit, and a test for externally serially accessing the plurality of clock delay circuits laid out in this step. Adding a circuit and applying the simplified logic formula to the laid-out circuit. And providing a wiring based on the information.

[Operation] According to the present invention, a logical expression representing an input signal to the clock delay circuit and an output signal of the logical circuit included in the logical circuit to be laid out is obtained, and these logical expressions are converted to the simplest form of sum of product terms. A logic circuit for implementing the converted and obtained logical formula is configured by PLA. Then, connect the necessary clock delay circuit to the output stage of each product term sum constituting the PLA, and lay out the logic circuit so that the output of the clock delay circuit is fed back to the input side as necessary. I have.

According to the present invention, since a layout based on PLA is performed, a regular layout is possible, and an algorithm such as wiring routing can be simplified, so that automatic layout can be easily performed.

Further, in the present invention, the clock delay circuit is arranged at the output stage of each sum of product terms of the PLA as necessary, so that the random logic up to the clock delay circuit uses a normal PLA layout method. be able to.

In addition, since the clock delay circuits can be collectively arranged on the output side of the product-term sum circuit, for example, by adding a parallel-serial mutual conversion function or the like to the group of clock delay circuits, Since external serial access to the circuit is facilitated, the LSI test function can be easily incorporated, and the test wiring can be simplified.

Furthermore, by laying out the PLA configuration,
Since the output waiting value for an arbitrary input can be obtained by a Boolean equation, it is easy to specify a connection failure point and the like.

Embodiment An embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a flowchart showing a layout method of a logic circuit according to an embodiment of the present invention.

Here, the layout method of this embodiment will be described by taking as an example a case where a logic circuit as shown in FIG. 2 is laid out.

In FIG. 2, an input signal D ₀ is directly input to one input terminal of the AND gate 3 and is input to the other input terminal of the AND gate 3 via the clock delay circuit 1 and the inverter 2. The output of the AND gate 3 is input to the OR gate 4, an AND gate with inverted output the output of the OR gate 4 by the inverter 5 of the input signal D ₃ 6
Has been entered. The output of the AND gate 6 is fed back to the OR gate 4 via the clock delay circuit 7, and the output of the AND gate 6 is transmitted through the clock delay circuit 7.
The signal is input to one input terminal of the D gate 9. The other input terminal of the AND gate 9, the signal through the inverter 8 of the input signal D ₁ is input. The AND gate 10 has A
The output of the ND gate 3 and the input signal D1 are input. AN
Outputs of the D gates 9 and 10 are input to the OR gate 11. O
The output of the R gate 11 and the input signals D ₂ and D ₃ are input to the NAND gate 12. The output and input signal D ₃ of NAND gate 12 are input to the AND gate 13, the output signal ST from the AND gate 13 are outputted. Also NA
The output of the ND gate 12 and the output of the clock delay circuit 7 are input to an AND gate 14, and the AND gate 14 outputs an output signal STP.

Here, the signals respectively input to the clock delay circuits 1 and 7 are D ₀₁ ′ and D ₀₂ ′, and the clock delay circuits
When the processing of FIG. 1 is executed as the signals D ₀₁ and D ₀₂ output from 1, 7 respectively, the following is obtained.

That is, first, from the logic diagram shown in FIG. 2, a logical expression representing each input signal D ₀₁ ′, D ₀₂ ′ to the clock delay circuits 1, 7 and each output signal ST, STP of the logic circuit is obtained. (S1).

The signal D ₀₁ ′ input to the clock delay circuit 1 is
It can be expressed as the following equation (1).

D ₀₁ ′ = D ₀ (1) The input signal D ₀₂ ′ to the clock delay circuit 7
Can be expressed by a logical expression such as the following expression (2) by the inverters 2 and 5, the AND gates 3 and 6, and the OR gate 4.

Similarly, the output signals ST, STP can be represented by the following logical expressions (3) and (4) from the inverter 8, the AND gates 9, 10, 13, 14, the OR gate 11, and the NAND gate 12. it can.

Next, when the above logical expressions (2), (3), and (4) are expanded into logical expressions of sum of product terms by a computer (S2), the following expressions (5), (6), and (7) are obtained, respectively. Can be expressed as

Next, the logical expression of the obtained sum of product terms is subjected to a logical expression simplification process (S3). This simplification process can be easily performed using a well-known algorithm such as a method based on the Carnot diagram, PRESTO, and ESPRESSO.

FIGS. 3 (a), (b), (c) and (d) show the signals respectively.
The Carnot diagram of D ₀₁ ′, D ₀₂ ′, ST, STP is shown.

The above equation (6) can be changed to the following equation (8) by the simplification process.

Subsequently, based on the above equations, the number of gates constituting the product term sum circuit, the position of the clock delay circuit, and the like are determined,
As shown in Fig. 4, a flexible (the number of sum of product terms can be increased as necessary) PLA formula logic diagram is created as a basic layout. In the figure, clock delay circuits 21 and 22
Respectively correspond to the clock delay circuits 1 and 7 in FIG. In addition, inverters 23 to 28 provided in the input stage
And the product term sum circuits 29, 30, 31, 32 provided at the input stage and the previous stage of the output terminal of the clock delay circuits 21, 22, respectively.
These are logics for realizing the above equations (5), (8), and (7), respectively.

Next, a test circuit is added to the clock delay circuit (S5). Specifically, parallel / serial conversion circuits 33 and 34 are added at the subsequent stage of the product term sum circuit, and these parallel / serial conversion circuits 33 and 34 and the clock delay circuits 21 and 22 are connected to each other. Allow access from As a result, operations such as inputting a test pattern from the outside and extracting a test result to the outside can be performed.

Finally, a wiring plot is made on the basic layout of the PLA according to the above equations (5), (8) and (7) (S
6).

By performing each of the above steps,
The layout of the logic LSI in the PLA format as shown in FIG. 5 is completed.

As described above, in the layout method of this embodiment, the random logic up to the input stage of the clock delay circuits 21 and 22 and the random logic up to the output terminal are each configured as a PLA, so that a regular layout can be performed. In addition, there is an advantage that an automatic layout can be easily realized and a test circuit can be easily added.

[Effects of the Invention] As described above, according to the present invention, a unit such as from a clock delay circuit to a clock delay circuit or from an output terminal is grouped together and a layout of a PLA configuration is performed based on the unit. Since a regular layout is possible and an algorithm such as wiring routing can be simplified, there is an effect that automatic layout becomes easy.

Further, according to the present invention, the clock delay circuits can be collectively arranged on the output side of the product-term sum circuit, so that, for example, a parallel-serial mutual conversion function or the like is added to the group of clock delay circuits. Thus, external access to these clock delay circuits can be facilitated. Therefore, the LSI test function can be easily incorporated, and the test wiring can be simplified.

Further, according to the present invention, by laying out the PLA configuration, an output wait value for an arbitrary input can be obtained by a Boolean algebraic expression, so that it is easy to specify a connection failure portion and the like.

[Brief description of the drawings]

FIG. 1 is a flowchart for explaining a method of laying out a logic circuit according to an embodiment of the present invention, FIG. 2 is a block diagram showing a random logic circuit laying out using the method, and FIG. Carnot map diagram showing functions,
FIG. 4 is a block diagram showing a state where the circuit is developed into a basic layout of a PLA, and FIG. 5 is a block diagram showing a state where a test circuit is added and a wiring block is performed on the basic layout. 1,7,21,22 ... clock delay circuit, 2,5,8,23-28 ...
… Inverter, 3,6,9,10,13,14 …… AND gate, 4,11…
… OR gate, 12… NAND gate, 29-32… Product term sum circuit, 33,34… Parallel-serial conversion circuit.

Claims (1)

(57) [Claims] 1. A step of obtaining logical expressions representing input signals to a plurality of clock delay circuits included in a logical circuit to be laid out and an output signal of the logical circuit, respectively, and a product term of the obtained logical expressions. A step of simplifying after conversion into a sum form, laying out a plurality of product term sum circuits obtained in this step in a programmable logic array format, and replacing the plurality of clock delay circuits with the product term sum circuit. Collectively laying out on the output side; adding a test circuit that enables external serial access to the plurality of clock delay circuits laid out in this step; and simplifying the laid out circuit. Providing wiring based on the obtained logical expression. Disk layout method.