CN108134607B - High-speed AD synchronous acquisition circuit and method between boards based on JESD204B - Google Patents

High-speed AD synchronous acquisition circuit and method between boards based on JESD204B Download PDF

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CN108134607B
CN108134607B CN201711380450.8A CN201711380450A CN108134607B CN 108134607 B CN108134607 B CN 108134607B CN 201711380450 A CN201711380450 A CN 201711380450A CN 108134607 B CN108134607 B CN 108134607B
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CN108134607A (en
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崔艳松
冯洋
孙东方
付常焜
刘思庆
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Beijing Huahang Radio Measurement Research Institute
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H03M1/123—Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods
    • H03M1/1255—Synchronisation of the sampling frequency or phase to the input frequency or phase

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Abstract

The invention provides a high-speed AD synchronous acquisition circuit and a synchronization method between boards based on JESD204B, wherein the acquisition circuit comprises a synchronous control board and K acquisition boards, the synchronous control board is respectively connected with each acquisition board and provides synchronous control signals with consistent time sequence and synchronous reference clocks which are homologous with an AD external sampling clock for each acquisition board, so that synchronous multi-path AD acquisition between the K acquisition boards is realized. The acquisition circuit adopts a modular design, and can be repeatedly stacked by multiple plates; the application range is wide, and the method is suitable for any ADC chip based on JESD 204B; the circuit is simple, effective and reliable, and effectively solves the contradiction between system miniaturization and gradual improvement of system performance index requirements.

Description

High-speed AD synchronous acquisition circuit and method between boards based on JESD204B
Technical Field
The invention belongs to the technical field of signal processing, and particularly relates to an inter-board high-speed AD synchronous acquisition circuit and a synchronization method based on JESD 204B.
Background
The traditional sampling data adopts a multi-channel data line parallel transmission mode, is easily influenced by intersymbol synchronization and crosstalk, has complex PCB wiring, and is difficult to meet the requirements of a multi-channel, high-bandwidth and miniaturized data transmission terminal. Currently, analog-to-digital converters (ADCs) are undergoing a transition from parallel LVDS (low voltage differential signaling) and CMOS digital interfaces to high-speed serial interfaces.
The JESD204B is a high-speed serial interface protocol, is mostly used for data transmission between a high-speed analog-digital converter and a back-end digital signal processing device, and under the same performance index, the analog-digital converter (ADC) adopting the JESD204B protocol is reduced by 75% compared with the traditional parallel analog-digital converter, the protocol is developed on the basis of the JESD204 and the JESD204A protocols, and has the advantages of different first two generations as a 3 rd generation high-speed serial converter interface protocol, the deterministic delay of each converter in the system can be established, and a multi-path ADC acquisition system is easier to establish.
With the enhancement of the miniaturization requirement of the system, the sampling requirement of the system which cannot be met by the traditional multi-path data line parallel ADC data transmission mode is adopted.
Disclosure of Invention
Aiming at the problems, the invention provides an inter-board high-speed AD synchronous acquisition circuit and a synchronous method based on JESD204B, and solves the problem of multi-path ADC inter-board synchronous acquisition based on JESD 204B.
The technical scheme of the invention is as follows:
a high-speed AD synchronous acquisition circuit between boards based on JESD204B comprises a synchronous control board and K acquisition boards;
the K acquisition boards are identical IN structure, each acquisition board is provided with N AD acquisition channels, and AD synchronous acquisition of multiple paths of analog signals is realized under the control of an AD external sampling clock ADCLK _ IN and a control signal output by the synchronous control board;
the synchronous control board is respectively connected with each acquisition board, and provides synchronous control signals SYNC _ IN with consistent time sequence and synchronous reference clocks SYNC _ REFCLK _ OUT with the AD external sampling clock for each acquisition board, so that multi-path AD synchronous acquisition is realized among K acquisition boards.
Furthermore, each acquisition board comprises an FPGAaThe AD circuit and the clock generating chip;
the FPGAaUnder the control of a synchronous control signal SYNC _ IN and a synchronous reference clock SYNC _ REFCLK _ OUT output by the synchronous control board, a configuration signal is output, and a clock generating chip and an AD circuit are configured;
the AD circuit is composed of N AD devices AD connected in parallel1～ADNThe method comprises the following steps of (1) carrying out AD sampling on N paths of analog signals;
the clock generation chip HM7043FPGAaAccording to the input AD external sampling clock ADCLK _ IN, output AD and ADAnd the multi-path clock signals required by step sampling comprise N paths of AD sampling clocks and N paths of AD reference clocks.
Further, the frequency phase of the AD external sampling clock ADCLK _ IN is consistent with that of the N-way AD sampling clock; the phases of the N paths of AD sampling clocks are consistent with the phases of the N paths of AD reference clocks.
Further, the clock generation chip uses the AD external sampling clock ADCLK _ IN to FPGAaAnd the configuration signals output to the clock generation chip are sampled, and the output multi-path clock signals are synchronized by the high-low clock edge of the configuration signals, so that the phases of the N paths of AD sampling clocks are consistent with the phases of the N paths of AD reference clocks.
Further, the FPGAaUnder the control of a synchronous trigger signal SYNC _ IN and a synchronous reference clock SYNC _ REFCLK _ OUT which are output by the synchronous control board and correspond to the acquisition board, the AD of an AD device IN the acquisition board is controlled through an N-path SPI control interface, a JESD204B high-speed serial interface and a link initialization signal1～ADNData sampling is performed.
Further, the link initialization signal is an initialization signal of an N-way JESD204B high-speed serial interface, and when the N-way link initialization signal is changed from low to high, the AD device AD is connected with the first end of the N-way JESD204B high-speed serial interface1～ADNAnd FPGAaInitializing the high-speed serial interface of the N paths of JESD 204B; after the initialization is successful, the N-path JESD204B high-speed serial interface transmits AD sampling data; the N-path SPI control interface is used for adjusting AD device AD1～ADNAnd the middle N paths of AD reference clock delayer parameters.
Furthermore, the synchronous control board consists of a clock chip and an FPGAbComposition is carried out;
the clock chip receives an external clock input signal SYNC _ REFCLK _ IN and generates a synchronous reference clock SYNC _ REFCLK _ OUT; respectively conveyed to a K-block acquisition board and an FPGAb(ii) a The SYNC _ REFCLK _ IN is a local oscillator clock for generating the AD external sampling clock ADCLK _ IN;
the FPGAbUnder the control of SYNC _ REFCLK _ OUT, synchronous input signals SYNC _ IN are generated and respectively transmitted to K acquisition boards.
Further, the frequency of the synchronous reference clock SYNC _ REFCLK _ OUT is 1/128 of the frequency of the AD external sampling clock ADCLK _ IN, and the phase of the synchronous reference clock SYNC _ REFCLK _ OUT coincides with the external clock input signal SYNC _ REFCLK _ IN;
the synchronous input signal SYNC _ IN is a single pulse, and the pulse width is SYNC _ REFCLK _ OUT clock period; and the synchronous input signal SYNC _ IN is output to the K acquisition boards for synchronization at the falling edge of the clock of the synchronous reference frequency SYNC _ REFCLK _ OUT. Furthermore, the wiring lengths of the N paths of AD sampling clocks and the N paths of AD reference clocks of each acquisition board in the K acquisition boards are equal; the length of SYNC _ IN wiring respectively connected with each acquisition board is equal; the wiring lengths of the synchronous reference clocks SYNC _ REFCLK _ OUT respectively connected with each acquisition board are equal.
A synchronization method of an inter-board high-speed AD synchronous acquisition circuit based on JESD204B comprises the following steps:
step 1, outputting a synchronous reference clock SYNC _ REFCLK _ OUT by a clock chip in a synchronous control board to control the FPGAbGenerating SYNC _ IN and outputting the SYNC _ IN to each acquisition board, and receiving the SYNC _ IN by each acquisition board simultaneously; the clock chip outputs SYNC _ REFCLK _ OUT to each acquisition board, and each acquisition board receives SYNC _ REFCLK _ OUT simultaneously;
step 2, FPGA of each acquisition boardaAfter receiving a corresponding synchronous reference clock SYNC _ REFCLK _ OUT and a synchronous trigger signal SYNC _ IN transmitted by a synchronous control board, generating a synchronous signal CLK _ SYNC _ IN of a clock generation chip, and enabling N paths of AD sampling clocks generated by the clock generation chip to be consistent with N paths of AD reference clocks IN phase;
step 3, collecting FPGA of the boardaThrough SPI control interface, adjust AD device AD1～ADNThe parameters of the middle N paths of AD reference clock delayers enable the relative phase relation between the N paths of AD sampling clocks and the N paths of AD reference clocks to meet the time sequence requirement;
step 4, collecting FPGA of the boardaInitializing the N-path JESD204B high-speed serial interface of the AD device through a link initialization signal;
and 5, after the initialization is successful, performing data sampling on all AD devices of the K acquisition boards, and realizing the synchronous acquisition of the high-speed AD between the boards.
According to the technical scheme, the invention has the beneficial effects that:
the synchronous acquisition among multiple ADC boards based on the JESD204B is realized; the modular design is adopted, and multiple plates can be repeatedly stacked; the application range is wide, and the method is suitable for any ADC chip based on JESD 204B; the circuit is simple, effective and reliable, and solves the contradiction between system miniaturization and gradual improvement of system performance index requirements.
Drawings
Fig. 1 is a schematic diagram of an inter-board high-speed AD synchronous acquisition circuit based on JESD 204B.
Detailed Description
The technical solution of the present invention will be further explained and explained in detail with reference to the accompanying drawings.
The technical scheme of the invention is described as follows:
a high-speed AD synchronous acquisition circuit between boards based on JESD204B is shown in figure 1 and comprises a synchronous control board and K acquisition boards 1-K;
the K acquisition boards are identical in structure, each acquisition board is provided with N AD acquisition channels, AD synchronous acquisition of multiple paths of analog signals is realized under the control of an AD external sampling clock and a control signal output by the synchronous control board, and a high-speed AD synchronous acquisition circuit consisting of the K acquisition boards has N x K AD acquisition channels;
the synchronous control board is respectively connected with each acquisition board, provides synchronous control signals SYNC _ IN with consistent time sequence and synchronous reference clocks SYNC _ REFCLK _ OUT with the same source of the AD external sampling clock for each acquisition board, and realizes synchronization of AD acquisition of multi-channel analog signals among the K acquisition boards.
Each acquisition board comprises a clock generation chip HM7043, an AD circuit and an FPGAa；
The FPGAaA clock generation chip HM7043 and an AD circuit are configured under the control of the output signal of the synchronous control board;
the clock generation chip HM7043 is in FPGAaAccording to the input AD external sampling clock, the time required for AD synchronous sampling is generatedA clock signal;
the AD circuit is composed of N AD devices AD connected in parallel1～ADNThe method comprises the following steps of (1) carrying out AD sampling on N paths of analog signals;
specifically, the clock generation chip HM7043 is in FPGAaUnder the control of the output CLK _ SYNC _ IN signal, providing N paths of AD sampling clocks and N paths of AD reference clocks for the AD circuit according to an AD external sampling clock ADCLK _ IN; the N-way AD sampling clock ADCLK _ OUT1～ADCLK_OUTNRespectively with AD in AD devices1～ADNConnected, the N-path AD reference clock AD _ REFCLK1～AD_REFCLKNAlso respectively AD device1～ADNConnecting;
specifically, the clock generation chip HM7043 operates IN the interface protocol specific mode of the JESD204B, and the AD external sampling clock ADCLK _ IN and the N-way AD sampling clock ADCLK _ OUT1～ADCLK_OUTNThe frequency and the phase of the signals are consistent; the phases of the N paths of AD sampling clocks are consistent with the phases of the N paths of AD reference clocks, and the frequency value of the N paths of AD reference clocks is 1/128 of the frequency value of the N paths of AD sampling clocks;
specifically, the clock generation chip HM7043 uses ADCLK _ IN to FPGAaThe output CLK _ SYNC _ IN signal is sampled, and multiple clock signals are synchronized by the high-low clock edge IN the CLK _ SYNC _ IN signal, so that the N paths of AD sampling clocks ADCLK _ OUT1～ADCLK_OUTNAnd an N-way AD reference clock AD _ REFCLK1～AD_REFCLKNThe phases are consistent. In particular, to ensure that the K acquisition boards can perform cooperative sampling, the N-way AD sampling clock ADCLK _ OUT of each of the K acquisition boards1～ADCLK_OUTNAnd an N-way AD reference clock AD _ REFCLK1～AD_REFCLKNThe wiring lengths are equal, and the relative phase relationship of two clocks reaching the AD circuits of the acquisition boards is ensured to be consistent.
FPGA in the acquisition boardaUnder the control of a synchronous trigger signal SYNC _ IN and a synchronous reference clock SYNC _ REFCLK _ OUT which are output by the synchronous control board and correspond to the acquisition board, the synchronous trigger signal SYNC _ IN and the synchronous reference clock SYNC _ REFCLK _ OUT are controlled by an SPI control interface, a JESD204B high-speed serial interface and an N-way link initialization signal AD _ SYNC _ OUT1～AD_SYNC_OUTNControlling AD of AD devices in the acquisition board1～ADNData sampling is performed.
The N-way link initialization signal AD _ SYNC _ OUT1～AD_SYNC_OUTNIs an initialization signal of the JESD204B high-speed serial interface when the N-way AD _ SYNC _ OUT1～AD_SYNC_OUTNSignal from low to high, AD device AD1～ADNAnd FPGAaInitializing a high-speed interface; after the initialization is successful, the JESD204B high-speed serial interface transmits AD sampling data; the SPI control interface is used for adjusting AD device1～ADNAnd the N paths of AD reference clock delayer parameters are used for changing the relative phase relation between the N paths of AD sampling clocks and the N paths of AD reference clocks and meeting the time sequence requirement.
In particular, the FPGAaAnd sampling the synchronous trigger signal SYNC _ IN by using the corresponding rising edge of the synchronous reference clock SYNC _ REFCLK _ OUT transmitted by the synchronous control board, and synchronizing the SYNC _ IN by using the SYNC _ REFCLK _ OUT at an output port to be used as the synchronous trigger signal of the HM 7043.
The synchronous control panel is composed of a clock chip and an FPGAbComposition is carried out;
the clock chip receives an external clock input signal SYNC _ REFCLK _ IN and generates a synchronous reference clock SYNC _ REFCLK _ OUT0～SYNC_REFCLK_OUTK(ii) a Wherein the synchronous reference clock SYNC _ REFCLK _ OUT1～SYNC_REFCLK_OUTKTo the corresponding collecting plate 1-K;
the FPGAbAt SYNC _ REFCLK _ OUT0Under the control of (2), a completely consistent synchronous input signal SYNC _ IN is generated1～SYNC_INKTo the corresponding collecting plate 1-K;
specifically, the synchronous reference clock SYNC _ REFCLK _ OUT0～SYNC_REFCLK_OUTKAt 1/128 times the frequency of the AD external sampling clock ADCLK _ IN, the synchronous reference frequency SYNC _ REFCLK _ OUT0～SYNC_REFCLK_OUTKCoincides with the external clock input signal SYNC _ REFCLK _ IN.
In particular, the synchronous reference clock SYNC _ REFCLK _ OUT0～SYNC_REFCLK_OUTKHave equal wiring length and ensure to reach each FPGAaThe time of the first and second switches is consistent; SYNC _ REFCLK _ IN is a local oscillator clock that generates AD external sampling clock ADCLK _ IN.
Specifically, the synchronous input signal SYNC _ IN1～SYNC_INKIs a SYNC _ REFCLK _ OUT0High pulse of clock period and use SYNC _ REFCLK _ OUT at output port0The falling edge of the clock is output to the corresponding acquisition boards 1-K for synchronization.
IN particular, the SYNC _ IN wiring lengths should be equal to ensure consistent arrival times at the FPGAa of each acquisition board.
A synchronization method of an inter-board high-speed AD synchronous acquisition circuit based on JESD204B comprises the following steps:
step 1, outputting a synchronous reference clock SYNC _ REFCLK _ OUT by a clock chip in a synchronous control board0Controlling an FPGAbThe generated SYNC _ IN is respectively output to the acquisition boards 1-K; clock chip output SYNC _ REFCLK _ OUT1～SYNC_REFCLK_OUTKTo the corresponding collecting plate 1-K;
step 2, collecting the FPGA of the board 1-KaReceiving the corresponding synchronous reference clock SYNC _ REFCLK _ OUT transmitted by the synchronous control board1～SYNC_REFCLK_OUTKAnd a synchronous trigger signal SYNC _ IN, which generates a synchronous signal CLK _ SYNC _ IN of the HMC7043, so that the phases of the N paths of AD sampling clocks of the acquisition boards 1-K are consistent with the phases of the N paths of AD reference clocks;
step 3, collecting the FPGA of the board 1-KaThrough SPI control interface, adjust AD device AD1～ADNThe parameters of the middle N paths of AD reference clock delayers enable the relative phase relation between the N paths of AD sampling clocks and the N paths of AD reference clocks to meet the time sequence requirement;
step 4, collecting the FPGA of the board 1-KaInitializing a high-speed serial interface with an AD circuit;
step 5, after the initialization is successful, the AD of the acquisition boards 1-K starts to carry out synchronous data sampling, and the synchronous data sampling is carried out on the FPGAaAnd transmitting the data.
According to the introduction of the above specific embodiments, the invention realizes the synchronous acquisition among multiple ADC boards based on JESD 204B; the modular design is adopted, and multiple plates can be repeatedly stacked; the application range is wide, and the method is suitable for any ADC chip based on JESD 204B; the circuit is simple, effective and reliable, and solves the contradiction between system miniaturization and gradual improvement of system performance index requirements.
The above-mentioned embodiments are only used for explaining and explaining the technical solution of the present invention, but should not be construed as limiting the scope of the claims. It should be clear to those skilled in the art that any simple modification or replacement based on the technical solution of the present invention will also result in new technical solutions that fall within the scope of the present invention.

Claims (8)

1. A high-speed AD synchronous acquisition circuit between boards based on JESD204B is characterized by comprising a synchronous control board and K acquisition boards;
the K acquisition boards are identical IN structure, each acquisition board is provided with N AD acquisition channels, and AD synchronous acquisition of multiple paths of analog signals is realized under the control of an AD external sampling clock ADCLK _ IN and a control signal output by the synchronous control board;
the synchronous control board is respectively connected with each acquisition board, and provides synchronous control signals SYNC _ IN with consistent time sequence and synchronous reference clocks SYNC _ REFCLK _ OUT which are homologous with the AD external sampling clock for each acquisition board, so that multi-path AD synchronous acquisition is realized among K acquisition boards;
each acquisition board comprises an FPGAaThe AD circuit and the clock generating chip;
the FPGAaUnder the control of a synchronous control signal SYNC _ IN and a synchronous reference clock SYNC _ REFCLK _ OUT output by the synchronous control board, a configuration signal is output, and a clock generating chip and an AD circuit are configured;
the AD circuit is composed of N AD devices AD connected in parallel1～ADNThe method comprises the following steps of (1) carrying out AD sampling on N paths of analog signals;
the clock generation chip HM7043 is in FPGAaUnder the configuration of (2), according to the input AD external sampling clock ADCLK _ IN, outputting a plurality of clock signals required by AD synchronous sampling, including N paths of AD samplingA clock and an N-way AD reference clock;
the synchronous control panel is composed of a clock chip and an FPGAbComposition is carried out;
the clock chip receives an external clock input signal SYNC _ REFCLK _ IN and generates a synchronous reference clock SYNC _ REFCLK _ OUT; respectively conveyed to a K-block acquisition board and an FPGAb(ii) a The SYNC _ REFCLK _ IN is a local oscillator clock for generating the AD external sampling clock ADCLK _ IN;
the FPGAbUnder the control of SYNC _ REFCLK _ OUT, synchronous input signals SYNC _ IN are generated and respectively transmitted to K acquisition boards.
2. The synchronous acquisition circuit of claim 1,
the AD external sampling clock ADCLK _ IN is consistent with the frequency phase of the N paths of AD sampling clocks; the phases of the N paths of AD sampling clocks are consistent with the phases of the N paths of AD reference clocks.
3. The synchronous acquisition circuit of claim 2, wherein the clock generation chip uses the AD external sampling clock ADCLK _ IN to FPGAaAnd the configuration signals output to the clock generation chip are sampled, and the output multi-path clock signals are synchronized by the high-low clock edge of the configuration signals, so that the phases of the N paths of AD sampling clocks are consistent with the phases of the N paths of AD reference clocks.
4. The synchronous acquisition circuit of claim 2, wherein the FPGA is configured to operate in a single modeaUnder the control of a synchronous trigger signal SYNC _ IN and a synchronous reference clock SYNC _ REFCLK _ OUT which are output by the synchronous control board and correspond to the acquisition board, the AD of an AD device IN the acquisition board is controlled through an N-path SPI control interface, a JESD204B high-speed serial interface and a link initialization signal1～ADNData sampling is performed.
5. The synchronous acquisition circuit of claim 4, wherein the link initialization signal is an initialization signal of an N-way JESD204B high-speed serial interface, when the N-way link initialization signal is detectedWhen the voltage is changed from low to high, the AD device AD1～ADNAnd FPGAaInitializing the high-speed serial interface of the N paths of JESD 204B; after the initialization is successful, the N-path JESD204B high-speed serial interface transmits AD sampling data; the N-path SPI control interface is used for adjusting AD device AD1～ADNAnd the middle N paths of AD reference clock delayer parameters.
6. The synchronous acquisition circuit of claim 1,
the frequency of the synchronous reference clock SYNC _ REFCLK _ OUT is 1/128 of the frequency of the AD external sampling clock ADCLK _ IN, and the phase of the synchronous reference clock SYNC _ REFCLK _ OUT coincides with the external clock input signal SYNC _ REFCLK _ IN;
the synchronous input signal SYNC _ IN is a single pulse, and the pulse width is SYNC _ REFCLK _ OUT clock period; and the synchronous input signal SYNC _ IN is output to the K acquisition boards for synchronization at the falling edge of the clock of the synchronous reference frequency SYNC _ REFCLK _ OUT.
7. The synchronous acquisition circuit of any of claims 1-6,
the wiring lengths of the N paths of AD sampling clocks and the N paths of AD reference clocks of each acquisition board in the K acquisition boards are equal; the length of SYNC _ IN wiring respectively connected with each acquisition board is equal; the wiring lengths of the synchronous reference clocks SYNC _ REFCLK _ OUT respectively connected with each acquisition board are equal.
8. A synchronization method using the high-speed AD synchronous acquisition circuit between boards based on JESD204B as claimed in any one of claims 1-7, which is characterized by comprising the following steps:
step 1, outputting a synchronous reference clock SYNC _ REFCLK _ OUT by a clock chip in a synchronous control board to control the FPGAbGenerating SYNC _ IN and outputting the SYNC _ IN to each acquisition board, and receiving the SYNC _ IN by each acquisition board simultaneously; the clock chip outputs SYNC _ REFCLK _ OUT to each acquisition board, and each acquisition board receives SYNC _ REFCLK _ OUT simultaneously;
step 2, FPGA of each acquisition boardaReceive synchronous controlAfter the corresponding synchronous reference clock SYNC _ REFCLK _ OUT and the synchronous trigger signal SYNC _ IN are transmitted by the board, a synchronous signal CLK _ SYNC _ IN of the clock generation chip is generated, so that the phases of N paths of AD sampling clocks generated by the clock generation chip are consistent with the phases of N paths of AD reference clocks;
step 3, collecting FPGA of the boardaThrough SPI control interface, adjust AD device AD1～ADNThe parameters of the middle N paths of AD reference clock delayers enable the relative phase relation between the N paths of AD sampling clocks and the N paths of AD reference clocks to meet the time sequence requirement;
step 4, collecting FPGA of the boardaInitializing the N-path JESD204B high-speed serial interface of the AD device through a link initialization signal;
and 5, after the initialization is successful, performing data sampling on all AD devices of the K acquisition boards, and realizing the synchronous acquisition of the high-speed AD between the boards.
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