CN102436735B - B type LXI (LAN eXtensions for Instrumentation) synchronous data acquisition instrument - Google Patents
B type LXI (LAN eXtensions for Instrumentation) synchronous data acquisition instrument Download PDFInfo
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- CN102436735B CN102436735B CN 201110454671 CN201110454671A CN102436735B CN 102436735 B CN102436735 B CN 102436735B CN 201110454671 CN201110454671 CN 201110454671 CN 201110454671 A CN201110454671 A CN 201110454671A CN 102436735 B CN102436735 B CN 102436735B
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Abstract
The invention relates to a B type LXI (LAN eXtensions for Instrumentation) synchronous data acquisition instrument, comprising a B type LXI interface module, a synchronous data acquisition instrument function module and an LED (Light-emitting Diode) indication module, wherein the B type LXI interface module comprises an embedded type processor circuit, an IEEE (Institute of Electrical and Electronic Engineers) 1588 triggering management circuit, a FLASH storage circuit, a DDR (Double Data Rate) dynamic storage circuit and an LAN (Local Area Network) interface communication circuit; and an analog acquisition circuit is used for acquiring an analog signal, carrying out programmable gain and programmable filtering on the analog signal, and then carrying out AD (Analog to Digital) sampling and transmitting sampling data into an FPGA (Filed Programmable Gate Array) control circuit. The FPGA control circuit is used for simulating operation control of an acquisition channel; an SDRAM (Synchronous Dynamic Random Access Memory) is used for storing and acquiring conversion data; and a PCI (Programmable Communication Interface) is used for connecting the B type LXI interface module and the synchronous data acquisition instrument function module. According to the invention, based on an LXI bus standard, the B type LXI synchronous data acquisition instrument is provided.
Description
Technical field
The present invention relates to a kind of category-B LXI bus synchronous data acquisition instrument circuit.
Background technology
Agilent and VXI Technology company have proposed a kind of new instrument bus-LXI (LAN eXtensions for Instrumentation) in 2004.The LXI instrument need not be special core bus cabinet and Zero greeve controller, directly utilize the standard LAN interface of universal PC, reduced the development and application cost to a great extent.And LAN to be industry the most stable and life cycle is the longest and in the continuous opened industrial standard of development, each manufacturer is easy to existing instrument product is transplanted on the LAN platform, and these all provide convenience for setting up wider distributed automatic measuring and controlling system.The LXI bus standard has defined the chronometer time synchronizing function based on IEEE1588 simultaneously, has introduced the notion based on Time Triggered for the first time in the thermometrically field, is easy to make up real-time testing system.
Along with quick development of modern science and technology, especially more and more higher in Aero-Space, military field for amplitude, the accuracy requirement of signals collecting, the user is also more and more higher to the requirement that data are gathered product, particularly in distributed measurement and control system, also require testing tool to have the programming remote control function, existing bus such as GPIB, PCI/PXI etc. can't well meet the demands, in order to satisfy the distributed test system demand of user for collection of simulant signal high precision, multichannel synchronousing collection, the synchronous data collection card of LXI bus arises at the historic moment.This category-B LXI bus synchronous data acquisition instrument circuit has 8 end lists or differential path, the collection of can running simultaneously, and every passage all can be realized the highest sampling of 2MSa/s.And the IEEE 1588 chronometer time synchronous protocols that the category-B instrument of LXI bus is had have been realized the Remote triggering synchronizing function of instrument in nanosecond, can play a significant role in ATS (Automatic Test System).
Summary of the invention
The present invention is based on the LXI bus standard, a kind of category-B LXI synchronous data collection instrument is provided.
Technical solution of the present invention:
Category-B LXI synchronous data collection instrument, its special character is: comprise category-B LXI interface module, synchronous data collection instrument functional module and LED indicating module;
Category-B LXI interface module comprises that flush bonding processor circuit, IEEE 1588 trigger management circuit, FLASH memory circuit, DDR dynamic memory circuit and LAN interface telecommunication circuit;
The flush bonding processor circuit is the network interface that is used to provide with the control computer communication, realizes the LXI bus protocol that procedure stores is relevant with processing;
IEEE 1588 triggers management circuit and is used to handle 1588 agreements, manages 1588 associated trigger and extraction time and stabs;
The FLASH memory circuit is used for memory system data and application program;
The DDR dynamic memory circuit is used for the dynamic memory process data, for the reading of application program, carry out buffering is provided;
The LAN interface telecommunication circuit provides the hardware path with the control computer communication;
Synchronous data collection instrument functional module comprises pci interface, analog acquisition circuit, FPGA control circuit and SDRAM memory circuit,
The analog acquisition circuit is used to gather simulating signal, simulating signal is carried out programme-controlled gain and program control filtering, carries out the AD sampling again, and imports sampled data into the FPGA control circuit;
The FPGA control circuit is used for the operation control of analog acquisition passage;
The SDRAM storer is used for the storage of collected translation data;
Pci interface is used for being connected of category-B LXI interface module and synchronous data collection instrument functional module.
Above-mentioned flush bonding processor circuit comprises PowerPC processor U1, described PowerPC processor U1 comprises internal bus interface U1A, DDR sdram controller interface U1B, local bus interface U1C, network MAC interface U1G, major clock and IO mouth U1D, described internal bus interface U1A and pci interface 2 communicate to connect, and described DDRSDRAM control unit interface U1B provides address, data and control link for the DDR dynamic memory circuit; Described local bus interface U1C provides interface for the FLASH memory circuit, described network MAC interface U1G provides two-way adaptive network path, and the first via links to each other with the LAN interface telecommunication circuit, the second tunnel be used for triggering PPS clock and the I/O port that management circuits provide IEEE 1588 agreements to IEEE 1588; Major clock is used to the clock input of PowerPC processor among described major clock and the IO mouth U1D, and the IO mouth is used for triggering management circuit to IEEE 1588 to be provided triggering passage and provide control port to the LED indicating module.
Above-mentioned category-B LXI interface module also comprises the GPIB/USB interface circuit that is used to realize GPIB/USB hardware path, and local bus interface U1C also provides interface for the gpib interface circuit, and described GPIB/USB interface circuit is connected with local bus interface U1C.
4, category-B LXI synchronous data collection instrument according to claim 3 is characterized in that:
Described IEEE 1588 triggers management circuits and comprises programmable logic device (PLD) FPGAU20, the LLD[0:7 of described programmable logic device (PLD) FPGAU20] data line is connected with the local bus circuit of PowerPC processor U1; The F1588_IO of described programmable logic device (PLD) FPGAU20 is connected with the IEEE1588 I/O port of PowerPC processor U1; Programmable logic device (PLD) FPGAU20 output terminal is connected with the PPS pulse per second (PPS) F1588_CLKOUT pin of LAN interface circuit.
Above-mentioned analog acquisition circuit comprises collection of simulant signal circuit, programme-controlled gain circuit, program control filtering circuit and the AD sample circuit that connects successively, and the output terminal of described AD sample circuit is connected with pci interface.
The FPGA control circuit comprises fpga chip U101,
Described fpga chip U101 comprise the A/D translation data interface of communicating by letter with the AD sample circuit,
Control SDRAM memory circuit refreshes, and reads, and the SDRAM control circuit of writing is used for control module, the sdram interface circuit of analog acquisition passage duty control and the interrupt control unit that is used to ask to read SDRAM memory circuit translation data,
Described SDRAM memory circuit comprises eight tunnel interconnective the 3rd storage chip U61-U68.
Above-mentioned FLASH memory circuit comprises NOR FLASH chip U6, the first address latch chip U4, the second address latch chip U5 of the 32MB that is used to the program of finishing and data storage and the gate circuit U7 that is used for data buffering, the described first address latch chip U4, the second address latch chip U5, gate circuit U7 connect successively, form buffer circuit, the NOR FLASH chip U6 of described 32MB is connected with the local bus interface U1C circuit of PowerPC processor by buffer circuit;
Described DDR dynamic memory circuit comprises a DDR SDRAM storage chip U2 the 2nd DDR SDRAM storage chip U3 of two parallel connections, and a described DDR SDRAM storage chip U2 all is connected with DDR sdram controller interface U1B with the 2nd DDR SDRAM storage chip U3;
Described LAN interface telecommunication circuit comprises network PHY chip U12, phase inverter U13, voltage controlled oscillator Y2 and ∏ type low-pass filter, signal CP_OUT after the PWM width modulation of the input end reception programmable logic device (PLD) FPGAU20 of described amplifier U13, the reverse signal of signal CP_OUT is given the input end of ∏ type low-pass filter after the output terminal output PWM width modulation of described amplifier U13, the output terminal of described ∏ type low-pass filter is connected with voltage controlled oscillator Y2 control end, and the output terminal of described voltage controlled oscillator Y2 is connected with network PHY chip U12.
The LED indicating module comprises driving circuit U50, the first common cathode Tricolor LED D1, the second common cathode Tricolor LED D2 and the 3rd common cathode Tricolor LED D3, the described first common cathode Tricolor LED D1 is connected with driving circuit U1, and the described second common cathode Tricolor LED D2 is connected with the major clock of PowerPC processor and the IO mouth of IO mouth U1D with the 3rd common cathode Tricolor LED D3.
Above-mentioned LAN interface telecommunication circuit comprises network PHY chip U12, phase inverter U13, voltage controlled oscillator Y2 and ∏ type low-pass filter, the input end of described amplifier U13 receives after the PWM width modulation of programmable logic device (PLD) FPGAU20 behind the signal CP_OUT, reverse signal by phase inverter U13 output CP_OUT, the reverse signal of the input termination CP_OUT of ∏ type low-pass filter, the output terminal of ∏ type low-pass filter is sent into voltage controlled oscillator Y2 control end, and the output terminal of described voltage controlled oscillator Y2 is connected with network PHY chip U12;
Described GPIB/USB interface circuit comprises gpib interface chip U10, USB interface chip U29, and gpib interface chip U10 links to each other with local bus interface U1C, and USB interface chip U29 links to each other with the local bus interface U1C of PowerPC processor.
Also comprise build-out resistor RN16～RN26 in above-mentioned DDR sdram controller interface U1B and the DDR dynamic memory circuit connection line,
Also be provided with clock distribution chip U43 on the clock input link of described major clock and IO mouth U1D and PowerPC processor,
Described DDR dynamic memory circuit also comprises terminating resistor and driven chip U44, the input end of a described DDR SDRAM storage chip U2 is connected to terminating resistor (R176-R180), and the input end of described the 2nd DDR SDRAM storage chip U3 is connected to terminating resistor (R171-R184).
The advantage that the present invention had:
1, this category-B LXI synchronous data collection instrument comprises 8 independently signal sampling channels, and every passage all has 1 independently 16 A/D converters and signal conditioning circuit, and whole acquisition module has the SDRAM data-carrier store of 256MB.Each passage independent parallel sampling, every passage all can be realized the highest sampling of 2MSa/s.Realize the data buffering with FPGA, SDRAM control, passage control, calibration control triggers functions such as control.
2, also comprise build-out resistor RN16～RN26 in DDR sdram controller interface U1B of the present invention and the DDR dynamic memory circuit connection line, the signal reflex that causes because of impedance matching when eliminating high-speed transfer.
3, also be provided with clock distribution chip U43 on the clock input link of major clock of the present invention and IO mouth U1D and PowerPC processor, strengthen clock driving force and clock stability.
4, DDR dynamic memory circuit of the present invention also comprises terminating resistor and driven chip U44, the input end of the one DDR SDRAM storage chip U2 is connected to terminating resistor R176-R180, the input end of the 2nd DDR SDRAM storage chip U3 is connected to terminating resistor R171-R184, improve the reliability of DDR storage, designed terminating resistor RN[27:34], provide termination voltage VTT and DDR to drive reference voltage MPC_MVREF by U44.
Description of drawings
Fig. 1 is the schematic diagram of category-B LXI synchronous data collection instrument of the present invention;
Fig. 2 is flush bonding processor circuit theory diagrams of the present invention;
Fig. 3 triggers the management circuit theory diagrams for IEEE 1588 of the present invention;
Fig. 4 is a FLASH memory circuit schematic diagram of the present invention;
Fig. 5 is a DDR dynamic memory circuit schematic diagram of the present invention;
Fig. 6 is a LAN interface telecommunication circuit schematic diagram of the present invention;
Fig. 7 is internal bus interface circuit theory diagrams of the present invention;
Fig. 8 is a GPIB/USB interface circuit schematic diagram of the present invention;
Fig. 9 is a LED indicating module schematic diagram of the present invention;
Figure 10 is analog acquisition circuit theory diagrams of the present invention;
Figure 11 is a FPGA control circuit schematic diagram of the present invention;
Figure 12 is a SDRAM memory circuit schematic diagram of the present invention.
Embodiment
As shown in Figure 1, category-B LXI bus synchronous data collecting instrument mainly is made up of three parts: category-B LXI interface module, synchronous data collection instrument functional module, LED indicating module.
Category-B LXI interface module is that the bus of LXI instrument realizes the unit, includes flush bonding processor circuit, IEEE 1588 triggering management circuits, FLASH memory circuit, DDR dynamic memory circuit, LAN interface telecommunication circuit, internal bus interface circuit and GPIB/USB interface circuit etc.;
Synchronous data collection instrument functional module is that the function of analog quantity 8 passage synchronous acquisition realizes the unit, includes analog acquisition circuit, FPGA control circuit and SDRAM memory circuit.
The LED indicating module is a complete operation function indicating member, includes driving circuit and LED demonstration and reset circuit etc.
Send into the AD sampling in the analog acquisition circuit after simulating signal reception, programme-controlled gain, the program control filtering, the data of gathering are imported among the FIFO of FPGA, buffer memory gets up in the SRAM, local bus by synchronous data collection instrument functional module then, data are sent to category-B LXI interface modules handle, the LXI interface module is finished the LXI protocol conversion, after the functions such as hardware timestamping of interpolation IEEE1588, the data of gathering is transferred to host computer by LAN.This category-B LXI synchronous data collection instrument comprises 8 independently signal sampling channels, and every passage all has 1 independently 16 A/D converters and signal conditioning circuit, and whole acquisition module has the SDRAM data-carrier store of 256MB.Each passage independent parallel sampling, every passage all can be realized the highest sampling of 2MSa/s.Realize the data buffering with FPGA, SDRAM control, passage control, calibration control triggers functions such as control.
As shown in Figure 2, use the PowerPC processor in the flush bonding processor circuit, dominant frequency is up to 667MHz.In this circuit, the internal bus interface U1A of use 32bit, running frequency 66MHz communicates with synchronous data collection instrument functional module and is connected, and sends packet and instruction bag; DDR sdram controller interface U1B provides address, data and control link for the DDR dynamic memory circuit, increases build-out resistor RN16～RN26, the signal reflex that causes because of impedance matching when eliminating high-speed transfer in each connection line; Local bus U1C adopts 32bit address wire and the multiplexing mode of data line, for peripheral hardwares such as FLASH, GPIB provide interface; Network MAC interface U1G provides two-way 1000M/100M/10M adaptive network path, the first via directly links to each other with the PHY of LAN interface telecommunication circuit, the second road path provides IEEE 1588 agreements PPS clock and I/O port, CFG_RS[0:3 simultaneously] PowerPC actuation schemes word, the start-up mode of decision systems be set; External series Communications Control Interface U1F provides USB interface, RS232 interface, IIC interface and SPI interface; Among major clock and the IO mouth U1D, use the active crystal oscillator of outside 66MHz as the PowerPC main processor clock, by a clock distribution chip U43, strengthen clock driving force and clock stability, be used as LXI_TRIG[0:7 with the IO mouth] 8 triggering passage and the control port of LED indicating module.
As shown in Figure 3, IEEE 1588 triggers management circuit and adopts programmable logic device (PLD) FPGA to realize, 8 position datawire LLD[0:7] be connected with the LocalBus of PowerPC, set up the communication between PowerPC processor and the FPGA, also can use the SPI mouth simply to control; LXI_TRIG[0:7] receiving after LXI sets out, trigger relevant treatment such as route, simultaneously triggering is sent among the PowerPC, finish trigger action, sending trigger pip also is to trigger lines by these 8 to finish; F1588_IO receives and dispatches 1588 incidents and handles in FPGA; The 1588 PPS pulse per second (PPS)s that F_1588_PPS output is handled by FPGA, CP_OUT is the output signal after process FPGA carries out the PWM width modulation, be used for adjusting the Network Transmission clock, F1588_CLKOUT receives the PPS pulse per second (PPS) by network PHY output, and LAN_X1 receives network PHY crystal oscillator clock.When needs were adjusted network clocking, LAN_X1 fed back to the current network clock among the FPGA, and FPGA is by certain PWM algorithm, and output CP_OUT adjusts present clock.
As shown in Figure 4, the FLASH memory circuit adopts the NOR FLASH of 32MB to finish the storage of program and data, and U6 is connected with the LocalBus of PowerPC, uses the address latch chip U4/U5 of 2 16bit, the gate circuit U7 of 1 16bit carries out data buffering, puies forward the signal high stability.
As shown in Figure 5, the DDR dynamic memory circuit is realized the high-speed cache of data, use the 16bitDDR SDRAM storage chip U2/U3 of 2 64MB directly to link to each other with PowerPC DDR controller, in order to improve the reliability of DDR storage, designed terminating resistor RN[27:34], provide termination voltage VTT and DDR to drive reference voltage MPC_MVREF by U44.
As shown in Figure 6, U12 is the network PHY chip, provides network communication interface between host computer and category-B LXI synchronous data collection instrument, simultaneously hardware extraction IEEE 1588 timestamps.U13 carries out after receiving the CP_OUT signal oppositely, the ∏ type low-pass filter by forming then by C68, C62, C67, R58, and general PWM modulation signal CP_OUT all the time sends into voltage controlled oscillator Y2 control end, carries out the adjustment of local network clock.U[15:19] and toggle switch SW1 provide the actuation schemes word for system.
As shown in Figure 7, P2 and P3 are internal bus interface, and interface and the synchronous data collection instrument functional module communication interface of 32bti, 66MHz is provided.
As shown in Figure 8, except LAN interface, this category-B LXI synchronous data collection instrument can also use GPIB to communicate by letter with host computer with USB interface.U10 is special-purpose gpib interface chip, in order to make the GPIB voltage matches of PowerPC port voltage and 5V of 3.3V, uses U9 to have the 16bit buffer gate circuit of voltage transitions.USB interface uses the U29 special chip directly to link to each other with PowerPC, realizes USB2.0 communication protocol.RS232 is a debug port, uses the U31 special chip, prints startup and Debugging message by RS232 in debug process.
As shown in Figure 9, LED indicating module circuit is according to LXI v1.3 standard design, and D1 is common cathode 3 look light emitting diodes, cooperates the U1 driving circuit, and standby and power are provided indication; D2 and D3 carry out the indication of network connection state and IEEE 1588 states respectively directly by the IO port controlling of PowerPC.
As shown in figure 10,8 people having a common goal's parallel acquisition front end simulation process part needs to realize functions such as simulating signal reception, programme-controlled gain, program control filtering and AD sampling.For the simulating signal receiving function, in order to reduce the veneer interference of signal to external world as far as possible, simulating signal receives with three discharge circuits, the discharge circuit of three discharge circuits is selected high speed high input impedance amplifier U12 for use, the input of signal has two kinds of DC coupling and AC coupling, AC coupling realizes that by an electric capacity single-ended and differential signal is selected by dpdt relay.U10 selects an analog switch for two four.Signal after receiving element is handled is sent into the programme-controlled gain processing of circuit, in order to guarantee that the result that A/D gathers has best signal to noise ratio (S/N ratio), must make signal reach the maximum input range of A/D when arriving the A/D front end as far as possible, so need the large-signal of input be decayed, small-signal is amplified.The programme-controlled gain circuit is made up of multiplexer U19 and Voltage Feedback amplifier U22.Program control filtering need will be selected the low-pass filter of different gears according to the frequency of input signal.The gear of wave filter is divided into 100kHz and 900kHZ, selects for use 3 rank Butterworth active filters to realize that the gear of wave filter is selected by relay, and signal is handled by the U14 amplifier after the low-pass filtering.AD is finished by the U25 special chip, and this A/D is the SAR AD converter of 16 2M sampling rates, and inside provides the reference of 4.096v, parallel data output, optional 16bit or 8bit data output format.Analog signal conversion is that the FPGA that imports Figure 10 after the digital signal into handles.
As shown in figure 11, fpga chip U1 finishes the operation control of whole acquisition channel, and decisive role is arranged in total system.FPGA finishes the interface with the A/D translation data; The refreshing of SDRAM, reading and writing control; The control of passage duty (trigger mode, the control of A/D sampling rate, interchannel synchro control, gain control, gain calibration control); The SDRAM data are to the interface control of local bus; Functions such as SDRAM data interruption control are read in request.
As shown in figure 12, whole acquisition module has the SDRAM data-carrier store of 512MB, by the U[61:68 among Figure 10] the SDRAM chip forms, under the control of the sdram interface of FPGA, gather translation data and be written among the SDRAM, reach certain memory data output after, reading of data is to local bus interface from SDRAM, be transferred in the category-B LXI interface module, send to host computer by LAN and offer system's use.
Claims (8)
1.B class LXI synchronous data collection instrument is characterized in that: comprise category-B LXI interface module, synchronous data collection instrument functional module and LED indicating module;
Category-B LXI interface module comprises that flush bonding processor circuit, IEEE 1588 trigger management circuit, FLASH memory circuit, DDR dynamic memory circuit and LAN interface telecommunication circuit;
The flush bonding processor circuit is the network interface that is used to provide with the control computer communication, realizes the LXI bus protocol that procedure stores is relevant with processing; Described LED indicating module intercoms mutually with the flush bonding processor circuit,
IEEE 1588 triggers management circuit and is used to handle 1588 agreements, manages 1588 associated trigger and extraction time and stabs; Described IEEE 1588 triggers management circuit and comprises programmable logic device (PLD) FPGA(U20);
The FLASH memory circuit is used for memory system data and application program;
The DDR dynamic memory circuit is used for the dynamic memory process data, for the reading of application program, carry out buffering is provided;
The LAN interface telecommunication circuit provides the hardware path with the control computer communication; Described LAN interface telecommunication circuit comprises network PHY chip (U12), phase inverter (U13), voltage controlled oscillator (Y2) and ∏ type low-pass filter, the input end reception programmable logic device (PLD) FPGA(U20 of described phase inverter (U13)) signal CP_OUT after the PWM width modulation, the reverse signal of signal CP_OUT is given the input end of ∏ type low-pass filter after the output terminal output PWM width modulation of described phase inverter (U13), the output terminal of described ∏ type low-pass filter is connected with voltage controlled oscillator (Y2) control end, and the output terminal of described voltage controlled oscillator (Y2) is connected with network PHY chip (U12);
Synchronous data collection instrument functional module comprises pci interface, analog acquisition circuit, FPGA control circuit and SDRAM memory circuit, the analog acquisition circuit is used to gather simulating signal, simulating signal is carried out programme-controlled gain and program control filtering, carry out the AD sampling again, and import sampled data into the FPGA control circuit; The FPGA control circuit is used for the operation control of analog acquisition passage; The SDRAM storer is used for the storage of collected translation data; Pci interface is used for being connected of category-B LXI interface module and synchronous data collection instrument functional module, described flush bonding processor circuit comprises PowerPC processor (U1), described PowerPC processor (U1) comprises internal bus interface (U1A), DDR sdram controller interface (U1B), local bus interface (U1C), network MAC interface (U1G), major clock and IO mouth (U1D), described internal bus interface (U1A) communicates to connect with pci interface, and described DDR sdram controller interface (U1B) provides the address for the DDR dynamic memory circuit, data and control link; Described local bus interface (U1C) provides interface for the FLASH memory circuit, described network MAC interface (U1G) provides two-way adaptive network path, and the first via links to each other with the LAN interface telecommunication circuit, the second tunnel be used for triggering PPS clock and the I/O port that management circuits provide IEEE 1588 agreements to IEEE 1588; Major clock is used to the clock input of PowerPC processor in described major clock and the IO mouth (U1D), and the IO mouth is used for triggering management circuit to IEEE 1588 to be provided triggering passage and provide control port to the LED indicating module,
Described programmable logic device (PLD) FPGA(U20) LLD[0:7] data line is connected with the local bus circuit of PowerPC processor (U1); Described programmable logic device (PLD) FPGA(U20) F1588_IO is connected with the IEEE1588 I/O port of PowerPC processor (U1); Programmable logic device (PLD) FPGA(U20) output terminal is connected with the PPS pulse per second (PPS) F1588_CLKOUT pin of LAN interface telecommunication circuit.
2. category-B LXI synchronous data collection instrument according to claim 1 is characterized in that:
Described category-B LXI interface module also comprises the GPIB/USB interface circuit that is used to realize GPIB/USB hardware path, and local bus interface (U1C) is also for the gpib interface circuit provides interface, and described GPIB/USB interface circuit is connected with local bus interface (U1C).
3. category-B LXI synchronous data collection instrument according to claim 2 is characterized in that:
Described analog acquisition circuit comprises collection of simulant signal circuit, programme-controlled gain circuit, program control filtering circuit and the AD sample circuit that connects successively, and the output terminal of described AD sample circuit is connected with pci interface.
4. category-B LXI synchronous data collection instrument according to claim 3 is characterized in that:
The FPGA control circuit comprises fpga chip (U101),
Described fpga chip (U101) comprise the A/D translation data interface of communicating by letter with the AD sample circuit,
Control SDRAM memory circuit refreshes, and reads, and the SDRAM control circuit of writing is used for control module, the sdram interface circuit of analog acquisition passage duty control and the interrupt control unit that is used to ask to read SDRAM memory circuit translation data,
Described SDRAM memory circuit comprises eight tunnel interconnective the 3rd storage chips (U61-U68).
5. category-B LXI synchronous data collection instrument according to claim 4 is characterized in that:
Described FLASH memory circuit comprises NOR FLASH chip (U6), the first address latch chip (U4), the second address latch chip (U5) of the 32MB that is used to the program of finishing and data storage and the gate circuit (U7) that is used for data buffering, the described first address latch chip (U4), the second address latch chip (U5), gate circuit (U7) are connected successively, form buffer circuit, the NOR FLASH chip (U6) of described 32MB is connected with local bus interface (U1C) circuit of PowerPC processor by buffer circuit;
Described DDR dynamic memory circuit comprises a DDR SDRAM storage chip (U2) the 2nd DDR SDRAM storage chip (U3) of two parallel connections, and a described DDR SDRAM storage chip (U2) all is connected with DDR sdram controller interface (U1B) with the 2nd DDR SDRAM storage chip (U3).
6. category-B LXI synchronous data collection instrument according to claim 5, it is characterized in that: the LED indicating module comprises driving circuit (U50), the first common cathode Tricolor LED (D1), the second common cathode Tricolor LED (D2) and the 3rd common cathode Tricolor LED (D3), the described first common cathode Tricolor LED (D1) is connected with driving circuit (U50), and the described second common cathode Tricolor LED (D2) is connected with the major clock of PowerPC processor and the IO mouth of IO mouth (U1D) with the 3rd common cathode Tricolor LED (D3).
7. category-B LXI synchronous data collection instrument according to claim 6 is characterized in that:
Described GPIB/USB interface circuit comprises gpib interface chip (U10), USB interface chip (U29), gpib interface chip (U10) links to each other with local bus interface (U1C), and USB interface chip (U29) links to each other with the local bus interface (U1C) of PowerPC processor.
8. category-B LXI synchronous data collection instrument according to claim 7 is characterized in that:
Also comprise build-out resistor in described DDR sdram controller interface (U1B) and the DDR dynamic memory circuit connection line,
Also be provided with clock distribution chip (U43) on the clock input link of described major clock and IO mouth (U1D) and PowerPC processor,
Described DDR dynamic memory circuit also comprises terminating resistor and driven chip (U44), the input end of a described DDR SDRAM storage chip (U2) is connected to terminating resistor, and the input end of described the 2nd DDR SDRAM storage chip (U3) is connected to terminating resistor.
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| CN106815157A (en) * | 2016-12-20 | 2017-06-09 | 北京旋极信息技术股份有限公司 | A kind of data acquisition module and data collecting system |
| CN107894528A (en) * | 2017-10-25 | 2018-04-10 | 江苏镇安欣润电力科技有限公司 | High speed synchronous sample system |
| CN110608865A (en) * | 2019-11-05 | 2019-12-24 | 中国空气动力研究与发展中心高速空气动力研究所 | Wind tunnel miniature measuring system |
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