CN202404742U - Class-B LXI multifunctional data collector - Google Patents

Abstract

The utility model relates to a Class-B LXI multifunctional data collector which comprises a Class-B LXI interface module, a multifunctional data collector function module for achieving analogue collection, analogue quantity output and digital quantity input and output, and an LED (light-emitting diode) indicating module, wherein the multifunctional data collector function module comprises an FPGA (field programmable gate array) unit, a PCI interface, a memory and an input and output unit. According to the Class-B LXI multifunctional data collector, the technical problem that requirements on higher sampling precision and speed cannot be met due to single function, low scanning frequency and small onboard cache of the conventional data collector is solved. The Class-B LXI multifunctional data collector provided by the utility model has various functions such as analogue quantity collection, analogue quantity output, digital quantity input and output, the functions of a timing counter and a programmable function interface and the like.

Description

Category-B LXI Multipurpose Data Acquisition Instrument

Technical field

The utility model relates to a kind of category-B LXI bus Multipurpose Data Acquisition Instrument circuit.

Background technology

Agilent and VXI Technology company have proposed a kind of new instrument bus-LXI (LAN eXtensions for Instrumentation) in 2004.The LXI instrument need not be special core bus cabinet and Zero greeve controller, directly utilize the standard LAN interface of universal PC, reduced the development and application cost to a great extent.And LAN that to be industry the most stable with life cycle is the longest and in the continuous opened industrial standard of development; Each manufacturer is easy to existing instrument product is transplanted on the LAN platform, and these all are to set up wider distributed automatic measuring and controlling system convenience is provided.The LXI bus standard has defined the chronometer time synchronizing function based on IEEE1588 simultaneously, has introduced the notion based on Time Triggered for the first time in the thermometrically field, is easy to make up real-time testing system.

Based on the data collecting instrument function singleness of scan pattern, the sweep frequency of the multifunction card of existing 16 precision all is lower than 1MSa/s, and less at the plate buffer memory at present.Along with quick development of modern science and technology,, also increasingly high for the sampling precision and the rate request of multi-functional scanning collection especially in Aero-Space, military field.In this case, the LXI bus Multipurpose Data Acquisition Instrument of exploitation high-speed, high precision has the excellent engineering using value.Particularly in distributed measurement and control system; Require testing tool to have the programming remote control function; Existing bus such as GPIB, PCI/PXI etc. can't well meet the demands, the Multipurpose Data Acquisition Instrument system of LXI bus satisfied that sampling rate is high, plate carry buffer memory big, be easy to set up requirement such as distributed measurement and control system.

Summary of the invention

Solve existing data collecting instrument function singleness, sweep frequency is all low, and in the less technical matters that can't satisfy increasingly high sampling precision and rate request of plate buffer memory, the utility model provides a kind of category-B LXI Multipurpose Data Acquisition Instrument.

The technical solution of the utility model:

Category-B LXI Multipurpose Data Acquisition Instrument, its special character is: comprise category-B LXI interface module, be used to realize analog acquisition, analog quantity output, the Multipurpose Data Acquisition Instrument functional module of digital quantity input and output, LED indicating module;

Said category-B LXI interface module comprises that flush bonding processor circuit, IEEE 1588 trigger management circuit, FLASH memory circuit, DDR dynamic memory circuit and LAN interface telecommunication circuit;

The flush bonding processor circuit is the network interface that is used to provide with the control computer communication, realizes the LXI bus protocol that procedure stores is relevant with processing;

IEEE 1588 triggers management circuit and is used to handle 1588 agreements, manages 1588 associated trigger and extraction time and stabs;

The FLASH memory circuit is used for memory system data and application program;

The DDR dynamic memory circuit is used for the dynamic memory process data, for the reading of application program, carry out buffering is provided;

The LAN interface telecommunication circuit provides the hardware path with the control computer communication;

The Multipurpose Data Acquisition Instrument functional module comprises FPGA unit 1, pci interface 2, storer 3 and input-output unit; Said input-output unit comprises analog input unit 41; Said FPGA unit 1 is connected with storer 3, and said FPGA unit is connected with pci bus 5 through pci interface 2, and said FPGA unit is connected with IO interface 6 through input-output unit; Said analog input unit 41 is a graded amplifying circuit; Said graded amplifying circuit comprises three discharge circuits, multi-way switch circuit and the level shifting circuit U55 that connects successively; Said three discharge circuits are used to realize importing the high impedance and the high common mode inhibition of simulating signal, and it comprises positive input discharge circuit U51B, negative input discharge circuit 9U51A and differential amplifier circuit U52; Said multi-way switch circuit is used to realize that switching and the signal of many gear signal amplify or dwindle, and it comprises the different convert resistance of the preposition follower U53, Port Multiplier U56, a plurality of parallel connection and the resistance that connect successively (R8～R14) and rearmounted amplifying circuit U54; Said preposition follower U53 is used to avoid the influence of the conducting resistance of Port Multiplier U56 to gain, and said Port Multiplier U56 and convert resistance (R8～R14) realize gear switch, said rearmounted amplifying circuit U54 is used for signal is adjusted to the voltage range of regulation; Said level shifting circuit U55 is used for the multi-way switch circuit amplification or the positive/negative voltage signal after dwindling converts positive voltage signal to.

Above-mentioned flush bonding processor circuit comprises PowerPC processor U1; Said PowerPC processor U1 comprises internal bus interface U1A, DDR sdram controller interface U1B, local bus interface U1C, network MAC interface U1G, major clock and IO mouth U1D; Said internal bus interface U1A is connected with pci interface 2 communications, and said DDRSDRAM control unit interface U1B provides address, data and control link for the DDR dynamic memory circuit; Said local bus interface U1C provides interface for the FLASH memory circuit; Said network MAC interface U1G provides two-way adaptive network path, and the first via links to each other with the LAN interface telecommunication circuit, the second tunnel be used for triggering PPS clock and the I/O port that management circuits provide IEEE 1588 agreements to IEEE 1588; Major clock is used to the clock input of PowerPC processor among said major clock and the IO mouth U1D, and the IO mouth is used for triggering management circuit to IEEE 1588 to be provided triggering passage and to the LED indicating module control port is provided.

Above-mentioned category-B LXI interface module also comprises the GPIB/USB interface circuit that is used to realize GPIB/USB hardware path, and local bus interface U1C also provides interface for the gpib interface circuit, and said GPIB/USB interface circuit is connected with local bus interface U1C.

Above-mentioned IEEE 1588 triggers management circuit and comprises PLD FPGAU20, and the LLD of said PLD FPGAU20 [0:7] data line is connected with the local bus circuit of PowerPC processor U1; The F1588_IO of said PLD FPGAU20 is connected with the IEEE1588I/O port of PowerPC processor U1; PLD FPGAU20 output terminal is connected with the PPS pulse per second (PPS) F1588_CLKOUT pin of LAN interface circuit.

Above-mentioned FLASH memory circuit comprises NOR FLASH chip U6, the first address latch chip U4, the second address latch chip U5 of the 32MB that is used for completion program and data storage and the gate circuit U7 that is used for data buffering; The said first address latch chip U4, the second address latch chip U5, gate circuit U7 connect successively; Form buffer circuit, the NOR FLASH chip U6 of said 32MB is connected with the local bus interface U1C circuit of PowerPC processor through buffer circuit;

Said DDR dynamic memory circuit comprises a DDR SDRAM storage chip U2 the 2nd DDRSDRAM storage chip U3 of two parallel connections, and a said DDR SDRAM storage chip U2 all is connected with DDR sdram controller interface U1B with the 2nd DDR SDRAM storage chip U3;

Said LAN interface telecommunication circuit comprises network PHY chip U12, phase inverter U13, voltage controlled oscillator Y2 and ∏ type low-pass filter; Signal CP_OUT after the PWM width modulation of the input end reception PLD FPGAU20 of said amplifier U13; The reverse signal of signal CP_OUT is given the input end of ∏ type low-pass filter after the output terminal output PWM width modulation of said amplifier U13; The output terminal of said ∏ type low-pass filter is connected with voltage controlled oscillator Y2 control end, and the output terminal of said voltage controlled oscillator Y2 is connected with network PHY chip U12.

The LED indicating module comprises driving circuit U50, the first common cathode Tricolor LED D1, the second common cathode Tricolor LED D2 and the 3rd common cathode Tricolor LED D3; The said first common cathode Tricolor LED D1 is connected with driving circuit U1, and the said second common cathode Tricolor LED D2 is connected with the major clock of PowerPC processor and the IO mouth of IO mouth U1D with the 3rd common cathode Tricolor LED D3.

Above-mentioned LAN interface telecommunication circuit comprises network PHY chip U12, phase inverter U13, voltage controlled oscillator Y2 and ∏ type low-pass filter; The input end of said amplifier U13 receives after the PWM width modulation of PLD FPGAU20 behind the signal CP_OUT; Reverse signal through phase inverter U13 output CP_OUT; The reverse signal of the input termination CP_OUT of ∏ type low-pass filter; The output terminal of ∏ type low-pass filter is sent into voltage controlled oscillator Y2 control end, and the output terminal of said voltage controlled oscillator Y2 is connected with network PHY chip U12;

Above-mentioned GPIB/USB interface circuit comprises gpib interface chip U10, USB interface chip U29, and gpib interface chip U10 links to each other with local bus interface U1C, and USB interface chip U29 links to each other with the local bus interface U1C of PowerPC processor.

Also comprise build-out resistor RN16～RN26 in above-mentioned DDR sdram controller interface U1B and the DDR dynamic memory circuit connection line,

Also be provided with clock distribution chip U43 on the clock input link of said major clock and IO mouth U1D and PowerPC processor,

Said DDR dynamic memory circuit also comprises terminating resistor and driven chip U44; The input end of a said DDRSDRAM storage chip U2 is connected to terminating resistor (R176-R180), and the input end of said the 2nd DDR SDRAM storage chip U3 is connected to terminating resistor (R171-R184).

Above-mentioned input-output unit also comprises simulation output unit 42, Digital I unit 43, simulation output control module 16, digital I 17; Said simulation output control module 16 is connected with simulation output unit 42, and said digital I 17 is connected with Digital I unit 43, and an end of said Digital I unit 43 is connected with FPGA unit 1, and its other end is connected with IO interface 6; It comprises the current-limiting resistance 20 that is arranged on the IO interface end and diode voltage-limiting protection circuit 10 and the bus switch 9 that is arranged on the FPGA interface end; Said bus switch 9 is used to realize the level conversion function;

Said FPGA unit 1 comprises logical routing module 11, internal clocking 14, other control modules 18, memory control module 13, local bus control module 12 and input/output control module; Said logical routing module 11 is connected with internal clocking 14, other control modules 18, memory control module and input/output control module respectively; Said input/output control module comprises analog input control module 15; Said analog input control module 15 is connected with analog input unit 41, and said memory control module 13 is connected with storer 3; Said logical routing module 11 is connected with pci bus 5 through pci interface 2.

The advantage that the utility model had:

1, the Acquisition Instrument of the utility model LXI bus has multiple functions such as analog acquisition, analog quantity output, digital quantity input and output, timer conter and programmable functions interface.The IEEE 1588 chronometer time synchronous protocols that the category-B instrument of this LXI bus is had have been realized the Remote triggering synchronizing function of instrument in nanosecond, can in ATS (Automatic Test System), play a significant role.

2, also comprise build-out resistor RN16～RN26 in the utility model DDR sdram controller interface U1B and the DDR dynamic memory circuit connection line, the signal reflex that causes because of impedance matching when eliminating high-speed transfer.

3, also be provided with clock distribution chip U43 on the clock input link of the utility model major clock and IO mouth U1D and PowerPC processor, strengthen clock driving force and clock stability.

4, the utility model DDR dynamic memory circuit also comprises terminating resistor and driven chip U44; The input end of the one DDR SDRAM storage chip U2 is connected to terminating resistor R176-R180; The input end of the 2nd DDR SDRAM storage chip U3 is connected to terminating resistor R171-R184; Improve the reliability of DDR storage, designed terminating resistor RN [27:34], provide termination voltage VTT and DDR to drive reference voltage MPC_MVREF by U44.

Description of drawings

Fig. 1 is the theory diagram of the utility model category-B LXI multifunctional data acquiring;

Fig. 2 is the utility model flush bonding processor circuit theory diagrams;

Wherein Fig. 2 a is U1A, and Fig. 2 b is U1B, and Fig. 2 c is U1C, and Fig. 2 d is U1D, and Fig. 2 e is U1F, and Fig. 2 f is U1G;

Fig. 3 is that the utility model IEEE 1588 triggers the management circuit theory diagrams;

Fig. 4 is the utility model FLASH memory circuit schematic diagram;

Fig. 5 is the utility model DDR dynamic memory circuit schematic diagram;

Fig. 6 is the utility model LAN interface telecommunication circuit schematic diagram;

Fig. 7 is the utility model internal bus interface circuit theory diagrams;

Fig. 8 is the utility model GPIB/USB interface circuit schematic diagram;

Fig. 9 is the utility model LED indicating module schematic diagram;

Figure 10 is the utility model multifunctional data acquisition card circuit theory diagrams, wherein: 1-FPGA unit, 2-PCI interface, 3-storer; 41-analog input unit, 42-simulates output unit, 43-Digital I unit, 5-PCI bus; The 6-IO interface, other circuit of 7-, 8-calibration circuit;

Figure 11 is the utility model Digital I element circuit schematic diagram, wherein: 9-bus switch, 10-diode voltage-limiting protection circuit, 20-current-limiting resistance;

Figure 12 is the utility model Digital I element circuit structural representation;

Figure 13 is the utility model FPGA element circuit schematic diagram; Wherein: 11-logical routing module, 12-local bus control module, the 13-memory control module, the 14-internal clocking, 15-analog input control module, 16-simulates output control module, 17-digital I, other control modules of 18-.

Embodiment

As shown in Figure 1, category-B LXI Multipurpose Data Acquisition Instrument comprises category-B LXI interface module, is used to realize analog acquisition, analog quantity output, the Multipurpose Data Acquisition Instrument functional module of digital quantity input and output, LED indicating module; Said category-B LXI interface module comprises that flush bonding processor circuit, IEEE 1588 trigger management circuit, FLASH memory circuit, DDR dynamic memory circuit and LAN interface telecommunication circuit;

The flush bonding processor circuit is the network interface that is used to provide with the control computer communication, realizes the LXI bus protocol that procedure stores is relevant with processing;

IEEE 1588 triggers management circuit and is used to handle 1588 agreements, manages 1588 associated trigger and extraction time and stabs;

The FLASH memory circuit is used for memory system data and application program;

The DDR dynamic memory circuit is used for the dynamic memory process data, for the reading of application program, carry out buffering is provided; The LAN interface telecommunication circuit provides the hardware path with the control computer communication;

The Multipurpose Data Acquisition Instrument functional module comprises FPGA unit 1, pci interface 2, storer 3 and input-output unit; Said input-output unit comprises analog input unit 41; Said FPGA unit 1 is connected with storer 3, and said FPGA unit is connected with pci bus 5 through pci interface 2, and said FPGA unit is connected with IO interface 6 through input-output unit; Said analog input unit 41 is a graded amplifying circuit; Said graded amplifying circuit comprises three discharge circuits, multi-way switch circuit and the level shifting circuit U55 that connects successively; Said three discharge circuits are used to realize importing the high impedance and the high common mode inhibition of simulating signal, and it comprises positive input discharge circuit U51B, negative input discharge circuit U51A and differential amplifier circuit U52; Said multi-way switch circuit is used to realize that switching and the signal of many gear signal amplify or dwindle, and it comprises the different convert resistance of the preposition follower U53, Port Multiplier U56, a plurality of parallel connection and the resistance that connect successively (R8～R14) and rearmounted amplifying circuit U54; Said preposition follower U53 is used to avoid the influence of the conducting resistance of Port Multiplier U56 to gain, and said Port Multiplier U56 and convert resistance (R8～R14) realize gear switch, said rearmounted amplifying circuit U4 is used for signal is adjusted to the voltage range of regulation; Said level shifting circuit U55 is used for the multi-way switch circuit amplification or the positive/negative voltage signal after dwindling converts positive voltage signal to.

As shown in Figure 2, use the PowerPC processor in the flush bonding processor circuit, dominant frequency is up to 667MHz.In this circuit, the internal bus interface U1A of use 32bit, running frequency 66MHz communicates with the Multipurpose Data Acquisition Instrument functional module and is connected, and sends packet and instruction bag; DDR sdram controller interface U1B provides address, data and control link for the DDR dynamic memory circuit, in each connection line, increases build-out resistor RN16～RN26, the signal reflex that causes because of impedance matching when eliminating high-speed transfer; Local bus U1C adopts 32bit address wire and the multiplexing mode of data line, for peripheral hardwares such as FLASH, GPIB provide interface; Network MAC interface U1G provides two-way 1000M/100M/10M adaptive network path; The first via directly links to each other with the PHY of LAN interface telecommunication circuit, the second road path provides IEEE 1588 agreements PPS clock and I/O port; CFG_RS [0:3] is provided with PowerPC actuation schemes word, the start-up mode of decision systems simultaneously; External series Communications Control Interface U1F provides USB interface, RS232 interface, IIC interface and SPI interface; Among major clock and the IO mouth U1D; Use the active crystal oscillator of outside 66MHz as the PowerPC main processor clock; Through a clock distribution chip U43, strengthen clock driving force and clock stability, be used as 8 triggering passage of LXI_TRIG [0:7] and the control port of LED indicating module with the IO mouth.

As shown in Figure 3; IEEE 1588 triggers management circuit and adopts PLD FPGA to realize; 8 position datawire LLD [0:7] are connected with the LocalBus of PowerPC, set up the communication between PowerPC processor and the FPGA, also can use the SPI mouth simply to control; LXI_TRIG [0:7] triggers relevant treatment such as route receiving after LXI sets out, and simultaneously triggering is sent among the PowerPC, accomplishes trigger action, and sending trigger pip also is to trigger lines by these 8 to accomplish; F1588_IO receives and dispatches 1588 incidents and in FPGA, handles; The 1588 PPS pulse per second (PPS)s that F_1588_PPS output is handled by FPGA; CP_OUT is the output signal after process FPGA carries out the PWM width modulation; Be used for adjusting the Network Transmission clock, F1588_CLKOUT receives the PPS pulse per second (PPS) by network PHY output, and LAN_X1 receives network PHY crystal oscillator clock.When needs adjustment network clocking, LAN_X1 feeds back to the current network clock among the FPGA, and FPGA is through certain PWM algorithm, and output CP_OUT adjusts present clock.

As shown in Figure 4; The FLASH memory circuit adopts the NOR FLASH of 32MB to come the storage of completion program and data, and U6 is connected with the LocalBus of PowerPC, uses the address latch chip U4/U5 of 2 16bit; The gate circuit U7 of 1 16bit carries out data buffering, puies forward the signal high stability.

As shown in Figure 5; The DDR dynamic memory circuit is realized the data in high speed buffer memory; Use the 16bitDDR SDRAM storage chip U2/U3 of 2 64MB directly to link to each other with PowerPC DDR controller; In order to improve the reliability of DDR storage, designed terminating resistor RN [27:34], provide termination voltage VTT and DDR to drive reference voltage MPC_MVREF by U44.

As shown in Figure 6, U12 is the network PHY chip, between host computer and category-B LXI Multipurpose Data Acquisition Instrument, network communication interface is provided, simultaneously hardware extraction IEEE 1588 timestamps.U13 carries out reverse after receiving the CP_OUT signal, the ∏ type low-pass filter through forming then by C68, C62, C67, R58, and PWM modulation signal CP_OUT sends into voltage controlled oscillator Y2 control end all the time, carries out the adjustment of local network clock.U [15:19] and toggle switch SW1 are that system provides the actuation schemes word.

As shown in Figure 7, P2 and P3 are internal bus interface, and interface and the Multipurpose Data Acquisition Instrument functional module communication interface of 32bti, 66MHz is provided.

As shown in Figure 8, except LAN interface, this category-B LXI Multipurpose Data Acquisition Instrument can also use GPIB to communicate by letter with host computer with USB interface.U10 is special-purpose gpib interface chip, and in order to make the GPIB voltage matches of PowerPC port voltage and 5V of 3.3V, use U9 has the 16bit buffer gate circuit of voltage transitions.USB interface uses the U29 special chip directly to link to each other with PowerPC, realizes USB2.0 communication protocol.RS232 is a debug port, uses the U31 special chip, in debug process, prints startup and Debugging message through RS232.

As shown in Figure 9, LED indicating module circuit is according to LXI v1.3 standard design, and D1 is common cathode 3 look light emitting diodes, cooperates the U50 driving circuit, and standby and power are provided indication; D2 and D3 carry out the indication of network connection state and IEEE 1588 states respectively directly by the IO port controlling of PowerPC.

Referring to Figure 10; The utility model multifunctional data acquisition card mainly is made up of analog input unit, simulation output unit, Digital I unit, FPGA unit, storer, pci interface and power supply; Be a kind of multifunctional data acquisition card, adopt the overall architecture of FPGA unit (Programmable Logic Controller)+PCI bridge+storer+peripherals based on PXI or pci bus.Wherein: the FPGA unit adopts chip XC3S1500, realizes the functions such as Communication Control of the peripherals control of (comprising analog input unit, simulation output unit, Digital I unit), timer conter, storer control, pci interface chip; The FPGA unit adopts PCI 9054 chips to realize the PXI/PCI interface function, converts pci bus to local bus; The FPGA unit is connected with IO interface 6 through input-output unit; Pci interface FPGA unit is connected with storer, and the jumbo SDRAM chip MT48LC8M32 that storer adopts monolithic realizes the interim storage of jumbo analog-and digital-data; FPGA built sdram controller carries out the metadata cache of each several part; Because the maximum operation frequency of SDRAM is 100MHz, so adopt the multilayer board wiring.

Referring to Figure 11 and Figure 12, the utility model Digital I unit is in order to realize the independent control of single IO direction, the mode that adopts FPGA directly to realize.The port voltage of common user IO level ratio FPGA is high, so the utility model adopts current-limiting resistance 20, diode voltage-limiting protection circuit 10 and bus switch 9 to carry out dual IO defencive function.Current-limiting resistance and diode carry out overvoltage protection, in voltage clamp to 0～5V, and the 3.3V signal that becomes FPGA normally to receive the IO conversion of signals of 5V through bus switch then.

Referring to Figure 13, the FPGA unit comprises that control, timer conter, the storer of peripherals such as analog input unit, simulation output unit, Digital I unit are controlled, the functions such as Communication Control of pci interface chip.FPGA adopts modular design; Be divided into the funtion part of relative opposition; Comprise analog input control module, simulation output control module, digital I, memory control module etc., also realize metadata cache function in a small amount simultaneously in inside, FPGA unit.

Claims (10)

1.B type LXI Multipurpose Data Acquisition Instrument is characterized in that: comprise category-B LXI interface module, be used to realize analog acquisition, analog quantity output, the Multipurpose Data Acquisition Instrument functional module of digital quantity input and output, LED indicating module;

Said category-B LXI interface module comprises that flush bonding processor circuit, IEEE 1588 trigger management circuit, FLASH memory circuit, DDR dynamic memory circuit and LAN interface telecommunication circuit;

The flush bonding processor circuit is the network interface that is used to provide with the control computer communication, realizes the LXI bus protocol that procedure stores is relevant with processing;

IEEE 1588 triggers management circuit and is used to handle 1588 agreements, manages 1588 associated trigger and extraction time and stabs;

The FLASH memory circuit is used for memory system data and application program;

The DDR dynamic memory circuit is used for the dynamic memory process data, for the reading of application program, carry out buffering is provided;

The LAN interface telecommunication circuit provides the hardware path with the control computer communication;

The Multipurpose Data Acquisition Instrument functional module comprises FPGA unit (1), pci interface (2), storer (3) and input-output unit; Said input-output unit comprises analog input unit (41); Said FPGA unit (1) is connected with storer (3), and said FPGA unit is connected with pci bus (5) through pci interface (2), and said FPGA unit is connected with IO interface (6) through input-output unit; Said analog input unit (41) is a graded amplifying circuit; Said graded amplifying circuit comprises three discharge circuits, multi-way switch circuit and the level shifting circuit (U55) that connects successively; Said three discharge circuits are used to realize importing the high impedance and the high common mode inhibition of simulating signal, and it comprises positive input discharge circuit (U51B), negative input discharge circuit (9U51A) and differential amplifier circuit (U52); Said multi-way switch circuit is used to realize that switching and the signal of many gear signal amplify or dwindle, and it comprises the different convert resistance of the preposition follower (U53), Port Multiplier (U56), a plurality of parallel connection and the resistance that connect successively (R8～R14) and rearmounted amplifying circuit (U54); Said preposition follower (U53) is used to avoid the influence of the conducting resistance of Port Multiplier (U56) to gain; Said Port Multiplier (U56) and convert resistance (R8～R14) realize gear switch, said rearmounted amplifying circuit (U54) is used for signal is adjusted to the voltage range of regulation; Said level shifting circuit (U55) is used for the multi-way switch circuit amplification or the positive/negative voltage signal after dwindling converts positive voltage signal to.

2. category-B LXI Multipurpose Data Acquisition Instrument according to claim 1 is characterized in that:

Said flush bonding processor circuit comprises PowerPC processor (U1); Said PowerPC processor (U1) comprises internal bus interface (U1A), DDR sdram controller interface (U1B), local bus interface (U1C), network MAC interface (U1G), major clock and IO mouth (U1D); Said internal bus interface (U1A) is connected with pci interface (2) communication, and said DDR sdram controller interface (U1B) provides address, data and control link for the DDR dynamic memory circuit; Said local bus interface (U1C) provides interface for the FLASH memory circuit; Said network MAC interface (U1G) provides two-way adaptive network path, and the first via links to each other with the LAN interface telecommunication circuit, the second tunnel be used for triggering PPS clock and the I/O port that management circuits provide IEEE 1588 agreements to IEEE 1588; Major clock is used to the clock input of PowerPC processor in said major clock and the IO mouth (U1D), and the IO mouth is used for triggering management circuit to IEEE 1588 to be provided triggering passage and to the LED indicating module control port is provided.

3. category-B LXI Multipurpose Data Acquisition Instrument according to claim 1 and 2 is characterized in that:

Said category-B LXI interface module also comprises the GPIB/USB interface circuit that is used to realize GPIB/USB hardware path, and local bus interface (U1C) is also for the gpib interface circuit provides interface, and said GPIB/USB interface circuit is connected with local bus interface (U1C).

4. category-B LXI Multipurpose Data Acquisition Instrument according to claim 3 is characterized in that:

Said IEEE 1588 triggers management circuit and comprises PLD FPGA (U20), and LLD [0:7] data line of said PLD FPGA (U20) is connected with the local bus circuit of PowerPC processor (U1); The F1588_IO of said PLD FPGA (U20) is connected with the IEEE1588I/O port of PowerPC processor (U1); PLD FPGA (U20) output terminal is connected with the PPS pulse per second (PPS) F1588_CLKOUT pin of LAN interface circuit.

5. category-B LXI Multipurpose Data Acquisition Instrument according to claim 4 is characterized in that:

Said FLASH memory circuit comprises NOR FLASH chip (U6), the first address latch chip (U4), the second address latch chip (U5) of the 32MB that is used for completion program and data storage and the gate circuit (U7) that is used for data buffering; The said first address latch chip (U4), the second address latch chip (U5), gate circuit (U7) are connected successively; Form buffer circuit, the NOR FLASH chip (U6) of said 32MB is connected with local bus interface (U1C) circuit of PowerPC processor through buffer circuit;

Said DDR dynamic memory circuit comprises a DDR SDRAM storage chip (U2) the 2nd DDR SDRAM storage chip (U3) of two parallel connections, and a said DDR SDRAM storage chip (U2) all is connected with DDR sdram controller interface (U1B) with the 2nd DDR SDRAM storage chip (U3);

Said LAN interface telecommunication circuit comprises network PHY chip (U12), phase inverter (U13), voltage controlled oscillator (Y2) and ∏ type low-pass filter; Signal (CP_OUT) after the PWM width modulation of the input end reception PLD FPGA (U20) of said amplifier (U13); The reverse signal of signal (CP_OUT) is given the input end of ∏ type low-pass filter after the output terminal output PWM width modulation of said amplifier (U13); The output terminal of said ∏ type low-pass filter is connected with voltage controlled oscillator (Y2) control end, and the output terminal of said voltage controlled oscillator (Y2) is connected with network PHY chip (U12).

6. category-B LXI Multipurpose Data Acquisition Instrument according to claim 5; It is characterized in that: the LED indicating module comprises driving circuit (U50), the first common cathode Tricolor LED (D1), the second common cathode Tricolor LED (D2) and the 3rd common cathode Tricolor LED (D3); The said first common cathode Tricolor LED (D1) is connected with driving circuit (U1), and the said second common cathode Tricolor LED (D2) is connected with the major clock of PowerPC processor and the IO mouth of IO mouth (U1D) with the 3rd common cathode Tricolor LED (D3).

7. category-B LXI Multipurpose Data Acquisition Instrument according to claim 6; It is characterized in that: said LAN interface telecommunication circuit comprises network PHY chip (U12), phase inverter (U13), voltage controlled oscillator (Y2) and ∏ type low-pass filter; The input end of said amplifier U13 receives after the PWM width modulation of PLD FPGA (U20) behind the signal (CP_OUT); Reverse signal through phase inverter (U13) output CP_OUT; The reverse signal of the input termination CP_OUT of ∏ type low-pass filter, the output terminal of ∏ type low-pass filter are sent into voltage controlled oscillator (Y2) control end, and the output terminal of said voltage controlled oscillator (Y2) is connected with network PHY chip (U12);

8. category-B LXI Multipurpose Data Acquisition Instrument according to claim 7; It is characterized in that: said GPIB/USB interface circuit comprises gpib interface chip (U10), USB interface chip (U29); Gpib interface chip (U10) links to each other with local bus interface (U1C), and USB interface chip (U29) links to each other with the local bus interface (U1C) of PowerPC processor.

9. category-B LXI Multipurpose Data Acquisition Instrument according to claim 8 is characterized in that:

Also comprise in said DDR sdram controller interface (U1B) and the DDR dynamic memory circuit connection line build-out resistor (RN16～RN26),

Also be provided with clock distribution chip (U43) on the clock input link of said major clock and IO mouth (U1D) and PowerPC processor,

Said DDR dynamic memory circuit also comprises terminating resistor and driven chip (U44); The input end of a said DDRSDRAM storage chip (U2) is connected to terminating resistor (R176-R180), and the input end of said the 2nd DDR SDRAM storage chip (U3) is connected to terminating resistor (R171-R184).

10. category-B LXI Multipurpose Data Acquisition Instrument according to claim 9 is characterized in that: said input-output unit also comprises simulation output unit (42), Digital I unit (43), simulation output control module (16), digital I (17); Said simulation output control module (16) is connected with simulation output unit (42), and said digital I (17) is connected with Digital I unit (43), and an end of said Digital I unit (43) is connected with FPGA unit (1), and its other end is connected with IO interface (6); It comprises current-limiting resistance (20) and diode voltage-limiting protection circuit (10) that is arranged on the IO interface end and the bus switch (9) that is arranged on the FPGA interface end; Said bus switch (9) is used to realize the level conversion function;

Said FPGA unit (1) comprises logical routing module (11), internal clocking (14), other control modules (18), memory control module (13), local bus control module (12) and input/output control module; Said logical routing module (11) is connected with internal clocking (14), other control modules (18), memory control module and input/output control module respectively; Said input/output control module comprises analog input control module (15); Said analog input control module (15) is connected with analog input unit (41), and said memory control module (13) is connected with storer (3); Said logical routing module (11) is connected with pci bus (5) through pci interface (2).

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