CN217508960U - High-speed board of gathering of broadband radio frequency signal - Google Patents

Abstract

The utility model discloses a board is gathered to broadband radio-frequency signal high speed, power module with the FPGA module directly links to each other, power module with the ADC module links to each other through the FMC connector, the FPGA module respectively with the ADC collection module DDR4 storage module the Flash module with interface module links to each other, clock management module respectively with the FPGA module ADC collection module links to each other, clock management module does the ADC collection module the FPGA module provides sampling clock, transmission clock, adjusts the sampling rate through modifying the sampling clock, adjusts transmission rate through modifying the transmission clock in order to realize high sampling rate and high transmission rate, improves the real-time of broadband signal acquisition integrated circuit board to the realization carries out full bandwidth real-time collection to big bandwidth signal.

Description

High-speed board of gathering of broadband radio frequency signal

Technical Field

The utility model relates to a signal acquisition technical field especially relates to a high-speed board of gathering of broadband radio frequency signal.

Background

In the design of collecting broadband radio-frequency signals in the field of wireless communication, the bandwidth and the rate of the broadband radio-frequency signals are limited, a radio-frequency collecting mode of an analog down converter, an ADC and an FPGA framework is adopted at present, the broadband radio-frequency input signals are subjected to frequency conversion through the analog down converter, and then intermediate-frequency and narrow-band signals after the frequency conversion are sampled.

However, the analog down converter is expensive in manufacturing cost, so that the cost of a radio frequency acquisition mode of an architecture of the analog down converter + the ADC + the FPGA is high, and the sampling rate of the radio frequency acquisition mode of the architecture is low, so that full-bandwidth real-time acquisition of a large-bandwidth signal cannot be achieved.

SUMMERY OF THE UTILITY MODEL

In view of the above, an object of the present invention is to provide a high-speed broadband radio frequency signal acquisition board with maximum 5G sampling, adjustable sampling rate, real-time acquisition storage and real-time data transmission, which can perform full-bandwidth real-time acquisition on large-bandwidth signals.

In order to achieve the above object, an embodiment of a first aspect of the present invention provides a broadband radio frequency signal high-speed acquisition board, which includes a broadband receiving front end and a broadband signal acquisition board, wherein the broadband receiving front end is connected to the broadband signal acquisition board;

the broadband signal acquisition board card comprises an FPGA processing carrier board, an FMC-AD acquisition sub-card and a power module, wherein the FPGA processing carrier board is connected with the FMC-AD acquisition sub-card through an FMC connector;

the FPGA processing carrier plate comprises an FPGA module, a DDR4 storage module, a clock management module, a Flash module and an interface module;

the FMC-AD acquisition daughter card comprises an ADC acquisition module;

the power module is directly connected with the FPGA module, the power module is connected with the ADC module through an FMC connector, the FPGA module is respectively connected with the ADC acquisition module, the DDR4 storage module, the Flash module and the interface module, and the clock management module is respectively connected with the FPGA module and the ADC acquisition module.

The utility model discloses an in some embodiments, clock management module does ADC collection module provides sampling clock and transmission clock, clock management module does the FPGA module provides the transmission clock, adjusts the sampling rate through modifying sampling clock, adjusts transmission rate through modifying sampling transmission clock.

In some embodiments of the present invention, the FPGA module is connected to the ADC module through the SPI interface for initialization configuration;

the FPGA module is connected with the clock management module through an SPI interface to carry out initialization configuration.

In some embodiments of the present invention, the ADC module has a radio frequency acquisition input interface all the way, and the ADC module is connected to the broadband receiving front end through the radio frequency acquisition input interface.

In some embodiments of the present invention, the ADC module is connected to the FPGA module through the JESD204B high-speed interface for data transmission.

In some embodiments of the present invention, an internal oscillator is selected for use as a clock source in the clock management module.

In some embodiments of the present invention, an external oscillator is selected for use as a clock source in the clock management module.

In some embodiments of the present invention, the FPGA module caches the received data through the DDR4 module.

In some embodiments of the present invention, the interface module includes an RS232 serial port, a gigabit network interface, a PCIE interface, and a 100G network port;

and the FPGA module transmits the received data to external equipment through the interface module.

Due to the adoption of the technical scheme, compared with the prior art, the utility model have the following advantage:

1. the ADC chip with high sampling rate is used for sampling, the sampling bandwidth is increased, the maximum 5G sampling can be realized, the sampling rate can be adjusted by modifying the sampling clock in the clock management module, the transmission rate can be adjusted by modifying the transmission clock in the clock management module, the high sampling rate and the high transmission rate are realized, the instantaneity of the broadband signal acquisition board card is improved, and the full-bandwidth real-time acquisition of large-bandwidth signals is realized.

2. The radio frequency acquisition mode that the ADC module is adopted to directly acquire the broadband radio frequency signals and digitize the broadband radio frequency signals is low in cost and high in cost performance.

3. The structure that the FPGA is used for processing the carrier plate and the FMC-AD acquisition sub card is adopted, and the modular design enables the carrier plate and the FMC-AD acquisition sub card to have universality.

4. The multi-interface compatibility can adapt to various application scenes.

Drawings

Fig. 1 is a functional block diagram of the present invention;

fig. 2 is the utility model discloses a broadband signal acquisition integrated circuit board layout.

Detailed Description

The foregoing and other technical matters, features and effects of the present invention will be apparent from the following detailed description of the embodiments, which is to be read in connection with the accompanying drawings 1 to 2. The structural contents mentioned in the following embodiments are all referred to the attached drawings of the specification.

A broadband radio frequency signal high-speed acquisition board comprises a broadband receiving front end and a broadband signal acquisition board card, wherein the broadband receiving front end is connected with the broadband signal acquisition board card;

the broadband signal acquisition board card comprises an FPGA processing support plate, an FMC-AD acquisition sub card and a power module, wherein the FPGA processing support plate is connected with the FMC-AD acquisition sub card through an FMC connector;

the FPGA processing carrier plate comprises an FPGA module, a DDR4 storage module, a clock management module, a Flash module and an interface module;

the FMC-AD acquisition daughter card comprises an ADC acquisition module;

the power module is directly connected with the FPGA module, the power module is connected with the ADC module through an FMC connector, the FPGA module is respectively connected with the ADC acquisition module, the DDR4 storage module, the Flash module and the interface module, and the clock management module is respectively connected with the FPGA module and the ADC acquisition module.

When the power is on, the FPGA module is initialized and configured by the BPI Flash in the Flash module; the BPI Flash is selected from MT28GU01GAAA1EGC-0SIT, the capacity is 1GB, 16bits are adopted, and special configuration pins related to Master BPI are mainly located in BANK65, BANK34 and BANK 0.

The FPGA module is connected with the ADC module through the SPI interface and carries out initialization configuration on the ADC module, and the initialization configuration of the ADC module comprises full-scale range setting, input bias voltage and ADC gain setting.

The FPGA module is connected with the clock management module through an SPI interface and carries out initialization configuration on the clock management module.

And storing the initialization configuration file in a Flash module, and automatically loading the initialization configuration file after power-on to complete the initialization configuration of the broadband signal acquisition board card.

The type of a clock management chip in the clock management module is LMK04828, a clock source supports an external oscillator or an internal oscillator, two paths of differential clocks output by the LMK04828 are provided for the ADC module, and three paths of clocks are provided for the FPGA module; the clock management module provides two types of sampling clocks and transmission clocks for the ADC module, provides two types of transmission clocks for the FPGA module, can adjust the sampling rate by modifying the sampling clocks, and adjusts the transmission rate by the transmission clocks so as to realize high sampling rate and high transmission rate, thereby improving the real-time performance of the broadband signal acquisition board card.

The ADC chip in the ADC module is selected to be a high sampling rate chip of an ADC12DJ2700, the sampling rate reaches 5Gbps/s, and the L-band signal can be directly acquired in a full frequency band and digitized through analog-to-digital conversion; the ADC chip is provided with a radio frequency acquisition input interface, the ADC module is connected with the broadband receiving front end through the radio frequency acquisition input interface, receives broadband radio frequency signals transmitted from the broadband receiving front end, the bandwidth range of the broadband radio frequency signals is the full frequency band of L-band signals, the sampling data are obtained after the broadband radio frequency signals are subjected to analog-to-digital conversion, and the sampling data are transmitted to the FPGA module through the JESD204B high-speed interface.

And after the FPGA module processes the sampling data transmitted by the ADC module, the processed sampling data is cached by the DDR4 module or is transmitted to external equipment by the interface module, and the work and transmission of each module are controlled.

The DDR4 module comprises two groups of 64-bit DDR4RDIMM memory banks, the capacity of each group of DDR4RDIMM memory banks can reach 16GB, the DDR4 module supports 32GB cache, the data bit width is 72bits, and the DDR4 module supports 5G sampling full-bandwidth data cache; the interface clock of the DDR4 module can be provided by an external high-performance differential clock, the frequency of the external interface clock is 100MHz, the external interface clock can be converted to other frequencies through an on-chip MMCM, and the VCCO voltage of a corresponding bank is set to be +1.2 v.

The interface module comprises a plurality of interfaces including an RS232 serial port, a gigabit network interface, a PCIE interface and a 100G network interface, and supports the FPGA module to transmit sampling data to external equipment in a plurality of modes;

the FPGA module is connected with full-duplex PCIe 3.0X16 and 100G network ports, real-time transmission of 5G sampling signals can be met, the PCIE interface is led out in a PCIE golden finger mode, PCIE X1, X4, X8 and X16 bandwidth modes are supported, and PCIE3.0 is supported.

The driving chip of the RS232 serial port is selected to be MAX3232EUE, the UART serial port led out by the FPGA module is converted into +3.3V level through a driving chip TXS0108E and then is interconnected with the MAX3232EUE of the RS232 serial port; the UART interface is switched to a DB9 connector for monitoring debugging state information.

And a gigabit network interface is led out from the FPGA module, and the RGMII interface is converted into 1000BASE-T standard output through a PHY chip.

The power supply module directly supplies power to the FPGA processing carrier plate; meanwhile, the power module supplies power to the FMC-AD acquisition sub card through the FMC connector.

The utility model discloses during the specific use, the ADC module passes through the broadband radio frequency and gathers the broadband radio frequency signal that input interface received the broadband and received the front end and transmit, directly adopts and digitize the signal through analog-to-digital conversion broadband radio frequency signal, obtains the sample data to transmit the sample data for through the high-speed interface of JESD204B the FPGA module.

After the FPGA module processes the sampling data transmitted by the ADC module, the processed sampling data is cached by the DDR4 module or is transmitted to external equipment by the interface module, and the work and transmission of each module are controlled.

The DDR4 module is used for caching the sampling data processed by the FPGA module.

The clock management module realizes the control of a working clock and a sampling clock and the control of a source clock.

The Flash module is used for storing an initialization configuration file required by starting the broadband signal acquisition board card.

The power supply module directly supplies power to the FPGA processing carrier plate; meanwhile, the power module supplies power to the FMC-AD acquisition sub card through the FMC connector.

The interface module is used for realizing large data volume interaction between the broadband signal acquisition board card and external equipment.

The above description is provided for further details of the present invention with reference to the specific embodiments, which should not be construed as limiting the present invention; to the utility model discloses affiliated and relevant technical field's technical personnel are based on the utility model discloses under the technical scheme thinking prerequisite, the extension of doing and the replacement of operating method, data all should fall within the utility model discloses within the protection scope.

Claims (9)

1. A broadband radio frequency signal high-speed acquisition board is characterized by comprising a broadband receiving front end and a broadband signal acquisition board card, wherein the broadband receiving front end is connected with the broadband signal acquisition board card;

the broadband signal acquisition board card comprises an FPGA processing support plate, an FMC-AD acquisition sub card and a power module, wherein the FPGA processing support plate is connected with the FMC-AD acquisition sub card through an FMC connector;

the FPGA processing carrier plate comprises an FPGA module, a DDR4 storage module, a clock management module, a Flash module and an interface module;

the FMC-AD acquisition daughter card comprises an ADC acquisition module;

the power module is directly connected with the FPGA module, the power module is connected with the ADC acquisition module through an FMC connector, the FPGA module is respectively connected with the ADC acquisition module, the DDR4 storage module, the Flash module and the interface module, and the clock management module is respectively connected with the FPGA module and the ADC acquisition module.

2. The board of claim 1, wherein the clock management module provides a sampling clock and a transmission clock for the ADC acquisition module, the clock management module provides a transmission clock for the FPGA module, the sampling rate is adjusted by modifying the sampling clock, and the transmission rate is adjusted by modifying the sampling transmission clock.

3. The board of claim 1, wherein the FPGA module is connected to the ADC module via an SPI interface for initialization configuration;

the FPGA module is connected with the clock management module through an SPI interface to carry out initialization configuration.

4. The board of claim 1, wherein the ADC module has a rf acquisition input interface, and the ADC module is connected to the wideband reception front end via the rf acquisition input interface.

5. The board of claim 1, wherein the ADC module is connected to the FPGA module for data transmission via a JESD204B high-speed interface.

6. The board of claim 2, wherein the clock source in the clock management module is an internal oscillator.

7. The board of claim 2, wherein the clock source in the clock management module is an external oscillator.

8. The board of claim 5, wherein the FPGA module buffers received data through the DDR4 storage module.

9. The board of claim 5, wherein the interface module comprises an RS232 serial port, a gigabit network interface, a PCIE interface, and a 100G network interface;

and the FPGA module transmits the received data to external equipment through the interface module.

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