CN108011642A - Transceiver handles board system - Google Patents
Transceiver handles board system Download PDFInfo
- Publication number
- CN108011642A CN108011642A CN201810019293.6A CN201810019293A CN108011642A CN 108011642 A CN108011642 A CN 108011642A CN 201810019293 A CN201810019293 A CN 201810019293A CN 108011642 A CN108011642 A CN 108011642A
- Authority
- CN
- China
- Prior art keywords
- signal
- receiving
- transceiver
- digital signal
- acquisition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/0003—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain
- H04B1/0007—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain wherein the AD/DA conversion occurs at radiofrequency or intermediate frequency stage
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
Abstract
The invention discloses transceiver to handle board system, including signal acquisition playback plate and digital signal panel；The signal acquisition playback plate includes 8 road AD acquisition modules, 2 road frequency agility RF receiving and transmission modules, clock circuit；The signal acquisition playback plate is connected using FMC connectors with digital signal panel；Transceiver processing board mainly completes A/D collections, array received processing, integrated navigation reception processing, transmitting signal generation and the monitoring information transmitting and receiving service of array signal, FMC subcard structures are used by ADC, arrange in pairs or groups and use with the digital signal panel of FMC interfaces, data exchange includes between plate：AD acquisition modules include 16 pairs of high speed serialization LVDS bus transfer adc datas altogether；The two panels chip of frequency agility RF receiving and transmission module includes 24 pairs of high speed serialization LVDS signal transmission ADC and DAC data altogether, and realization possesses 8 passages and fixes frequency point array signal A/D collections with receiving disposal ability, possesses 2 passage frequency agility signal transmitting and receiving disposal abilities.
Description
Technical field
The present invention relates to transceiver to handle board, and in particular to transceiver handles board system.
Background technology
With the development and progress of electronic technology, the generally use of various electronic instruments and equipment, for electronic signal
It is required that higher and higher, the reception and transmitting of signal are played a crucial role in electronic communication field, improve the transmission of signal
Speed, increases the data processing of signal transceiver, needs more functions in use to meet R＆D and production needs.
Existing electronic instrument and equipment have the function of telecommunication, are substantially by transmitting antenna and reception antenna
Collective effect, signal launched and received to realize the transmission of information and data, but with data-handling capacity
Transceiver plate does not have also.
The content of the invention
Transceiver processing board system is provided, possesses 8 passages and fixes frequency point array signal A/D collections with receiving processing energy
Power, possesses 2 passage frequency agility signal transmitting and receiving disposal abilities.
The present invention is achieved through the following technical solutions：
Transceiver handles board system, including signal acquisition playback plate and digital signal panel；The signal is adopted
Collection playback plate includes 8 road AD acquisition modules, 2 road frequency agility RF receiving and transmission modules, clock circuit；The signal acquisition playback plate is adopted
It is connected with FMC connectors with digital signal panel.Consider the versatility of board, FMC subcard structures, and FMC are used by ADC
The digital signal panel collocation of interface uses, and data exchange includes between plate：AD acquisition modules include 16 pairs of high speed serializations altogether
LVDS bus transfer adc datas, 4 pairs of LVDS clocks and SPI and control IO, wherein in order to ensure two panels AD acquisition module chips
Collection signal synchronization, LVDS data and clock will be put on same FPGA_bank；The two of frequency agility RF receiving and transmission module
Piece chip includes 24 pairs of high speed serialization LVDS signal transmission ADC and DAC data altogether, altogether 16 control IO, two groups of CLK with
And SPI controlling bus guides to FMC connectors, wherein LVDS high-speed serial signals and clock will be put into same FPGA_bank；It is real
Now possess 8 passages to fix frequency point array signal A/D collections and receive disposal ability, possess the processing of 2 passage frequency agility signal transmitting and receivings
Ability.
Further, AD acquisition chips select AD9653BCPZ-125.AD9653 is a 4 passage, 16,125MSPS
Analog-digital converter (ADC), sampling hold circuit in built-in piece, sets specifically for low cost, low-power consumption, small size and ease for use
Meter；The switching rate of the product reaches as high as 125MSPS, has outstanding dynamic property and low power consumption characteristic, to small package ruler
Highly significant, ADC requirements are using the power supply of 1.8V single supplies and LVPECL/CMOS/LVDS compatible types sampling speed for very little application
Rate clock signal, to give full play to its working performance；For most of applications, without external reference-voltage source or driving
Device.
Further, frequency agility transceiving chip selects two panels AD9364BBCZ.AD9364 be a 1 passage high-performance of 1x,
High integration RF agile transceivers；The programmability and broadband ability of the device become the preferable choosing of a variety of transceiver applications
Select；The device integrates RF front ends and flexible mixed signal baseband part, integrates frequency synthesizer, being provided for processor can
Digital interface is configured, is imported so as to simplify design；AD9364 operating frequency ranges are 70MHz to 6.0GHz, cover most of spy
Perhaps license and unlicensed band, the bandwidth chahnel scope of support are 200kHz with down toward 56MHz.
Further, digital signal panel uses the framework of DSP+FPGA, and DSP uses TMS320C6455BZTZA processing
Device, FPGA use XC7VX485T-2FFG1157.The I/O signal of XC7VX485T-2FFG1157 has 600 I/O signals, 20 pairs
Serdes receives and dispatches at a high speed universal serial bus, and the signal of comprehensive whole plate, the I/O signal being connected with DSP is no more than 100, removing and FMC
The signal of playback card connection is gathered, other all I/O interface signal statistics are no more than 150, and therefore, the IO and FMC of FPGA connect
Connect no less than 350, the general purpose I/O bus of actual FMC is no more than 200, and FPGA can draw the I/O port of FMC full, it is contemplated that logical
With property, all I/O ports use LVDS difference cablings；Both it can be used for LVDS high-speed serial bus, and can be used for single-ended control
Signal processed.
Compared with prior art, the present invention have the following advantages and advantages：
1st, transceiver processing board system of the present invention, FMC subcard structures, and the numeral letter of FMC interfaces are used by ADC
The collocation of number processing board uses, and data exchange includes between plate：AD acquisition modules include 16 pairs of high speed serialization LVDS bus transfers altogether
Adc data, 4 pairs of LVDS clocks and SPI and control IO, wherein in order to ensure the collection signal of two panels AD acquisition module chips
Synchronous, LVDS data and clock will be put on same FPGA_bank；The two panels chip of frequency agility RF receiving and transmission module wraps altogether
24 pairs of high speed serialization LVDS signal transmission ADC and DAC data are included, 16 control IO, two groups of CLK and SPI controls are total altogether
Line guides to FMC connectors, and wherein LVDS high-speed serial signals and clock will be put into same FPGA_bank；Realization possesses 8 passages
Fixed frequency point array signal A/D collections possess 2 passage frequency agility signal transmitting and receiving disposal abilities with receiving disposal ability；
2nd, transceiver processing board system of the present invention, AD9653 is a 4 passage, 16,125MSPS analog-digital converters
(ADC), sampling hold circuit in built-in piece, is designed specifically for low cost, low-power consumption, small size and ease for use；The product
Switching rate reach as high as 125MSPS, there is outstanding dynamic property and low power consumption characteristic, the application to small package size is very
Significant, ADC requirements are powered using 1.8V single supplies and LVPECL/CMOS/LVDS compatible type sample rate clock signals,
To give full play to its working performance；For most of applications, without external reference-voltage source or driving element；
3rd, transceiver processing board system of the present invention, AD9364 are a 1 passage high-performance of 1x, high integration RF victories
Become transceiver；The programmability and broadband ability of the device become the ideal chose of a variety of transceiver applications；The device collection
RF front ends are integrated with flexible mixed signal baseband part, integrate frequency synthesizer, and providing configurable numeral for processor connects
Mouthful, imported so as to simplify design；AD9364 operating frequency ranges are 70MHz to 6.0GHz, cover most of charter and exempt from
Licensed band, the bandwidth chahnel scope of support are 200kHz with down toward 56MHz.
Brief description of the drawings
Attached drawing described herein is used for providing further understanding the embodiment of the present invention, forms one of the application
Point, do not form the restriction to the embodiment of the present invention.In the accompanying drawings：
Fig. 1 is main assembly block diagram of the present invention.
Embodiment
For the object, technical solutions and advantages of the present invention are more clearly understood, with reference to embodiment and attached drawing, to this
Invention is described in further detail, and exemplary embodiment of the invention and its explanation are only used for explaining the present invention, do not make
For limitation of the invention.
Embodiment
As shown in Figure 1, transceiver processing board system of the present invention, including at signal acquisition playback plate and digital signal
Manage plate；The signal acquisition playback plate includes 8 road AD acquisition modules, 2 road frequency agility RF receiving and transmission modules, clock circuit；It is described
Signal acquisition playback plate is connected using FMC connectors with digital signal panel；AD acquisition modules chip uses AD9653BCPZ-
125；Frequency agility transceiving chip selects two panels AD9364BBCZ；Digital signal panel uses the framework of DSP+FPGA, and DSP is used
TMS320C6455BZTZA processors, FPGA use XC7VX485T-2FFG1157.During implementation, transceiving integrated board is by signal
Collection playback plate and digital signal panel composition, overall dimension is no more than 135 × 135 × 40mm, due to whole transceiver
Change board J30J connectors to be mounted, LED etc., the interface such as RJ45 is all put on digital signal panel, then is gathered back
The position that reserve above-mentioned connector will be snapped on digital signal panel by putting board size；Digital Signal Processing card is according to 135
× 135mm full scale designs, and signal acquisition playback card is then necessarily less than the size, is tentatively set to 115 × 115mm；It is whole to receive
The integrated board height of hair is designed according to no more than 40mm；During implementation, whole plate Power Management Design, subcard power supply passes through DC-DC on plate
To power, support plate offer 5V power supplies and IO accessory power supplys, according to data, AD9653 needs power supply respectively+1.8VA ,+1.8VD ,+
1.3VREF, monolithic maximum power dissipation 708mW；It is respectively+1.3V, auxiliary DAC voltage 3.3V ,+1.0VREF that AD9364, which needs to power,
Reference voltage, 1.8V maximum currents are no more than 330mA, and+3.3V maximum currents are no more than；AD9522 mainly powers as+3.3V, most
Big power consumption is no more than 1.3W, to ensure good power supply noise performance, improves the SNR of ADC collections, power supply first uses switch by electricity
Pressure drop is got off, and all gives each chip power supply using the LDO voltages changed afterwards.
Above-described embodiment, has carried out the purpose of the present invention, technical solution and beneficial effect further
Describe in detail, it should be understood that the foregoing is merely the embodiment of the present invention, be not intended to limit the present invention
Protection domain, within the spirit and principles of the invention, any modification, equivalent substitution, improvement and etc. done, should all include
Within protection scope of the present invention.
Claims (4)
1. transceiver handles board system, it is characterised in that plays back plate and digital signal panel including signal acquisition；Institute
Stating signal acquisition playback plate includes 8 road AD acquisition modules, 2 road frequency agility RF receiving and transmission modules, clock circuit；The signal acquisition
Playback plate is connected using FMC connectors with digital signal panel.
2. transceiver according to claim 1 handles board system, it is characterised in that the AD acquisition modules chip is adopted
Use AD9653BCPZ-125.
3. transceiver according to claim 1 handles board system, it is characterised in that the frequency agility transceiving chip choosing
With two panels AD9364BBCZ.
4. transceiver according to claim 1 handles board system, it is characterised in that the digital signal panel is adopted
With the framework of DSP+FPGA, DSP uses TMS320C6455BZTZA processors, and FPGA uses XC7VX485T-2FFG1157.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810019293.6A CN108011642A (en) | 2018-01-09 | 2018-01-09 | Transceiver handles board system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810019293.6A CN108011642A (en) | 2018-01-09 | 2018-01-09 | Transceiver handles board system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108011642A true CN108011642A (en) | 2018-05-08 |
Family
ID=62050393
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810019293.6A Withdrawn CN108011642A (en) | 2018-01-09 | 2018-01-09 | Transceiver handles board system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108011642A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110392185A (en) * | 2019-07-17 | 2019-10-29 | 珠海纳睿达科技有限公司 | A kind of signal acquisition subcard work system |
| CN110987007A (en) * | 2019-12-06 | 2020-04-10 | 四川九洲空管科技有限责任公司 | Takang and range finder simulator system and method based on agile frequency transceiver |
| CN112511176A (en) * | 2020-10-13 | 2021-03-16 | 北京电子工程总体研究所 | Cold standby redundancy system and method based on frequency agile converter |
| CN113965220A (en) * | 2021-09-30 | 2022-01-21 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Universal interface processing device for radio frequency terminal |
-
2018
- 2018-01-09 CN CN201810019293.6A patent/CN108011642A/en not_active Withdrawn
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110392185A (en) * | 2019-07-17 | 2019-10-29 | 珠海纳睿达科技有限公司 | A kind of signal acquisition subcard work system |
| CN110987007A (en) * | 2019-12-06 | 2020-04-10 | 四川九洲空管科技有限责任公司 | Takang and range finder simulator system and method based on agile frequency transceiver |
| CN112511176A (en) * | 2020-10-13 | 2021-03-16 | 北京电子工程总体研究所 | Cold standby redundancy system and method based on frequency agile converter |
| CN113965220A (en) * | 2021-09-30 | 2022-01-21 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Universal interface processing device for radio frequency terminal |
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Application publication date: 20180508 |
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| WW01 | Invention patent application withdrawn after publication |