CN202918281U

CN202918281U - A universal expandable digital intermediate frequency receiver

Info

Publication number: CN202918281U
Application number: CN 201220652978
Authority: CN
Inventors: 高攀峰
Original assignee: Individual
Current assignee: Individual
Priority date: 2012-12-03
Filing date: 2012-12-03
Publication date: 2013-05-01
Anticipated expiration: 2022-12-03

Abstract

The utility model discloses a digital intermediate frequency receiver comprising a multichannel ADC module, a multichannel bridging module, and a multichannel digital down conversion ASIC module, a multichannel FPGA processing module, a multichannel DSP processing module, a multi-interface output interface output module, and a DSP main control module. The data output of the multichannel ADC module is connected with the data input of the multichannel bridging module. The data output of the multichannel bridging module is connected with the data input of the multichannel digital down conversion ASIC module. The data output of the multichannel digital down conversion ASIC module is connected with the data input of the multichannel FPGA processing module. Bidirectional multichannel data connection is established between the multichannel FPGA processing module and the multichannel DSP processing module. The multichannel FPGA processing module provides expansion interfaces for peripheral equipment. Final results is outputted by the data output of the multichannel DSP processing module via the multi-interface output interface output module. The digital intermediate frequency receiver has characteristics of good universality, high processing efficiency, low cost, and benefits to industrialization.

Description

A kind of universal extendible digital if receiver

Affiliated technical field

The utility model relates to a kind of digital if receiver, especially has the digital if receiver with good Universal and scalability of multichannel flexible combination and parallel processing structure, and the technical field of this utility model belongs to the software wireless electrical domain.

Background technology

Traditional radio system is the artificial antenna electric system, is generally super-heterodyne architecture.

As shown in Figure 1, the traditional analog radio receiving system of super-heterodyne architecture, comprise RF front-end module 101, down conversion module 102, local oscillator module 103, intermediate frequency bandpass filtering modules block 104, demodulation module 105 and baseband processing module 106, radiofrequency signal is through after processing successively with upper module, be converted to final result and export to user 107, above each module all adopts analog form, used frequency range, modulation system in the different communication systems, all corresponding to different hardware configurations, thereby be difficult to intercommunication between the different communication systems.

In order to solve existing compatible difficult, the difficult problems such as upgrading is difficult, construction cycle length of traditional analog wireless communication system, people have proposed the concept of software radio.The central idea of software radio is that one of structure has opening, standardization, modular general hardware platform, various functions such as working frequency range, modulation /demodulation type, data format, encryption mode, communication protocol etc. are finished with software programming, and make broadband A/D transducer and the as close as possible antenna of DA transducer, have high degree of flexibility to develop, an open new generation of wireless communication system.

The structure of comparatively ideal software radio system is that ADC, DAC directly realize in radio frequency part, but this has proposed very high requirement to AD, DA and follow-up Digital Signal Processing speed, because the at present restriction of device processing speed, be difficult to realize radiofrequency signal is directly carried out sampling with high precision and carried out follow-up digital processing, but the sampling with high precision and the follow-up digital processing that realize intermediate-freuqncy signal are practicable, are to realize at present a kind of preferred option of software radio so adopt the digital intermediate frequency receiver with wide band technology.

As shown in Figure 2, present feasible software radio receiving system, comprise RF front-end module 101, down conversion module 102., local oscillator module 103, intermediate frequency bandpass filtering modules block 104, ADC module 202, Digital Down Converter Module 203 and digital base band processor module 204, radiofrequency signal is converted to final result and exports to user 107 through after processing successively with upper module.Wherein, assembly 201 namely constitutes a digital if receiver, comprises ADC module 202, Digital Down Converter Module 203 and digital base band processor module 204.

Present a lot of digital if receivers all design for certain concrete application, and the technical scheme difference of different receivers is large, and versatility is poor, and cost is higher, and cost performance is low, often can only be as experiment porch, and veritably commercialization.

From selected technical scheme, present digital if receiver is broadly divided into following three classes:

(1) ASIC (application-specific integrated circuit (ASIC), Application Specific Integrated Circuit) scheme

(2) DSP (digital signal processor, Digital Signal Processor) scheme

(3) FPGA (field programmable gate array, Field Programmable Gate Array) scheme

Fig. 3 A is depicted as the digital if receiver 305 of ASIC scheme, mainly is made of ADC module 202, ASIC module 301, output module 304; The major advantage of ASIC scheme receiver is that the design cycle is short, and simple in structure, cost is lower, but its very flexible, versatility is poor; Fig. 3 B is depicted as the digital if receiver 306 of DSP scheme, mainly is made of ADC module 202, DSP module 302, output module 304; The advantage of DSP scheme receiver is that serial process speed is high, and addressing system is flexible, and suitable processing has the algorithm of complex control structure, but its parallel processing capability is relatively poor; Fig. 3 C is depicted as the digital if receiver 307 of FPGA scheme, mainly is made of ADC module 202, FPGA module 303, output module 304; The advantage of FPGA scheme receiver is that parallel processing speed is high, is fit to the deal with data amount large, the relatively simple algorithm of operating structure, but be not suitable for processing the algorithm with complex control structure.The scheme that a small amount of DSP and FPGA combination are also arranged at present, but versatility is still good not.

Often all based on the different designs that should be used for, the technical scheme difference is large for the receiver of the above three kinds of technical scheme, and versatility is poor, if concrete the application had relatively high expectations to systematic function, then the cost of above technical scheme can be very high, and cost performance is lower.

From receiving on the system, present digital if receiver roughly is divided into following two classes:

(1) based on the digital if receiver of passage Digital Down Convert, is designated hereinafter simply as passage Digital Down Convert receiver;

(2) based on the channelizing digital if receiver of multiphase filtering, be designated hereinafter simply as the multiphase filtering channelized receiver.

The advantage of passage Digital Down Convert receiver is, concentrate in the visual field, can change neatly centre frequency and adjust bandwidth, is fit to do flexibly that passage receives, but number of channels is few, lacks the frequency range Global Information, is difficult to search for, monitor and intercept and capture the signal of full probability.

The advantage of multiphase filtering channelized receiver is, number of channels is many, affords a wide field of vision, and can realize all-probabity interception, be fit to do full probability and receive, but structure fix, parameter is adjusted in inconvenience, lacks flexibility.

The utility model content

Above from technical scheme and the pluses and minuses of present digital if receiver that received two angle analysis of system, the subject matter of digital if receiver is that the technical scheme difference is large at present, versatility is poor, and cost is higher, cost performance is low, in order to overcome the shortcoming of prior art, the utility model provides a kind of extendible digital if receiver with multichannel flexible combination and parallel processing structure, this receiver combines the ASIC scheme, the DSP scheme, the advantage of FPGA scheme, can be used as simultaneously multichannel passage Digital Down Convert receives, can be used as again full probability receives, the reception that is applicable to two types is used, and has good Universal and scalability.

The purpose of this utility model is achieved through the following technical solutions: the extendible digital if receiver with multichannel flexible combination and parallel processing structure, this receiver comprises: multichannel ADC module, the multichannel bridge module, multi-channel digital down-conversion ASIC module, multichannel FPGA processing module, multichannel DSP processing module, many interfaces output module and DSP top control module, the data output of described multichannel ADC module is connected with the data input of described multichannel bridge module, the data output of described multichannel bridge module is connected with the data input of described multi-channel digital down-conversion ASIC module, the data output of described multi-channel digital down-conversion ASIC module is connected with the data input of described multichannel FPGA processing module, there are the two-way multi-channel data to connect between described multichannel FPGA processing module and the described multichannel DSP processing module, described multichannel FPGA processing module externally provides expansion interface, the data output of described multichannel DSP processing module is carried out the output of final result by described many interfaces output module, described DSP top control module is controlled described multichannel bridge module, described multichannel DSP processing module and described many interfaces output module, described multichannel DSP processing module receives the control command of described DSP top control module, and controls described multi-channel digital down-conversion ASIC module and described multichannel FPGA processing module according to control command.

Described multichannel ADC module comprises the ADC chip of a plurality of concurrent workings, and total AD number of channels is H, H＞1.

Described multichannel bridge module is realized with CPLD or FPGA.

Described multi-channel digital down-conversion ASIC module comprises the multi-channel digital down-conversion asic chip of a plurality of concurrent workings, the Digital Down Convert number of channels of described multi-channel digital down-conversion ASIC module is J, J＞H, H are the AD number of channels of described multichannel ADC module.

Described multichannel FPGA processing module comprises the fpga chip of a plurality of concurrent workings, has bi-directional data to connect between each fpga chip, and each fpga chip externally provides expansion interface.

Described multichannel DSP processing module comprises the dsp chip of a plurality of concurrent workings.

Described many interfaces output module comprise in USB, gigabit Ethernet, WIFI and the UART interface any one or multiple, the quantity of every kind of interface is not limit.

Described multichannel bridge module is configured to H the AD passage of J passage flexible allocation of multi-channel digital down-conversion ASIC module to multichannel ADC module, realize the flexible combination between AD passage and the Digital Down Convert passage, making this receiver can be used as multichannel passage Digital Down Convert receives, can be used as again full probability receives, the reception that is applicable to two types is used, and has good versatility.

Existing digital if receiver mostly designs for certain concrete application, the technical scheme difference of different receivers is large, versatility is poor, and cost is higher, cost performance is low, often can only be as experiment porch, and veritably commercialization, the utility model compared with prior art has following beneficial effect:

(1) receive path is many, and passage configuration and combination are flexible, and application mode is flexible, both can be used as flexibly passage reception, can be used as again full probability and receives, and versatility is good, and the scope of application is wide, can be applicable to a plurality of fields such as radar, communication, observing and controlling:

(a) a plurality of AD passages, number of channels is H, H＞1, a plurality of Digital Down Convert passages, number of channels are J, J＞H;

(b) but various parameter flexible configuration such as the centre frequency of each passage, bandwidth, filter coefficient in the multi-channel digital down-conversion ASIC module;

(c) but the AD passage is connected connection and combination flexible configuration with the Digital Down Convert passage, thereby this receiver both can be used as flexibly that passage receives, and can be used as again full probability and received.

(2) favorable expandability

(a) each fpga chip of multichannel FPGA processing module externally provides expansion interface, and expansion interface can external FPGA expansion board clamping, thereby strengthens the disposal ability of the multichannel FPGA processing module of receiver;

(b) expansion interface can also be as outbound data output.

(3) receptivity is good, and disposal ability is strong, and higher treatment effeciency is arranged:

(a) ASIC, DSP and three schemes of FPGA are carried out good combination, combined the advantage of ASIC, DSP and three schemes of FPGA, can bring into play ASIC, DSP and FPGA advantage separately;

(b) structure of multi-channel parallel processing, disposal ability is strong, and higher treatment effeciency is arranged.

(4) cost is low, and cost performance is high, is beneficial to industrialization:

(a) high-end device is ten times of low side devices impose such as its speed, and its price may be equivalent to tens times even hundreds of times of low side devices impose.In the big data quantity signal is processed, adopt a plurality of low and middle-end devices to carry out parallel processing, can obtain the performance higher than high-end single processor system with lower cost, higher cost performance is arranged;

(b) design feature of processing based on this receiver multi-channel parallel, each passage need not be selected the most expensive in the industry FPGA and DSP device on the receiver, only need select Eco-power device, take full advantage of ASIC, FPGA, DSP associated treatment structure and multi-channel parallel and process the advantage of structure, can satisfy a large amount of practical applications, thus this receiver to have a cost low, cost performance is high, be beneficial to industrialization, be beneficial to the advantage of popularization.

Description of drawings

Shown in Figure 1 is the structured flowchart of the traditional analog radio receiving system of super-heterodyne architecture;

Shown in Figure 2 is the structured flowchart of at present feasible software radio receiving system;

It is the structured flowchart of the digital if receiver of ASIC scheme shown in Fig. 3 A;

It is the structured flowchart of the digital if receiver of DSP scheme shown in Fig. 3 B;

It is the structured flowchart of the digital if receiver of FPGA scheme shown in Fig. 3 C;

Shown in Figure 4 is the structured flowchart of digital if receiver of the present utility model;

Shown in Figure 5 is the structured flowchart of multi-channel digital down-conversion ASIC module in the utility model;

Shown in Figure 6 is the structured flowchart of multichannel FPGA processing module in the utility model;

Shown in Figure 7 is the structured flowchart of multichannel DSP processing module in the utility model;

Shown in Figure 8 is an allocation plan schematic diagram that by the multichannel bridge module receiver of embodiment is configured to multichannel passage Digital Down Convert receiver among the utility model embodiment;

Shown in Figure 9 is an allocation plan schematic diagram that by the multichannel bridge module receiver of embodiment is configured to the full probability receiver among the utility model embodiment;

Main symbol description

101～RF front-end module, 102～down conversion module, 103～local oscillator module

104～intermediate frequency bandpass filtering modules block, 105～demodulation module, 106～baseband processing module

107～user

Main composition 202～ADC module of 201～digital if receiver

203～Digital Down Converter Module, 204～digital base band processor module

301～ASIC module, 302～DSP module, 303～FPGA module

304～output module

The digital if receiver of 305～AISC scheme

The digital if receiver of 306～DSP scheme

The digital if receiver of 307～FPGA scheme

401～multichannel ADC module, 402～multichannel bridge module

403～multi-channel digital down-conversion ASIC module

404～multichannel FPGA processing module, 415～expansion interface, 405～multichannel DSP processing module

406～many interfaces output module, 407～DSP top control module, 408～bridge module control bus

409～output control bus, 410～Digital Down Convert Partial controll bus group

411～FPGA Partial controll bus group, 412～DSP control bus

413～FPGA-DSP local data bus group

414～have an extendible digital if receiver of multichannel flexible combination and parallel processing structure

501_m～m multichannel asic chip

502_m～m railway digital down-conversion Partial controll bus

601_n～n fpga chip 602_n～n road FPGA Partial controll bus

603_n～n FPGA expansion interface

A 701_k～k dsp chip

The the 1st to the 6 road AD passage among 801_1 to 801_6～embodiment

The connection of 36 Digital Down Convert passages signal among 802～embodiment

The a certain road of 6 road AD passages among 901～embodiment

Embodiment

Below in conjunction with drawings and Examples, the utility model is described in further detail, but execution mode of the present utility model is not limited to this.

The background technology chapters and sections are from technical scheme and the pluses and minuses of present digital if receiver that received two angle analysis of system, the subject matter of digital if receiver is that the technical scheme difference is large at present, versatility is poor, and cost is higher, cost performance is low, in order to overcome the shortcoming of prior art, the utility model provides a kind of extendible digital if receiver with multichannel flexible combination and parallel processing structure, as shown in Figure 4, assembly 414 is the extendible digital if receiver with multichannel flexible combination and parallel processing structure, this receiver is comprised of following part: multichannel ADC module 401, multichannel bridge module 402, multi-channel digital down-conversion ASIC module 403, multichannel FPGA processing module 404, multichannel DSP processing module 405, many interfaces output module 406 and DSP top control module 407; The data output of multichannel ADC module 401 is connected with the data input of multichannel bridge module 402; The data output of multichannel bridge module 402 is connected with the data input of multi-channel digital down-conversion ASIC module 403; The data output of multi-channel digital down-conversion ASIC module 403 is connected with the data input of multichannel FPGA processing module 404; Multichannel FPGA processing module 404 is connected with multichannel DSP processing module by FPGA-DSP local data bus group 413 and is carried out two-way connection; Multichannel FPGA processing module 404 externally provides expansion interface 415; The data output of multichannel DSP processing module 405 is carried out the output of final result by many interfaces output module 406; DSP top control module 407 is by bridge module control bus 408 control multichannel bridge modules 402, by DSP control bus 412 control multichannel DSP processing modules 405, by output control bus 409 many interfaces of control output modules 406; Multichannel DSP processing module 405 receives the control command of DSP top control module 407, and by Digital Down Convert Partial controll bus group 410 control multi-channel digital down-conversion ASIC modules 403, by FPGA Partial controll bus group 411 control multichannel FPGA processing modules 404.

In the utility model, described multichannel ADC module 401 comprises the ADC chip of a plurality of concurrent workings, and total AD number of channels is H, H＞1.Adopt the ADC chip of a plurality of concurrent workings can increase the AD number of channels of receiver, enlarge the scope of application of receiver, strengthen versatility.In this embodiment, consider the indexs such as the dynamic range of receiver and sensitivity, the ADC chip has been selected the ADC chip of high accuracy and high sampling rate, as shown in Figure 8, in this embodiment, the AD port number H=6 that multichannel ADC module 401 is total, the assembly numbering of each AD passage is followed successively by 801_1,801_2,801_3,801_4,801_5 and 801_6.

In the utility model, described multichannel bridge module 402 usefulness CPLD or FPGA realize.In this embodiment, multichannel bridge module 402 usefulness FPGA realize.The data-handling capacity of 402 couples of FPGA of described multichannel bridge module is less demanding, and this embodiment has been selected the fpga chip of the many pins of low-resource.

As shown in Figure 5, multi-channel digital down-conversion ASIC module 403 described in the utility model, the multi-channel digital down-conversion asic chip that comprises a plurality of concurrent workings, the assembly of each multi-channel digital down-conversion asic chip numbering be followed successively by 501_1,501_2 ... 501_m, m is the positive integer more than or equal to 1, the Digital Down Convert number of channels of described multi-channel digital down-conversion ASIC module 403 is J, and J＞H, H are the AD number of channels of described multichannel ADC module 401.As shown in Figure 8, in this embodiment, selected 66 passage Digital Down Convert asic chips to realize multi-channel digital down-conversion ASIC module 403, the assembly numbering of 66 passage Digital Down Convert asic chips is followed successively by 803_1,803_2,803_3,803_4,803_5 and 803_6, in this embodiment, total Digital Down Convert port number J=36, wherein each passage in each 6 passage asic chip is all integrated high-precision digital quadrature low-converter, a plurality of programmable coefficients FIR filters and a plurality of half-band width decimation filter, and programmable digital AGC.

As shown in Figure 5, multi-channel digital down-conversion ASIC module 403 described in the utility model, by Digital Down Convert Partial controll bus group 410, accept the control of described multichannel DSP processing module 405, the assembly of each Digital Down Convert Partial controll bus of Digital Down Convert Partial controll bus group 410 inside numbering be followed successively by 502_1,502_2 ... 502_m, control respectively multi-channel digital down-conversion ASIC module 403 inner corresponding multi-channel digital down-conversion asic chip 501_1,501_2 ... 501_m, m are the positive integer more than or equal to 1.

As shown in Figure 6, described multichannel FPGA processing module 404, the fpga chip that comprises a plurality of concurrent workings, there is bi-directional data to connect between each fpga chip, the assembly numbering of each fpga chip is followed successively by 601_1,601_2,601_n, n is the positive integer more than or equal to 1, multichannel FPGA processing module 404 is by FPGA Partial controll bus group 411, accept the control of described multichannel DSP processing module 405, the assembly numbering of each FPGA Partial controll bus of FPGA Partial controll bus group 411 inside is followed successively by 602_1,602_2,602_n, control respectively multichannel FPGA processing module 404 inner corresponding fpga chip 601_1,601_2,601_n, n is the positive integer more than or equal to 1, each fpga chip externally provides expansion interface, numbering is followed successively by 603_1,603_2,603_n, n is the positive integer more than or equal to 1, expansion interface can external FPGA expansion board clamping, thereby strengthen the disposal ability of the multichannel FPGA processing module of receiver, can also be as outbound data output.This embodiment has used 3 fpga chips economical, that disposal ability is moderate to realize multichannel FPGA processing module 404, at 12 signal processing channels of the inner realization of every FPGA, the signal input part of per 1 FPGA receives the signal output from per 2 Digital Down Convert asic chips, 3 fpga chips and 6 Digital Down Convert AISC chips form 3 groups altogether, there is bi-directional data to connect between 3 FPGA simultaneously, each FPGA externally provides expansion interface, and 3 FPGA externally provide 3 expansion interfaces altogether.

As shown in Figure 7, described multichannel DSP processing module 405 comprises the dsp chip of a plurality of concurrent workings, the assembly of each dsp chip numbering be followed successively by 701_1,701_2 ... 701_k, k is the positive integer more than or equal to 1, the control that multichannel DSP processing module 405 is accepted from DSP top control module 407 by DSP control bus 412, and respectively by Digital Down Convert Partial controll bus group 410 and FPGA Partial controll bus group 411, multi-channel digital down-conversion ASIC module 403 and multichannel FPGA processing module 404 are controlled.This embodiment has used 6 dsp chips economical, that disposal ability is moderate to realize multichannel DSP processing module 405, and every dsp chip is responsible for processing the data of 6 passages, and 6 dsp chip concurrent workings are finished the data of 36 passages and processed.

Described many interfaces output module 406 comprise in USB, gigabit Ethernet, WIFI and the UART interface any one or multiple, the quantity of every kind of interface is not limit.In this embodiment, many interfaces output module 406 has been selected the FPGA scheme, and design has realized 1 USB interface, 1 gigabit ethernet interface, 3 UART interfaces and 1 WIFI interface.

In the utility model, multichannel bridge module 402 is configured to J passage flexible allocation of multi-channel digital down-conversion ASIC module 403 H AD passage to multichannel ADC module 401, thereby realize the flexible combination of AD passage and Digital Down Convert passage, making this receiver can be used as multichannel passage Digital Down Convert receives, can be used as again full probability receives, the reception that is applicable to two types is used, enlarged the scope of application of this receiver, strengthened versatility, now based on the present embodiment, the operation principle of above-mentioned multichannel bridge module 402 is described in detail as follows:

(1) as shown in Figure 8, assembly 801_1 to 801_6 is the 1st to the 6 road AD passage among the embodiment, assembly 802 is the connection signal of 36 Digital Down Convert passages among the embodiment, multichannel bridge module 402 is configured to change the annexation of input pin and output pin, 36 Digital Down Convert passages are averagely allocated to 6 AD passages, the receiver of the present embodiment is configured to multichannel passage Digital Down Convert receiver, makes this receiver be applicable to multichannel passage Digital Down Convert and receive.

(2) as shown in Figure 9, assembly 901 is a certain road of 6 road AD passages among the embodiment, assembly 802 is the connection signal of 36 Digital Down Convert passages among the embodiment, multichannel bridge module 402 is configured to change the annexation of input pin and output pin, 36 Digital Down Convert passages are all distributed to 1 AD passage, remaining AD passage can temporarily leave unused, thereby the receiver of the present embodiment is configured to the full probability receiver of 36 passages, makes this receiver be applicable to full probability and receives.

(3) according to different application, also can adopt other flexibly methods of salary distribution.

Existing digital if receiver mostly designs for certain concrete application, the technical scheme difference of different receivers is large, versatility is poor, generally can not be applicable to simultaneously passage Digital Down Convert reception and full probability receives, be not suitable in multi-field application, have relatively high expectations if concrete interface applications is received the machine systematic function, then the receiver cost of prior art scheme can be very high, cost performance is low, is unfavorable for commercialization.

The advantage of this embodiment is as follows:

(1) receive path is many, and passage configuration and combination are flexible, and application mode is flexible, both can be used as flexibly passage reception, can be used as again full probability and receive, and versatility is good, and the scope of application is wide, can be applicable to a plurality of fields such as radar, communication, observing and controlling

(a) 6 AD passages, 36 Digital Down Convert passages;

(c) but the AD passage is connected connection and combination flexible configuration with the Digital Down Convert passage, thereby this receiver both can be used as flexibly that passage receives, and can be used as again full probability and receive;

(2) receptivity is good, and disposal ability is strong, and higher treatment effeciency is arranged

(a) the embodiment receiver has carried out good combination to ASIC, DSP and three schemes of FPGA, combines the advantage of ASIC, DSP and three schemes of FPGA, can bring into play ASIC, DSP and FPGA advantage separately;

(b) the embodiment receiver has 6 ASIC, 3 FPGA, and 6 DSP, the structure that adopts multi-channel parallel to process, disposal ability is strong, and higher treatment effeciency is arranged;

(3) favorable expandability

(a) 3 of multichannel FPGA processing module FPGA externally provide 3 expansion interfaces, and expansion interface can external FPGA expansion board clamping, thereby strengthen the disposal ability of the multichannel FPGA processing module of receiver;

(b) expansion interface can also be as outbound data output.

(4) cost is low, and cost performance is high, is beneficial to industrialization

(b) in this embodiment, design feature based on the processing of this receiver multi-channel parallel, each passage need not be selected the most expensive in the industry FPGA and DSP device on the receiver, has all selected in the industry Eco-power device, takes full advantage of the advantage that ASIC, FPGA, DSP associated treatment and multi-channel parallel are processed, cost with economy, realized powerful disposal ability, thus this embodiment receiver to have a cost low, cost performance is high, be beneficial to industrialization, be beneficial to the advantage of popularization.

Described embodiment is execution mode of the utility model; but execution mode of the present utility model is not subjected to the restriction of described embodiment; other any do not deviate from change, the modification made under the utility model Spirit Essence and the principle, substitutes, combination, simplify; all should be the substitute mode of equivalence, be included within the protection range of the present utility model.

Claims

1. digital if receiver, it is characterized in that, comprise: multichannel ADC module, the multichannel bridge module, multi-channel digital down-conversion ASIC module, multichannel FPGA processing module, multichannel DSP processing module, many interfaces output module and DSP top control module, the data output of described multichannel ADC module is connected with the data input of described multichannel bridge module, the data output of described multichannel bridge module is connected with the data input of described multi-channel digital down-conversion ASIC module, the data output of described multi-channel digital down-conversion ASIC module is connected with the data input of described multichannel FPGA processing module, there are the two-way multi-channel data to connect between described multichannel FPGA processing module and the described multichannel DSP processing module, described multichannel FPGA processing module externally provides expansion interface, the data output of described multichannel DSP processing module is carried out the output of final result by described many interfaces output module, described DSP top control module is controlled described multichannel bridge module, described multichannel DSP processing module and described many interfaces output module, described multichannel DSP processing module receives the control command of described DSP top control module, and controls described multi-channel digital down-conversion ASIC module and described multichannel FPGA processing module according to control command.

2. digital if receiver according to claim 1, it is characterized in that: described multichannel ADC module comprises the ADC chip of a plurality of concurrent workings, total AD number of channels is H, H＞1.

3. digital if receiver according to claim 1 is characterized in that: described multichannel bridge module is realized with CPLD or FPGA.

4. digital if receiver according to claim 2, it is characterized in that: described multi-channel digital down-conversion ASIC module comprises the multi-channel digital down-conversion asic chip of a plurality of concurrent workings, the Digital Down Convert number of channels of described multi-channel digital down-conversion ASIC module is J, J＞H, H are the AD number of channels of described multichannel ADC module.

5. digital if receiver according to claim 1, it is characterized in that: described multichannel FPGA processing module comprises the fpga chip of a plurality of concurrent workings, has bi-directional data to connect between each fpga chip, each fpga chip externally provides expansion interface.

6. digital if receiver according to claim 1, it is characterized in that: described multichannel DSP processing module comprises the dsp chip of a plurality of concurrent workings.

7. digital if receiver according to claim 1 is characterized in that: described many interfaces output module comprise in USB, gigabit Ethernet, WIFI and the UART interface any one or multiple, the quantity of every kind of interface is not limit.

8. digital if receiver according to claim 3, it is characterized in that, described multichannel bridge module is configured to a plurality of AD passages of a plurality of Digital Down Convert passage flexible allocation of multi-channel digital down-conversion ASIC module to described multichannel ADC module are realized the flexible combination between AD passage and the Digital Down Convert passage.