CN103544470A

CN103544470A - Double-color infrared isomerism parallel automatic air target identifier for movable platform

Info

Publication number: CN103544470A
Application number: CN201310336492.7A
Authority: CN
Inventors: 钟胜; 张天序; 高士英; 桑红石; 颜露新; 左峥嵘; 王建辉; 徐文辉; 王顺; 谭崇涛
Original assignee: Huazhong University of Science and Technology
Current assignee: Huazhong University of Science and Technology
Priority date: 2013-08-05
Filing date: 2013-08-05
Publication date: 2014-01-29
Anticipated expiration: 2033-08-05
Also published as: CN103544470B

Abstract

The invention discloses a double-color infrared isomerism parallel automatic air target identifier for a movable platform. The target identifier comprises a switching network and at least one processing part. Each processing part is connected with the switching network through an input FIFO (first in first out) interface, a synchronous storage output interface and a control line. The switching network is used for dynamically connecting different input FIFO interfaces and the synchronous storage output interfaces. Each processing part is used for completing various algorithm functions during automatic target identification. Each input FIFO interface is used for caching input to-be-processed image data. Each synchronous storage output interface is used for caching to-be-output processed image data. Each control line is used for controlling data transmission during image data transmission. Due to the fact that the uniform switching network with cache is used, total dynamic mutual connection among different processing parts is guaranteed, resource consumption is reduced, and system resource utilization efficiency is increased.

Description

A kind of moving platform air target Dual band IR isomery automatic target recognizer that walks abreast

Technical field

The invention belongs to digital signal processing technique field, more specifically, relate to the parallel automatic target recognizer of a kind of moving platform air target Dual band IR isomery.

Background technology

The identification of air target imaging automatic target belongs to imaging Target Recognition.Although aerial target background is very not complicated, but aerial target is generally less, translational speed is very fast, cause the identification of aerial target difficulty very, and the blocking of cloud layer, the various conditions such as backlight and intense laser interfere are brought very large impact to the stability of the accuracy of identification of target and identification.Therefore the algorithm, adopting in the identification of air target imaging automatic target is very complicated.

Air target imaging automatic Target Recognition System needs data volume to be processed large, and algorithm is complicated, so just the software and hardware resources of system has been proposed to very high requirement, and particularly, in the situation that moving platform volume power consumption is limited, the design difficulty of system is very large.

Along with the development of technology, the increase of demand, the framework of traditional image processing system more and more can not meet or be difficult to meet the demand of design.Research more rationally, more efficient imaging automatic Target Recognition System is under the requirement condition in the low-power consumption of moving platform software and hardware computational resource finite sum, and improving target accuracy of identification and system real time aspect has very important meaning.

Summary of the invention

Above defect or Improvement requirement for prior art, the invention provides the parallel automatic target recognizer of a kind of moving platform air target Dual band IR isomery, its object is to solve under the requirement of moving platform software and hardware computational resource finite sum low-power consumption, the technical matters that aerial target is identified.

For achieving the above object, the invention provides the parallel automatic target recognizer of a kind of moving platform air target Dual band IR isomery, comprise: switching network and at least one processing element, between described processing element and described switching network, pass through input fifo interface, synchronous memories output interface and control line connect, described switching network is for different described input fifo interface and the described synchronous memories output interfaces of dynamic link, described processing element has been used for the required various algorithm function of automatic target identifying, described input FIFO is for the pending view data of buffer memory input, described synchronous memories output interface is for the to be exported view data of handling of buffer memory, described control line is used in the control data transmission of image data transmission process.

The present invention has adopted dynamic buffering structure to link different processing element, and the use of input FIFO and synchronous memories output interface has solved the interconnect problem that the difference between different pieces of information width, different pieces of information speed, distinct interface causes effectively.The use of switching network guarantee between different disposal parts dynamically complete interconnected in, reduced resource consumption, improved the level of resources utilization of system.

Preferably, described processing element comprises field programmable gate array (Field Programmable Gate Array, FPGA) module, and two nonuniformity correction SOC (system on a chip) (System on Chip, SoC) module, two multiple-stage filtering special IC (Application Specific Integrated Circuit, ASIC) module, two profiles follow the tracks of with mark ASIC module, two digital signal processors (Digital Signal Processor, DSP) module at least one, wherein:

Described two nonuniformity correction SoC modules, described two multiple-stage filtering ASIC modules, described two DSP modules, described two profiles are followed the tracks of and are connected with described FPGA module respectively with mark ASIC module, described FPGA module provides the data channel between each module, and controls each module cooperative and complete in an orderly manner image Processing tasks;

Described FPGA module is also inputted for receiving two-way image simultaneously, and the image of two-way input is carried out to pre-service simultaneously;

Described two nonuniformity correction SoC modules, for receive independently described FPGA module through pretreated two-way image simultaneously, the pretreated two-way image of described process is carried out respectively to nonuniformity correction processing, and the image after nonuniformity correction is processed outputs to described FPGA module by described two-way;

Described two multiple-stage filtering ASIC modules, for receive the image of described two-way after nonuniformity correction is processed from described FPGA module independently simultaneously, and the image after described two-way nonuniformity correction is processed carries out respectively multiple-stage filtering processing, little target in image is strengthened, and the image after multiple-stage filtering is processed outputs to described FPGA module by described two-way;

Described two DSP modules; for receive the image described two-way multiple-stage filtering is processed from described FPGA module independently simultaneously; and the image after described two-way multiple-stage filtering is processed carries out respectively many-valued dividing processing; tentatively be partitioned into suspected target and background, and the image after many-valued dividing processing outputs to described FPGA module by described two-way;

Described two profiles are followed the tracks of and mark ASIC module, for the image from described FPGA module receives the many-valued dividing processing of described two-way independently simultaneously, and respectively the image that two-way is many-valued after cutting apart is carried out to profile and follow the tracks of with mark and process, generate objective contour coordinate information, and described two-way objective contour coordinate information is outputed to described FPGA module;

Described two DSP modules also for receiving described two-way objective contour coordinate information from described FPGA module independently, and according to described two-way objective contour coordinate information, target is carried out to feature extraction and feature identification, the coordinate information of output real goal respectively.

In this programme, owing to having adopted the image processing ASIC/SoC of multiple special use to complete corresponding image work for the treatment of, ASIC/SoC has treatment effeciency feature high, low in energy consumption, the ASIC/SoC designing for image processing algorithm application specially can, under very low power consumption, complete corresponding image processing algorithm quickly and efficiently.And traditional framework to the empty fixed target imagery automatic Target Recognition System many DSP of general employing or many DSP+FPGA, although DSP and FPGA have very high handling property, but all belong to general processor, not specially for image Processing tasks, there is the problem that power consumption is large, treatment effeciency is not high.Therefore, the method that the embodiment of the present invention proposes can improve the real-time of system in air target imaging automatic Target Recognition System, and reduces the power consumption of system.Compare and adopt general processor, improving on the basis for the treatment of effeciency, both guaranteed the real-time of system, reduced again the overall power of system, reduced to process chip such as DSP and FPGA the requirement to arithmetic capability simultaneously.Be conducive to the realization of production domesticization, reduce the dependence to external high-end chip.Meanwhile, the use of associating general processor DSP and FPGA has guaranteed the dirigibility of system, and the reconstruct of feasible system meets the needs of algorithms of different flow process.ASIC/SoC, DSP, these three kinds of process chip of FPGA are coordinated concurrent working, have guaranteed the high-level efficiency of performance and the high-level efficiency of volume power consumption of imaging automatic Target Recognition System.

Preferably, described automatic target recognizer also comprises straddle processing element, described straddle processing element by deserializer or and device converter be connected with described switching network, described switching network also for link the synchronous memories output interface of described processing unit and described deserializer or and device converter, described straddle processing element is for the transmission of data between control panel, described deserializer is for converting serial data to parallel data, and described parallel-to-serial converter is used for parallel data transformed into serial data.Described straddle processing element is transmitted high speed channel is provided for view data between pre-processed board and disposable plates.

Preferably, in described automatic target recognizer, described processing element comprises pre-processed board part and disposable plates part; Image is first sent to disposable plates and is further processed after pre-processed board is processed, wherein:

Described pre-processed board completes picture format conversion process, noise-removed filtering processing, nonuniformity correction processing, multiple-stage filtering processing;

Described disposable plates completes that image is many-valuedly cut apart, profile tracking and the function such as mark, feature extraction and feature identification;

Described disposable plates also provides the interface of communicating by letter with host computer with PC, and the interface function being connected with monitor;

Concrete, described pre-processed board comprises:

FPGA module, two nonuniformity correction SoC modules, two synchronous DRAM (Synchronous Dynamic Random Access Memory, SDRAM) module, two flash memory (Flash EEPROM Memory, Flash) module, two dual port RAMs (DPRAM) module, two multiple-stage filtering ASIC modules, two parallel serial conversion modules, wherein:

Described two nonuniformity correction SoC modules, described two dual port RAMs (DPRAM) module, described two multiple-stage filtering ASIC modules, described two parallel serial conversion modules are connected with described FPGA module respectively, described FPGA module provides the data channel between each module, and controls each module cooperative and complete in an orderly manner image Processing tasks;

Described FPGA module also, for receiving the input of two-way image, is carried out pre-service to the image of two-way input simultaneously;

Described two SDRAM modules, described two Flash modules are connected with described two nonuniformity correction SoC modules respectively, parameter and data when described two SDRAM modules are stored respectively described two nonuniformity correction SoC modules work, described two Flash modules are stored respectively the program of described two nonuniformity correction SoC modules, described two nonuniformity correction SoC modules are after electrification reset, respectively from described two Flash module fixed address fetch programs of correspondence and enter into normal operating conditions;

Described two nonuniformity correction SoC modules, for receive independently described FPGA module through pretreated two-way image simultaneously, the pretreated two-way image of described process is carried out respectively to nonuniformity correction processing, and respectively described two-way image after nonuniformity correction is processed is outputed to described FPGA module;

Described two DPRAM modules are connected with described two multiple-stage filtering ASIC, and described two DPRAM are for storing respectively the view data after described two-way multiple-stage filtering ASIC processes;

Described two multiple-stage filtering ASIC modules, for receive the image of described two-way after nonuniformity correction is processed from described FPGA module independently simultaneously, and the image after respectively described two-way nonuniformity correction being processed carries out multiple-stage filtering processing, little target in image is strengthened, and respectively described two-way image after multiple-stage filtering is processed being outputed to described two DPRAM modules, described FPGA module reads described two-way image after multiple-stage filtering is processed from described two DPRAM modules;

Described two parallel serial conversion modules, for receive the two-way image described multiple-stage filtering is processed and the two-way image after described multiple-stage filtering processing be sent to disposable plates from described FPGA module independently simultaneously;

Described disposable plates comprises:

FPGA module, two profiles are followed the tracks of and mark ASIC module, two DSP modules, two SDRAM modules, two Flash modules, two strings modular converter, video DAC module, level switch module, wherein:

Described two profiles are followed the tracks of with mark ASIC module, two DSP modules, two strings modular converter, video DAC module, level switch module and are connected with described FPGA module respectively, described FPGA module provides the data channel between each module, and controls each module cooperative and complete in an orderly manner image Processing tasks;

Described two strings modular converter, for receiving independently the image the described two-way multiple-stage filtering sending from pre-processed board is processed, and the image after respectively described two-way multiple-stage filtering being processed is sent to described FPGA module simultaneously;

Described two SDRAM modules are connected with described two DSP modules respectively with described two Flash modules, parameter and data when described two SDRAM modules are stored respectively described two DSP modules work, described two Flash modules are stored respectively the program of described two DSP modules, described two DSP modules after electrification reset, fixed address fetch program enter into normal operating conditions from described two Flash modules of correspondence respectively;

Described two DSP modules, for receive the image described two-way multiple-stage filtering is processed from described FPGA module independently simultaneously, and respectively the image after described two-way multiple-stage filtering processing is carried out to many-valued dividing processing, and the image after many-valued dividing processing outputs to described FPGA module by described two-way;

Described two DPRAM modules are followed the tracks of and are connected with mark ASIC with described two profiles, and described two DPRAM follow the tracks of the view data after processing with mark ASIC for storing respectively described two profiles;

Described two profiles are followed the tracks of and mark ASIC module, for the image from described FPGA module receives the many-valued dividing processing of described two-way independently simultaneously, and respectively the image of the many-valued dividing processing of two-way is carried out to profile and follow the tracks of and mark processing, generate two-way objective contour coordinate information, and respectively described two-way objective contour coordinate information is outputed to described FPGA module;

Described two DSP modules also for receiving described two-way objective contour coordinate information from described FPGA module independently, and according to described two-way objective contour coordinate information, target is carried out to feature extraction and feature identification, the coordinate information of output real goal respectively;

Described video DAC module, for from the complete view data of described FPGA module reception & disposal or any intermediate treatment view data, and by the described view data of handling or arbitrarily intermediate treatment view data output to monitor;

Described level switch module, for providing the serial communication between described target marker and PC.

In this programme, due to the restriction of system bulk, adopted the double-decker of pre-processed board and disposable plates, by pre-processed board, completed that picture format conversion process, filtering processing, nonuniformity correction are processed, multiple-stage filtering is processed; And by disposable plates complete that image is many-valuedly cut apart, profile tracking and the function such as mark, feature extraction and characteristic matching; Thereby realized the separation of algorithm process in the automatic identifying of target, promoted treatment effeciency.And the image processing ASIC/SoC by multiple special use completes corresponding image work for the treatment of, ASIC/SoC has treatment effeciency feature high, low in energy consumption, the ASIC/SoC designing for image processing algorithm application specially can, under very low power consumption, complete corresponding image processing algorithm quickly and efficiently.And traditional framework to the empty fixed target imagery automatic Target Recognition System many DSP of general employing or many DSP+FPGA, although DSP and FPGA have very high handling property, but all belong to general processor, not specially for image Processing tasks, there is the problem that power consumption is large, treatment effeciency is not high.Therefore, the method that the embodiment of the present invention proposes can improve the real-time of system in air target imaging automatic Target Recognition System, and reduces the power consumption of system.Compare and adopt general processor, improving on the basis for the treatment of effeciency, both guaranteed the real-time of system, reduced again the overall power of system, reduced to process chip such as DSP and FPGA the requirement to arithmetic capability simultaneously.Be conducive to the realization of production domesticization, reduce the dependence to external high-end chip.Meanwhile, the use of associating general processor DSP and FPGA has guaranteed the dirigibility of system, and the reconstruct of feasible system meets the needs of algorithms of different flow process.ASIC/SoC, DSP, these three kinds of process chip of FPGA are coordinated concurrent working, have guaranteed the high-level efficiency of performance and the high-level efficiency of volume power consumption of imaging automatic Target Recognition System.

Preferably, switching network in described automatic target recognizer specifically comprises: M input trigger, a N band enable the three-state gate array that the band of the triple gate controlled and M * N enables, the three-state gate array that the band of described M * N enables enables for a full connection described M input trigger and described N band the triple gate of controlling, a described M input trigger, for connecting M different synchronous memories output interface, is with the triple gate that enables to control for connecting N different input FIFO for described N.

In this programme, the switching network of building by trigger, triple gate and synchronous memories output interface and input FIFO, the control of the triple gate enabling by band, the data that both can realize single synchronous memories output interface send to single FIFO input interface, simultaneously, can realize the Simultaneous Transmission of Data of a synchronous memories output interface in a plurality of input FIFO, realize the broadcast transmission of data.Described switching network has reduced the FIFO storer that need to take a large amount of storage unit, has realized dynamically entirely interconnected between each processing element.In system performance objective recognizer task process, can be according to Target Recognition Algorithms need to change data stream connected mode, the data stream of reconstruct Target Recognition Algorithms.

Further preferred, nonuniformity correction SoC in described automatic target recognizer comprises input interface, output interface, universal asynchronous receiving-transmitting transmitter (Universal Asynchronous Receiver/Transmitter, UART) interface, Memory Controller and the special-purpose pin of controlling, described input interface is for receiving the input of view data from described FPGA; Described nonuniformity correction SoC carries out nonuniformity correction to the view data of described input, and by described output interface, described view data after nonuniformity correction is outputed to described FPGA; Described UART interface is used for and described FPGA module communication, transfer control order etc.; Described Memory Controller being for connecting and control external memory storage, reading out data or to data writing in described external memory storage from described external memory storage; The described special-purpose pin of controlling is for the control of described FPGA module to nonuniformity correction SoC.

Further preferred, multiple-stage filtering ASIC in described automatic target recognizer is by the complete image pixel of outside dual port RAM stores processor, between described multiple-stage filtering ASIC and described FPGA module, by data bus, control line, clock, pass a parameter and view data, between described multiple-stage filtering ASIC and dual port RAM, by data bus, address bus, control line, transmit the view data after multiple-stage filtering, described FPGA module reads the view data after the multiple-stage filtering in described dual port RAM by data bus, address bus, control line.

Accompanying drawing explanation

Fig. 1 is the one-piece construction schematic diagram of the parallel automatic target recognizer of moving platform air target Dual band IR isomery in the present invention;

Fig. 2 is the agent structure schematic diagram of the parallel automatic target recognizer of the constructed moving platform air target Dual band IR isomery of a preferred embodiment of the invention;

Fig. 3 is the parallel automatic target recognizer of the constructed moving platform air target Dual band IR isomery of a preferred embodiment of the invention and external interface connection diagram;

Fig. 4 is the nonuniformity correction SoC application block diagram in a preferred embodiment of the invention;

Fig. 5 is the flow chart of the nonuniformity correction SoC in a preferred embodiment of the invention;

Fig. 6 is the multiple-stage filtering ASIC application block diagram in a preferred embodiment of the invention;

Fig. 7 is the operational flowchart of the multiple-stage filtering ASIC in a preferred embodiment of the invention;

Fig. 8 is that the profile in a preferred embodiment of the invention is followed the tracks of and mark ASIC application block diagram;

Fig. 9 is that profile in a preferred embodiment of the invention is followed the tracks of the operational flowchart with mark ASIC;

Figure 10 is the detailed structure schematic diagram of the parallel automatic target recognizer of the constructed moving platform air target Dual band IR isomery of a preferred embodiment of the invention;

Figure 11 is the air target automatic identification algorithm typical flowchart in a preferred embodiment of the invention;

Figure 12 is the system input picture processing flow chart in a preferred embodiment of the invention;

Figure 13 is the interactive network schematic diagram in a preferred embodiment of the invention;

When Figure 14 is remote in a preferred embodiment of the invention, the interconnecting relation schematic diagram between each processing element of system;

When Figure 15 is the middle distance in a preferred embodiment of the invention, the interconnecting relation schematic diagram between each processing element of system;

Figure 16 be in a preferred embodiment of the invention closely time, the interconnecting relation schematic diagram between each processing element of system;

Figure 17 be in a preferred embodiment of the invention be remote time, little target image is processed streamline schematic diagram;

When Figure 18 is the middle distance in a preferred embodiment of the invention, Area Objects image is processed streamline schematic diagram;

Figure 19 be in a preferred embodiment of the invention closely time, general objective image is processed streamline schematic diagram.

Embodiment

In order to make object of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not intended to limit the present invention.In addition,, in each embodiment of described the present invention, involved technical characterictic just can not combine mutually as long as do not form each other conflict.

In order to solve the problems of the technologies described above, the invention provides a kind of automatic target recognizer, to realize under the requirement of moving platform software and hardware computational resource finite sum low-power consumption, aerial target is identified fast.

Fig. 1 is the one-piece construction schematic diagram in the parallel automatic target recognizer of the constructed moving platform air target isomery of a preferred embodiment of the invention.As shown in Figure 1, described automatic target recognizer consists of switching network and at least one processing element, between described processing element and described switching network, pass through input fifo interface, synchronous memories output interface and control line connect, described switching network is for different described input fifo interface and the described synchronous memories output interfaces of dynamic link, described processing element has been used for the required various algorithm function of automatic target identifying, described input FIFO is for the pending view data of buffer memory input, described synchronous memories output interface is for the to be exported view data of handling of buffer memory, described control line is for playing control action in image data transmission process, guarantee the accurate and effective of image data transmission.

ASIC/SoC is as special-purpose processor, and IO interface has very large difference with general processor as DSP compares with FPGA.Between the different ASIC/SoC that process for image, input and output difference is also very large.What some ASIC/SoC inputted is view data, and output is also view data; Some ASIC/SoC input be view data, output is feature (as coordinate etc.).The bit wide of view data is also not quite similar, and has plenty of 16bit, has plenty of 8bit, and what have even only has 3bit.The IO interface buffer memory of ASIC/SoC is also variant, and some ASIC/SoC does not need buffer memory; Some ASIC/SoC needs buffer memory; Some ASIC/SoC carries buffer memory; Some does not carry buffer memory.It is the difficult point of a design that these differences just cause the Networking Design between interconnected and different ASIC/SoC and the general processor between different ASIC/SoC.

In the embodiment of the present invention, adopted dynamic buffering structure to link different processing element.The use of input FIFO and synchronous memories output interface has solved the interconnect problem that the difference between different pieces of information width, different pieces of information speed, distinct interface causes effectively.The use of switching network guarantee between different disposal parts dynamically complete interconnected in, reduced resource consumption, improved the level of resources utilization of system.

Further, described automatic target recognizer can also comprise straddle processing element, described straddle processing element by deserializer or and device converter be connected with described switching network, described switching network also for link the synchronous memories output interface of described processing unit and described deserializer or and device converter, described straddle processing element is for the accurate transmission of data between control panel, described deserializer is for converting serial data to parallel data, and described parallel-to-serial converter is used for parallel data transformed into serial data.

Described straddle processing element is transmitted high speed channel is provided for view data between pre-processed board and disposable plates.

Fig. 2 is the agent structure schematic diagram of the parallel automatic target recognizer of the constructed moving platform air target Dual band IR isomery of a preferred embodiment of the invention, the parallel automatic target recognizer of a kind of moving platform air target Dual band IR isomery has been proposed, by adopting the image processing ASIC/SoC of multiple special use to complete corresponding image work for the treatment of, improving on the basis for the treatment of effeciency, both guaranteed the real-time of system, reduce again the overall power of system, reduced the requirement to arithmetic capability to process chip such as DSP and FPGA simultaneously.Specifically as shown in Figure 2, described target marker comprises: field programmable gate array (Field Programmable Gate Array, FPGA) module, two nonuniformity correction SOC (system on a chip) (System on Chip, SoC) module, two multiple-stage filtering special IC (Application Specific Integrated Circuit, ASIC) module, two profiles are followed the tracks of and mark ASIC module, two digital signal processor (Digital Signal Processor, DSP) module, wherein:

Described FPGA module also, for receiving the input of two-way image, is carried out pre-service simultaneously to the two-way image of input independently; Such as described pre-service, can be: image data format conversion, medium filtering, mean filter, gaussian filtering etc.;

Described two nonuniformity correction SoC modules, for receive independently described two-way FPGA module through pretreated image simultaneously, described two-way is carried out to nonuniformity correction processing through pretreated image, and the image after nonuniformity correction is processed outputs to described FPGA module by described two-way respectively; By nonuniformity correction, can proofread and correct the gradation of image causing because of infrared imaging device imaging characteristic distorts;

Described two multiple-stage filtering ASIC modules, for receive the image of described two-way after nonuniformity correction is processed from described FPGA module independently simultaneously, and the image after respectively described two-way nonuniformity correction being processed carries out multiple-stage filtering processing, little target in image is strengthened, and by described two-way, the image after multiple-stage filtering is processed outputs to described FPGA module respectively;

Described two DSP modules, for receive the image described two-way multiple-stage filtering is processed from described FPGA module independently simultaneously, and the image after described two-way multiple-stage filtering is processed carries out many-valued dividing processing, tentatively be partitioned into suspected target and background, and the image after many-valued dividing processing outputs to described FPGA module by described two-way respectively;

Described two profiles are followed the tracks of and mark ASIC module, for the image from described FPGA module receives the many-valued dividing processing of described two-way independently simultaneously, and respectively the image that two-way is many-valued after cutting apart is carried out to profile and follow the tracks of with mark and process, generate two-way objective contour coordinate information, and respectively described two-way objective contour coordinate information is outputed to described FPGA module;

In the embodiment of the present invention, adopted the image processing ASIC/SoC of multiple special use to complete corresponding image work for the treatment of, ASIC/SoC has treatment effeciency feature high, low in energy consumption, the ASIC/SoC designing for image processing algorithm application specially can, under very low power consumption, complete corresponding image processing algorithm quickly and efficiently.And the general framework that adopts many DSP or many DSP+FPGA of traditional air target imaging automatic Target Recognition System, although DSP and FPGA have very high handling property, but all belong to general processor, not specially for image Processing tasks, have the problem that power consumption is large, treatment effeciency is not high.

Therefore, the method that the embodiment of the present invention proposes can improve the real-time of system in air target imaging automatic Target Recognition System, and reduces the power consumption of system.Compare and adopt general processor, improving on the basis for the treatment of effeciency, both guaranteed the real-time of system, reduced again the overall power of system, reduced to process chip such as DSP and FPGA the requirement to arithmetic capability simultaneously.Be conducive to the realization of production domesticization, reduce the dependence to external high-end chip.Meanwhile, the use of associating general processor DSP and FPGA has guaranteed the dirigibility of system, and the reconstruct of feasible system meets the needs of algorithms of different flow process.ASIC/SoC, DSP, these three kinds of process chip of FPGA are coordinated concurrent working, have guaranteed the high-level efficiency of performance and the high-level efficiency of volume power consumption of imaging automatic Target Recognition System.

Fig. 3 is the parallel automatic target recognizer of the constructed moving platform air target Dual band IR isomery of a preferred embodiment of the invention and external interface connection diagram; As shown in Figure 3, described target marker is connected with image input interface, PC serial ports, analog video output interface and host computer serial ports, concrete, described two-way image input interface is for the input of two-way view data, described target marker is processed the view data of described two-way input, completes target identifying; Described PC serial ports, host computer communication serial port are for debugging and parameter setting system; Described analog video output interface, outputs to monitor by the result of described target marker identification, the intermediate result of processing by monitor observable image result or image.

Fig. 4 is the nonuniformity correction SoC application block diagram in the parallel automatic target recognizer of the constructed moving platform air target Dual band IR isomery of a preferred embodiment of the invention.As shown in Figure 4, described nonuniformity correction SoC mainly comprises input interface, output interface, universal asynchronous receiving-transmitting transmitter (Universal Asynchronous Receiver/Transmitter, UART) interface, Memory Controller and the special-purpose pin of controlling.Described input interface is for the input of view data; Described nonuniformity correction SoC carries out nonuniformity correction to the view data of described input, and by the described view data after nonuniformity correction of described output interface output; Described UART interface is used for communicating by letter with ppu, transfer control order etc.; Described Memory Controller being for connecting and control external memory storage, reading out data or to data writing in described external memory storage from described external memory storage; The described special-purpose pin of controlling is for the control of ppu to nonuniformity correction SoC.Concrete, in the embodiment of the present invention, described ppu can be FPGA module.

Fig. 5 is the flow chart of the nonuniformity correction SoC in the parallel automatic target recognizer of the constructed moving platform air target Dual band IR isomery of a preferred embodiment of the invention.As shown in Figure 5, the method for operating of described nonuniformity correction comprises:

After described nonuniformity correction SoC electrification reset, enter init state, after initialization completes, described nonuniformity correction SoC is written into configuration parameter and enters correction work state.Described nonuniformity correction SoC receives image and according to correction parameter, image is carried out to nonuniformity correction, and by the image output after nonuniformity correction.

After described nonuniformity correction SoC initialization completes, if ppu is write bypass enable order by serial ports to the internal register of described nonuniformity correction SoC, described nonuniformity correction SoC enters into bypass functionality state, and output original image, to correct image.

Same, in the process of image input, correction, correcting image output, if described nonuniformity correction SoC receives, serial ports interrupts or look-at-me appears in dedicated pin, described nonuniformity correction SoC will be transferred to interrupt handling routine, if serial ports is write bypass enable order to register, described nonuniformity correction SoC will proceed to bypass functionality state, and output original image, to correct image.

In the embodiment of the present invention, by adopting nonuniformity correction SoC to carry out the nonuniformity correction of image, and adopt traditional FPGA to add the nonuniformity correction that DSP carries out image to compare, improved system treatment effeciency, reduced entire system power consumption.

Fig. 6 is the multiple-stage filtering ASIC application block diagram in the parallel automatic target recognizer of the constructed moving platform air target Dual band IR isomery of a preferred embodiment of the invention.As shown in Figure 6, described multiple-stage filtering ASIC needs the complete image pixel of outside dual port RAM stores processor.Between described multiple-stage filtering ASIC and ppu, by data bus, control line, clock, pass a parameter and view data.Between described multiple-stage filtering ASIC and dual port RAM, by data bus, address bus, control line, transmit the view data after multiple-stage filtering.Ppu reads the view data after the multiple-stage filtering in described dual port RAM by data bus, address bus, control line.Concrete, in the embodiment of the present invention, described ppu can be FPGA module.

Fig. 7 is the operational flowchart of the multiple-stage filtering ASIC in the parallel automatic target recognizer of the constructed moving platform air target Dual band IR isomery of a preferred embodiment of the invention.As shown in Figure 7, described multiple-stage filtering ASIC operating process comprises: after described multiple-stage filtering ASIC power-up initializing, wait for that ppu writes program parameters, ppu writes described program parameters the length of input picture and width is arranged, and the address field of the external SRAM of configuration output data storage.After having configured, described multiple-stage filtering ASIC enters multiple-stage filtering duty.Described multiple-stage filtering ASIC receives view data, and image is carried out to multiple-stage filtering processing, and successively the image pixel after multiple-stage filtering is sent to external SRAM according to the address of setting.

In the embodiment of the present invention, by adopting multiple-stage filtering ASIC to carry out the processing of image multiple-stage filtering, the FPGA traditional with employing or DSP carry out the processing of image multiple-stage filtering and compare, and have improved system treatment effeciency, have reduced entire system power consumption.

Fig. 8 is that the profile in the parallel automatic target recognizer of the constructed moving platform air target Dual band IR isomery of a preferred embodiment of the invention is followed the tracks of and mark ASIC application block diagram.As shown in Figure 8, between described profile tracking and mark ASIC and ppu, mainly by data bus, address bus, control line, clock etc., transmit data, control command etc.Concrete, in the embodiment of the present invention, described ppu can be FPGA module.

Fig. 9 is that the profile in the parallel automatic target recognizer of the constructed moving platform air target Dual band IR isomery of a preferred embodiment of the invention is followed the tracks of the operational flowchart with mark ASIC.As shown in Figure 9, described profile is followed the tracks of with the operating process of mark ASIC and is comprised: after described profile tracking and mark ASIC electrification reset, wait for that ppu writes the parameter of image to be marked and controls parameter.Ppu is by after the parameter of image to be marked and control parameter read-in, and described profile is followed the tracks of with mark ASIC and entered profile tracking and markers work state.Described profile is followed the tracks of and is read the image to be marked row labels of going forward side by side with mark ASIC and process, and by the coordinate information output of mark.

In the process of mark, once there is mistake, described profile is followed the tracks of with mark ASIC will abandon this two field picture, wait for lower two field picture input.

In the embodiment of the present invention, by adopting profile tracking, with mark ASIC, the suspected target in image is carried out to profile tracking, process with mark, the FPGA traditional with employing or DSP carry out profile tracking and compare with mark, have improved system treatment effeciency, have reduced entire system power consumption.

Figure 10 is the detailed structure schematic diagram of the parallel automatic target recognizer of the constructed moving platform air target Dual band IR isomery of a preferred embodiment of the invention.As shown in figure 10, because volume in moving platform automatic target identification application has strict restriction, described target marker is comprised of two parts, comprises pre-processed board part and disposable plates part; Image is first sent to disposable plates and is further processed after pre-processed board is processed, wherein:

Described pre-processed board mainly completes the functions such as picture format conversion process, noise-removed filtering processing, nonuniformity correction processing, multiple-stage filtering processing.

Described disposable plates mainly completes that image is many-valuedly cut apart, profile tracking and the function such as mark, feature extraction and feature identification.

Described disposable plates also provides the interface of communicating by letter with host computer with PC, and the interface function being connected with monitor.

(1) concrete, as shown in figure 10, described pre-processed board comprises:

Described two parallel serial conversion modules, for receive the two-way image described multiple-stage filtering is processed and the two-way image after described multiple-stage filtering processing be sent to disposable plates from described FPGA module independently simultaneously.

(2) concrete, as shown in figure 10, described disposable plates comprises: FPGA module, two profiles are followed the tracks of and mark ASIC module, two DSP modules, two SDRAM modules, two Flash modules, two strings modular converter, video DAC module, level switch module, wherein:

Below the described target marker course of work is described: two-way infrared image is input to respectively in the FPGA of pre-processed board, FPGA changes the image data format of two-way input respectively, then sends two outside nonuniformity correction SoC to and carries out independently nonuniformity correction simultaneously.Nonuniformity correction SoC can analog imaging device sequential, directly the image of handling is sent respectively to two multiple-stage filtering ASIC by FPGA again and independently image is carried out to multiple-stage filtering processing simultaneously.Two-way image after multiple-stage filtering ASIC handles is sent to disposable plates by two parallel-serial conversion chips of FPGA outside respectively.Disposable plates receives after two-way view data through two strings conversion chip simultaneously independently, and two-way view data is sent in FPGA respectively.Then FPGA carries out two-way view data buffer memory and is sent to respectively in two DSP, and according to different application, DSP carries out different algorithms image is carried out to many-valued dividing processing.Image after the many-valued dividing processing of two-way is sent to respectively two profiles tracking again and carries out independently profile tracking and mark processing simultaneously with mark ASIC, and the two-way image after mark is complete is sent to respectively through FPGA the processing that corresponding DSP carries out succeeding target identification again.Image after processing procedure neutralisation treatment is complete can be sent to monitor through image-display units and show.

Nonuniformity correction SoC, multiple-stage filtering ASIC, profile follow the tracks of with the use of tri-kinds of special image processors of mark ASIC improved system treatment effeciency, reduced the power consumption of system; The use of DSP and two kinds of general processors of FPGA, has guaranteed the dirigibility of system and the reconfigurability of system.ASIC/SoC, DSP, these three kinds of process chip of FPGA are coordinated concurrent working, have guaranteed the high-level efficiency of performance and the high-level efficiency of volume power consumption of imaging automatic Target Recognition System.

Figure 11 is the air target automatic identification algorithm typical flowchart of the parallel automatic target recognizer of the constructed moving platform air target Dual band IR isomery of a preferred embodiment of the invention.As shown in figure 11, the general feature that adopts of air target imaging automatic target identification is known method for distinguishing, different from the distance of target according to aircraft, is divided into distance small target, middle distance Area Objects and general objective closely.During different distance, the algorithm of use is not quite similar.

Due to the imaging characteristic of infrared imaging device, need carry out nonuniformity correction processing to infrared image.

When remote, target is little target, for the treatment scheme of the infrared image that comprises little target, comprises: nonuniformity correction, multiple-stage filtering, cut apart, feature extraction, feature identification.

When middle distance, target is Area Objects.The treatment scheme of infrared image comprises: nonuniformity correction, cut apart, the identification of feature extraction, feature.

Closely time, target is general objective, and target critical point is identified.The treatment scheme of infrared image comprises: nonuniformity correction, feature extraction, feature identification.

Wherein, in concrete application, the method for described feature extraction comprises: Threshold segmentation, silhouette markup, rim circumference, edge area, Corner Detection, the centre of form etc.

Figure 12 is the input picture processing flow chart of the parallel automatic target recognizer of the constructed moving platform air target Dual band IR isomery of a preferred embodiment of the invention.As shown in figure 12, to each two field picture, FPGA first carries out pre-service, then by nonuniformity correction SoC, proofread and correct processing, different according to the far and near degree of target, selection is carried out multiple-stage filtering processing or is not carried out multiple-stage filtering processing, then the image after processing is carried out to parallel-serial conversion and string conversion and be sent to that DSP is cut apart or feature extraction, then the view data of handling being sent into profile follows the tracks of and carries out profile with mark ASIC and follow the tracks of with mark and process, and then by DSP, carry out feature identification scheduling algorithm and process, provide target information.Last image can be sent to monitor and show by the display unit of FPGA.

Figure 13 is the interactive network schematic diagram in the parallel automatic target recognizer of the constructed moving platform air target Dual band IR isomery of a preferred embodiment of the invention.As shown in figure 13, the three-state gate array that the interactive network in described target marker is enabled by the band of N X N, a N input trigger, a N triple gate that band enables to control form.The three-state gate array that the band of described N X N enables enables for a full connection described N input trigger and described N band the triple gate of controlling, a described N input trigger, for connecting N different synchronous memories output interface, is with the triple gate that enables to control for connecting N different input FIFO for described N.

The control of the triple gate enabling by described band, the data that both can realize single synchronous memories output interface send to single FIFO input interface, meanwhile, can realize the Simultaneous Transmission of Data of a synchronous memories output interface in a plurality of input FIFO, realize the broadcast transmission of data.Described switching network has reduced the FIFO storer that need to take a large amount of storage unit, has realized dynamically entirely interconnected between each processing element.In system performance objective recognizer task process, can be according to Target Recognition Algorithms need to change data stream connected mode, the data stream of reconstruct Target Recognition Algorithms.

Figure 14 is that the constructed moving platform air target Dual band IR isomery of a preferred embodiment of the invention walks abreast automatic target recognizer when remote, the interconnecting relation schematic diagram between each processing element of system.As shown in figure 14, in figure, solid line represents the annexation of Physical layer; The data path annexation of dotted line presentation logic layer.Nonuniformity correction SoC, multiple-stage filtering ASIC, DPRAM, DSP, profile is followed the tracks of and mark ASIC, video DAC is connected by different interfaces respectively from FPGA in Physical layer, by the buffer structure of described FPAG inside, in logical layer each processing unit, set up active data circulation flow path, specifically as shown in the figure, between described nonuniformity correction SoC and described multiple-stage filtering ASIC, there is a data path, for transmitting the view data after nonuniformity correction is processed, described multiple-stage filtering ASIC arrives DPRAM by the image data transmission after multiple-stage filtering is processed, between described DPRAM and described DSP, there is a data path, for transmitting the view data after multiple-stage filtering is processed, between described DSP and profile tracking and mark ASIC, there is a data path, for transmitting the view data after many-valued dividing processing, data path between described profile tracking and mark ASIC and described DSP, also for transmitting through profile, follow the tracks of the image coordinate data after processing with mark, between described DSP and described video DAC, there is a data path, for transmitting the view data that need to show.

Figure 15 is that the constructed moving platform air target Dual band IR isomery of a preferred embodiment of the invention walks abreast automatic target recognizer when middle distance, the interconnecting relation schematic diagram between each processing element of system.As shown in figure 15, in figure, solid line represents the annexation of Physical layer; The data path annexation of dotted line presentation logic layer.Nonuniformity correction SoC, multiple-stage filtering ASIC, DPRAM, DSP, profile is followed the tracks of and mark ASIC, video DAC is connected by different interfaces respectively from FPGA in Physical layer, by the buffer structure of described FPAG inside, in logical layer each processing unit, set up active data circulation flow path, specifically as shown in the figure, between described nonuniformity correction SoC and described DSP, there is a data path, for transmitting the view data after nonuniformity correction is processed, between described DSP and profile tracking and mark ASIC, there is a data path, for transmitting the view data after many-valued dividing processing, data path between described profile tracking and mark ASIC and described DSP, also for transmitting through profile, follow the tracks of the image coordinate data after processing with mark, between described DSP and described video DAC, there is a data path, for transmitting the view data that need to show.

Figure 16 is that the constructed moving platform air target Dual band IR isomery of a preferred embodiment of the invention walks abreast automatic target recognizer closely time, the interconnecting relation schematic diagram between each processing element of system.As shown in figure 16, in figure, solid line represents the annexation of Physical layer; The data path annexation of dotted line presentation logic layer.Nonuniformity correction SoC, multiple-stage filtering ASIC, DPRAM, DSP, profile is followed the tracks of and mark ASIC, video DAC is connected by different interfaces respectively from FPGA in Physical layer, by the buffer structure of described FPAG inside, in logical layer each processing unit, set up active data circulation flow path, specifically as shown in the figure, between described nonuniformity correction SoC and described DSP, there is a data path, for transmitting the view data after nonuniformity correction is processed, between described DSP and described video DAC, there is a data path, for transmitting the view data that need to show.

Different phase in target identification, recognizer is different, processing to image is also not quite similar, the data stream of recognizer inside is not identical yet, the use of dynamic buffering structure provides the different phase in target identification, the transmission channel of the data stream of recognizer inside, and reduced the consumption of resource.

Figure 17 is that the constructed moving platform air target Dual band IR isomery of a preferred embodiment of the invention walks abreast automatic target recognizer when remote, the streamline schematic diagram that system is processed little target image.As shown in figure 17, view data is successively in an orderly manner through processing unit processes such as FPGA, nonuniformity correction SoC, multiple-stage filtering ASIC, DSP, profile tracking and mark ASIC, DSP, each processing unit collaborative work, each constantly has multiple image to be processed in an orderly manner on streamline.

Figure 18 is that the constructed moving platform air target Dual band IR isomery of a preferred embodiment of the invention walks abreast automatic target recognizer when middle distance, the streamline schematic diagram that system opposite target image is processed.As shown in figure 18, view data is successively in an orderly manner through each processing unit processes such as FPGA, nonuniformity correction SoC, DSP, profile tracking and mark ASIC, DSP, each processing unit collaborative work, each constantly has multiple image to be processed in an orderly manner on streamline.

Figure 19 is that the constructed moving platform air target Dual band IR isomery of a preferred embodiment of the invention walks abreast automatic target recognizer closely time, the streamline schematic diagram that system is processed general objective key point image.As shown in figure 19, view data is passed through each processing unit processes such as FPGA, nonuniformity correction SoC, DSP successively in an orderly manner, each processing unit collaborative work, and each constantly has multiple image to be processed in an orderly manner on streamline.

Those skilled in the art will readily understand; the foregoing is only preferred embodiment of the present invention; not in order to limit the present invention, all any modifications of doing within the spirit and principles in the present invention, be equal to and replace and improvement etc., within all should being included in protection scope of the present invention.

Claims

1. the parallel automatic target recognizer of moving platform air target Dual band IR isomery, is characterized in that, described target marker comprises:

Switching network and at least one processing element, between described processing element and described switching network, pass through input fifo interface, synchronous memories output interface and control line connect, described switching network is for different described input fifo interface and the described synchronous memories output interfaces of dynamic link, described processing element has been used for the required various algorithm function of automatic target identifying, described input FIFO is for the pending view data of buffer memory input, described synchronous memories output interface is for the to be exported view data of handling of buffer memory, described control line is used in the control data transmission of image data transmission process.

2. automatic target recognizer as claimed in claim 1, it is characterized in that, described target marker comprises field programmable gate array (Field Programmable Gate Array, FPGA) module, two nonuniformity correction SOC (system on a chip) (System on Chip, SoC) module, two multiple-stage filtering special IC (Application Specific Integrated Circuit, ASIC) module, two profiles are followed the tracks of and mark ASIC module, two digital signal processors (Digital Signal Processor, DSP) module, wherein:

3. automatic target recognizer as claimed in claim 1, it is characterized in that, also comprise: straddle processing element, described straddle processing element by deserializer or and device converter be connected with described switching network, described switching network also for link the synchronous memories output interface of described processing unit and described deserializer or and device converter, described straddle processing element is for the transmission of data between control panel, described deserializer is for converting serial data to parallel data, and described parallel-to-serial converter is used for parallel data transformed into serial data.

4. automatic target recognizer as claimed in claim 3, is characterized in that, described processing element comprises pre-processed board part and disposable plates part; Image is first sent to disposable plates and is further processed after pre-processed board is processed, wherein:

Concrete, described pre-processed board comprises:

Described disposable plates comprises:

5. the automatic target recognizer as described in claim 1 to 4 any one, it is characterized in that, described switching network specifically comprises: M input trigger, a N band enable the three-state gate array that the band of the triple gate controlled and M * N enables, the three-state gate array that the band of described M * N enables enables for a full connection described M input trigger and described N band the triple gate of controlling, a described M input trigger, for connecting M different synchronous memories output interface, is with the triple gate that enables to control for connecting N different input FIFO for described N.

6. the automatic target recognizer as described in claim 2 or 4, it is characterized in that, described nonuniformity correction SoC comprises input interface, output interface, universal asynchronous receiving-transmitting transmitter (Universal Asynchronous Receiver/Transmitter, UART) interface, Memory Controller and the special-purpose pin of controlling, described input interface is for receiving the input of view data from described FPGA; Described nonuniformity correction SoC carries out nonuniformity correction to the view data of described input, and by described output interface, described view data after nonuniformity correction is outputed to described FPGA; Described UART interface is used for and FPGA module communication described in ppu, transfer control order etc.; Described Memory Controller being for connecting and control external memory storage, reading out data or to data writing in described external memory storage from described external memory storage; The described special-purpose pin of controlling is for the control of FPGA module to nonuniformity correction SoC described in ppu.

7. the automatic target recognizer as described in claim 2 or 4, it is characterized in that, described rotation ASIC need to be by the complete image pixel of outside dual port RAM stores processor, described in described rotation ASIC and ppu, between FPGA module, pass through data bus, control line, clock passes a parameter and view data, between described rotation ASIC and described dual port RAM, pass through data bus, address bus, control line transmits the view data after rotation is processed, described ppu FPGA module is passed through data bus, address bus, control line reads the view data after the rotation processing in described dual port RAM.

8. the automatic target recognizer as described in claim 2 or 4, it is characterized in that, described multiple-stage filtering ASIC need to be by the complete image pixel of outside dual port RAM stores processor, described in described multiple-stage filtering ASIC and ppu, between FPGA module, pass through data bus, control line, clock passes a parameter and view data, between described multiple-stage filtering ASIC and dual port RAM, pass through data bus, address bus, control line transmits the view data after multiple-stage filtering, described in ppu, FPGA module is passed through data bus, address bus, control line reads the view data after the multiple-stage filtering in described dual port RAM.