CN103647573B - Multichannel ADC synchronized sampling intermediate-frequency receiver - Google Patents
Multichannel ADC synchronized sampling intermediate-frequency receiver Download PDFInfo
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- CN103647573B CN103647573B CN201310594342.6A CN201310594342A CN103647573B CN 103647573 B CN103647573 B CN 103647573B CN 201310594342 A CN201310594342 A CN 201310594342A CN 103647573 B CN103647573 B CN 103647573B
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Abstract
The invention discloses a kind of multichannel ADC synchronized sampling intermediate-frequency receiver, it comprises multiple fpga chip and dsp chip, and first multichannel ADC module and the second multichannel ADC module, the signal of the first multichannel ADC module exports and is connected with the signal input of the first fpga chip, two-way multi-channel data cube computation is had between first fpga chip and the first dsp chip, the signal of the second multichannel ADC module exports and is connected with the signal input of the second fpga chip, two-way multi-channel data cube computation is had between second fpga chip and the second dsp chip, first multichannel ADC module and the second multichannel ADC module also with clock distribution model calling.The present invention has multiple AD passage, and sampling clock is mutually independent simultaneously, and can carry out synchronous acquisition when shared external clock and internal clock, cost is low, and cost performance is high, and can carry out the Big Dipper and gps satellite location, intelligence degree is high.
Description
Technical field
The present invention relates to a kind of digital if receiver, particularly multichannel ADC synchronized sampling intermediate-frequency receiver.
Background technology
Existing Intermediate Frequency Digital Receiver is primarily of single analog to digital converter (ADC) and digital down converter composition, wherein analog-to-digital conversion module mainly completes the sampling of analog if signal, and conversion obtains digitized intermediate-freuqncy signal, interested signal is converted to base band by digital down converter, do sampling rate conversion and filtering process simultaneously, obtain orthogonal I, follow-up digital signal processor is sent to carry out base band signal process after Q signal, inside whole intermediate-frequency receiver, digital down converter is the core of whole Intermediate Frequency Digital Receiver, but under normal circumstances, existing Intermediate Frequency Digital Receiver only can realize single pass signal sampling, inefficiency, working method is single.When working on frequent vehicle-carried mobile equipment, often because can not satellite fix and occur various trouble simultaneously.
Number of patent application: a kind of Universal type digital intermediate frequency receiver disclosed in 201210507125.4, it comprises multichannel ADC module, multichannel bridge module, multi-channel digital down-conversion ASIC module, multichannel FPGA processing module, multichannel DSP module, over-borrowing mouth output module and DSP top control module, the data of described multichannel ADC module export and are connected with the data input of multichannel bridge module, the data of multichannel bridge module export and are connected with the data input of multi-channel digital down-conversion ASIC module, the data input of multi-channel digital down-conversion ASIC module connects, the data of multi-channel digital down-conversion ASIC module export and are connected with the data input of multichannel FPGA processing module, two-way multi-channel data cube computation is had between multichannel FPGA processing module and multichannel DSP processing module, the data of multichannel DSP processing module export the output being carried out final result by multiplex roles output module, this invention versatility is good, treatment effeciency is high, cost is low.But be not provided with inside and outside clock distribution module, the synchronous or asynchronous-sampling of multichannel ADC can not be carried out, and any switching laws of interior external clock, be not provided with satellite positioning functions simultaneously, location defect is existed to the intermediate-frequency receiver used on the mobile apparatus.The internal design structures of this invention is, multiple AD passage respectively with multiple ADC model calling, multiple ADC module respectively with multiple Digital Down Convert ASIC model calling, multiple Digital Down Convert ASIC module is connected with FPGA processing module again, this project organization adopts the structure of point circuit, every bar circuit all needs an AD passage, ADC module, a Digital Down Convert ASIC module and a FPGA processing module, this project organization, sampling channel is more, design more complicated, cost is also higher, and synchronous signal conversion process ability is also lower.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, one is provided to have multiple AD passage, the sampling clock of multichannel ADC module is mutually independent, the Big Dipper and gps satellite location can be carried out, any switching laws between external clock and internal clock can be carried out simultaneously, can synchronous acquisition be realized, cost is low, cost performance is high, passage configuration and compound mode applying flexible, intelligence degree much higher passage ADC synchronized sampling intermediate-frequency receiver.
The object of the invention is to be achieved through the following technical solutions: multichannel ADC synchronized sampling intermediate-frequency receiver, it comprises the first fpga chip, second fpga chip, 3rd fpga chip, first dsp chip, second dsp chip, first multichannel ADC module, second multichannel ADC module and clock distribution module, the signal of the first multichannel ADC module exports and is connected with the signal input of the first fpga chip, be connected by two-way multi-channel data line between first fpga chip with the first dsp chip, the signal of the second multichannel ADC module exports and is connected with the signal input of the second fpga chip, two-way multi-channel data cube computation is had between second fpga chip and the second dsp chip, first fpga chip is connected with the second fpga chip by bus, first dsp chip is connected with the second dsp chip by bus, first fpga chip and the second fpga chip are connected with the Big Dipper/GPS interface respectively, 3rd fpga chip is connected with the Big Dipper/GPS interface by spi bus, first fpga chip is connected with the 3rd fpga chip by bus, first dsp chip is connected with DDR2 internal memory and nonvolatile flash memory respectively by bus, second dsp chip is connected with DDR2 internal memory and nonvolatile flash memory respectively by bus, first fpga chip is connected with nonvolatile flash memory and four-way digital down converter respectively by bus, second fpga chip is connected with nonvolatile flash memory and four-way digital down converter respectively by bus, the output of clock distribution module respectively with the first multichannel ADC module and the second multichannel ADC model calling,
Multichannel ADC module: the signal of multiple AD passage is sampled, and carries out analog-to-digital conversion;
Fpga chip: coordinate four-way Digital Down Convert to complete baseband-converted, and extract I/Q component, by I, Q component feeding dsp chip through pulse-width matched filter;
The Big Dipper/GPS interface: the function with the Big Dipper and the two navigation of GPS;
Clock distribution module: for the first multichannel ADC module and the second multichannel ADC module provide internal clock or external clock respectively, or carry out clock switching.
The signal input part of described clock distribution module is connected with the signal output part of temperature compensating crystal oscillator and the signal end of external clock respectively.
The first described multichannel ADC module and passage AD4, passage AD5, passage AD6 are one group, second multichannel ADC module and passage AD1, passage AD2, passage AD3 are one group, the sampling clock of two groups of AD is mutually independent, often group all can realize any switching laws between internal clock and external clock under the cooperation of clock distribution module, when two groups of AD use homology clock, require that each road AD is synchronous.
The 3rd described fpga chip is also connected with CPCIe*4 interface by GPIO bus, and CPCIe*4 Interface realization intermediate frequency acquisition process plate is with the data interaction of host computer.
Receiver inside is also provided with independently-powered interface and power management module, with the normal use power supply to each function element.
The present invention has following advantage:
1, have multiple AD passage, the sampling clock of multichannel ADC module is mutually independent, can carry out synchronous acquisition when shared external clock and internal clock simultaneously;
2, be provided with internal clock and external clock, any switching laws between internal clock and external clock can be carried out;
3, be provided with CPCIe*4 interface, the data interaction of intermediate frequency acquisition process plate with host computer can be realized;
4, be provided with the Big Dipper/GPS interface, there is the function of the Big Dipper and the two navigation of GPS;
5, ASIC, DSP and FPGA tri-kinds of technology combined, disposal ability is stronger, has higher treatment effeciency;
6, cost is low, and cost performance is high, passage configuration and compound mode applying flexible, and intelligence degree is high, is beneficial to industrialization and produces and use.
Accompanying drawing explanation
Fig. 1 is structural representation of the present invention.
Embodiment
Below in conjunction with accompanying drawing, technical scheme of the present invention is described in further detail, but protection scope of the present invention is not limited to the following stated.
As shown in Figure 1, multichannel ADC synchronized sampling intermediate-frequency receiver, it comprises the first fpga chip, second fpga chip, 3rd fpga chip, first dsp chip, second dsp chip, first multichannel ADC module, second multichannel ADC module and clock distribution module, the signal of the first multichannel ADC module exports and is connected with the signal input of the first fpga chip, be connected by two-way multi-channel data line between first fpga chip with the first dsp chip, the signal of the second multichannel ADC module exports and is connected with the signal input of the second fpga chip, two-way multi-channel data cube computation is had between second fpga chip and the second dsp chip, first fpga chip is connected with the second fpga chip by bus, first dsp chip is connected with the second dsp chip by bus, first fpga chip and the second fpga chip are connected with the Big Dipper/GPS interface respectively, 3rd fpga chip is connected with the Big Dipper/GPS interface by spi bus, first fpga chip is connected with the 3rd fpga chip by bus, first dsp chip is connected with DDR2 internal memory and nonvolatile flash memory respectively by bus, second dsp chip is connected with DDR2 internal memory and nonvolatile flash memory respectively by bus, first fpga chip is connected with nonvolatile flash memory and four-way digital down converter respectively by bus, second fpga chip is connected with nonvolatile flash memory and four-way digital down converter respectively by bus, the output of clock distribution module respectively with the first multichannel ADC module and the second multichannel ADC model calling,
Multichannel ADC module: the signal of multiple AD passage is sampled, and carries out analog-to-digital conversion;
Fpga chip: coordinate four-way Digital Down Convert to complete baseband-converted, and extract I/Q component, by I, Q component feeding dsp chip through pulse-width matched filter;
The Big Dipper/GPS interface: the function with the Big Dipper and the two navigation of GPS;
Clock distribution module: for the first multichannel ADC module and the second multichannel ADC module provide internal clock or external clock respectively, or carry out clock switching.
The signal input part of described clock distribution module is connected with the signal output part of temperature compensating crystal oscillator and the signal end of external clock respectively.
The first described multichannel ADC module and passage AD4, passage AD5, passage AD6 are one group, second multichannel ADC module and passage AD1, passage AD2, passage AD3 are one group, the sampling clock of two groups of AD is mutually independent, often group all can realize any switching laws between internal clock and external clock under the cooperation of clock distribution module, when two groups of AD use homology clock, require that each road AD is synchronous.
The 3rd described fpga chip is also connected with CPCIe*4 interface by GPIO bus, and CPCIe*4 Interface realization intermediate frequency acquisition process plate is with the data interaction of host computer.
Receiver inside is also provided with independently-powered interface and power management module, with the normal use power supply to each function element.
Described PCIe bridging chip is LX50T, is connected to CPCIe*4 interface, realizes the data interaction of intermediate frequency acquisition process plate with host computer.LX50T chip has 15 GPIO to link on CPCIe connector Xj4 after driving, and send order for FPGA external device, the signal level after driving reaches+5V or+12V.
Described dsp chip is the DSP:TMS320C6455 of 1GHz dominant frequency, connects Rapid IO*4 (1.25Gbps) interface and a road McBSP interface between the first described dsp chip and the second dsp chip.
Claims (3)
1. multichannel ADC synchronized sampling intermediate-frequency receiver, it is characterized in that: it comprises the first fpga chip, second fpga chip, 3rd fpga chip, first dsp chip, second dsp chip, first multichannel ADC module, second multichannel ADC module and clock distribution module, the signal of the first multichannel ADC module exports and is connected with the signal input of the first fpga chip, be connected by two-way multi-channel data line between first fpga chip with the first dsp chip, the signal of the second multichannel ADC module exports and is connected with the signal input of the second fpga chip, two-way multi-channel data cube computation is had between second fpga chip and the second dsp chip, first fpga chip is connected with the second fpga chip by bus, first dsp chip is connected with the second dsp chip by bus, first fpga chip and the second fpga chip are connected with the Big Dipper/GPS interface respectively, 3rd fpga chip is connected with the Big Dipper/GPS interface by spi bus, first fpga chip is connected with the 3rd fpga chip by bus, first dsp chip is connected with DDR2 internal memory and nonvolatile flash memory respectively by bus, second dsp chip is connected with DDR2 internal memory and nonvolatile flash memory respectively by bus, first fpga chip is connected with nonvolatile flash memory and four-way digital down converter respectively by bus, second fpga chip is connected with nonvolatile flash memory and four-way digital down converter respectively by bus, the output of clock distribution module respectively with the first multichannel ADC module and the second multichannel ADC model calling, the 3rd described fpga chip is also connected with CPCIe*4 interface by GPIO bus, and CPCIe*4 Interface realization intermediate frequency acquisition process plate is with the data interaction of host computer,
Multichannel ADC module: the signal of multiple AD passage is sampled, and carries out analog-to-digital conversion;
Fpga chip: coordinate four-way Digital Down Convert to complete baseband-converted, and extract I/Q component, by I, Q component feeding dsp chip through pulse-width matched filter;
The Big Dipper/GPS interface: the function with the Big Dipper and the two navigation of GPS;
Clock distribution module: for the first multichannel ADC module and the second multichannel ADC module provide internal clock or external clock respectively, or carry out clock switching; The sampling clock of multichannel ADC module is mutually independent, can carry out synchronous acquisition when shared external clock and internal clock simultaneously.
2. multichannel ADC synchronized sampling intermediate-frequency receiver according to claim 1, is characterized in that: the signal input part of described clock distribution module is connected with the signal output part of temperature compensating crystal oscillator and the signal end of external clock respectively.
3. multichannel ADC synchronized sampling intermediate-frequency receiver according to claim 1, it is characterized in that: the first described multichannel ADC module and passage AD4, passage AD5, passage AD6 are one group, second multichannel ADC module and passage AD1, passage AD2, passage AD3 are one group, the sampling clock of two groups of AD is mutually independent, often group all can realize any switching laws between internal clock and external clock under the cooperation of clock distribution module, when two groups of AD use homology clock, require that each road AD is synchronous.
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| CN101640545A (en) * | 2009-08-31 | 2010-02-03 | 北京航空航天大学 | Programmable radio frequency down-conversion device |
| CN103036582A (en) * | 2012-12-03 | 2013-04-10 | 高攀峰 | Universal type digital intermediate frequency receiver |
| CN103117767A (en) * | 2013-01-15 | 2013-05-22 | 武汉大学 | Multi-mode multi-frequency global navigational satellite system receiver radio frequency front end device |
| CN203722622U (en) * | 2013-11-25 | 2014-07-16 | 成都九华圆通科技发展有限公司 | Multichannel ADC synchronous-sampling intermediate-frequency receiver |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101640545A (en) * | 2009-08-31 | 2010-02-03 | 北京航空航天大学 | Programmable radio frequency down-conversion device |
| CN103036582A (en) * | 2012-12-03 | 2013-04-10 | 高攀峰 | Universal type digital intermediate frequency receiver |
| CN103117767A (en) * | 2013-01-15 | 2013-05-22 | 武汉大学 | Multi-mode multi-frequency global navigational satellite system receiver radio frequency front end device |
| CN203722622U (en) * | 2013-11-25 | 2014-07-16 | 成都九华圆通科技发展有限公司 | Multichannel ADC synchronous-sampling intermediate-frequency receiver |
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Denomination of invention: A multichannel ADC synchronization sampling intermediate frequency receiver Effective date of registration: 20160728 Granted publication date: 20151104 Pledgee: Agricultural Bank of China Limited by Share Ltd Chengdu West Branch Pledgor: Jiuhua Yuantong Science and Technology Development Co., Ltd., Chengdu Registration number: 2016510000036 |
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