CN103647573A - A multichannel ADC synchronization sampling intermediate frequency receiver - Google Patents
A multichannel ADC synchronization sampling intermediate frequency receiver Download PDFInfo
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- CN103647573A CN103647573A CN201310594342.6A CN201310594342A CN103647573A CN 103647573 A CN103647573 A CN 103647573A CN 201310594342 A CN201310594342 A CN 201310594342A CN 103647573 A CN103647573 A CN 103647573A
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Abstract
The invention discloses a multichannel ADC synchronization sampling intermediate frequency receiver comprising a plurality of FPGA chips and DSP chips. The multichannel ADC synchronization sampling intermediate frequency receiver also comprises a first multichannel ADC module and a second multichannel ADC module. A signal output of the first multichannel ADC module is connected with a signal input of a first FPGA chip. Bidirectional multichannel data connection exists between the first FPGA chip and a first DSP chip. A signal output of a second multichannel ADC module is connected with a signal input of a second FPGA chip. Bidirectional multichannel data connection exists between the second FPGA chip and a second DSP chip. The first multichannel ADC module and the second multichannel ADC module are also connected with a clock distribution module. The multichannel ADC synchronization sampling intermediate frequency receiver is provided with a plurality of AD channels, and at the same time, sampling clocks are mutually independent. Synchronization acquisition can be carried out when an outer clock and an inner clock which are used in common. The multichannel ADC synchronization sampling intermediate frequency receiver is low in cost and high in cost performance. In addition, the multichannel ADC synchronization sampling intermediate frequency receiver can carry out Beidou and GPS satellite positioning, and is high in intelligentized degree.
Description
Technical field
The present invention relates to a kind of digital if receiver, particularly multichannel ADC synchronized sampling intermediate-frequency receiver.
Background technology
Existing Intermediate Frequency Digital Receiver is mainly comprised of single analog to digital converter (ADC) and digital down converter, wherein analog-to-digital conversion module mainly completes the sampling of analog if signal, and conversion obtains digitized intermediate-freuqncy signal, digital down converter is converted to base band by interested signal, do sampling rate conversion and filtering processes simultaneously, obtain the I of quadrature, after Q signal, send follow-up digital signal processor to carry out base band signal process, in whole intermediate-frequency receiver the inside, digital down converter is the core of whole Intermediate Frequency Digital Receiver, but generally, existing Intermediate Frequency Digital Receiver only can realize single pass signal sampling, inefficiency, working method is single.While working on frequent vehicle-carried mobile equipment, often because can not satellite fix and occur various troubles simultaneously.
Number of patent application: 201210507125.4 disclosed a kind of universal digital intermediate-frequency receivers, it comprises multichannel ADC module, multichannel bridge module, multi-channel digital down-conversion ASIC module, multichannel FPGA processing module, multichannel DSP module, over-borrowing mouth output module and DSP top control module, the data output of described multichannel ADC module is connected with the data input of multichannel bridge module, the data output of multichannel bridge module is connected with the data input of multi-channel digital down-conversion ASIC module, the data input of multi-channel digital down-conversion ASIC module connects, the data output of multi-channel digital down-conversion ASIC module is connected with the data input of multichannel FPGA processing module, between multichannel FPGA processing module and multichannel DSP processing module, there are two-way multi-channel data to connect, the data output of multichannel DSP processing module is carried out the output of final result by many interfaces output module, this invention versatility is good, treatment effeciency is high, cost is low.But be not provided with inside and outside clock distribution module, can not carry out multichannel ADC synchronously or asynchronous-sampling, and any switching of interior external clock, be not provided with satellite positioning functions simultaneously, be there is to location defect in the intermediate-frequency receiver using on mobile device.The indoor design structure of this invention is, a plurality of AD passages are connected with a plurality of ADC modules respectively, a plurality of ADC modules are connected with a plurality of Digital Down Convert ASIC modules respectively, a plurality of Digital Down Convert ASIC modules are connected with FPGA processing module again, this project organization adopts the structure of minute circuit, every circuit all needs an AD passage, an ADC module, a Digital Down Convert ASIC module and a FPGA processing module, this project organization, sampling channel is more, design more complicated, cost is also higher, and synchronous signal conversion process ability is also lower.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, a kind of a plurality of AD passages that have are provided, the sampling clock of multichannel ADC module is mutually independent, can carry out the Big Dipper and gps satellite location, can carry out any switching between external clock and internal clock, can realize synchronous acquisition simultaneously, cost is low, cost performance is high, passage configuration and compound mode applying flexible, the much higher passage ADC of intelligent degree synchronized sampling intermediate-frequency receiver.
The object of the invention is to be achieved through the following technical solutions: multichannel ADC synchronized sampling intermediate-frequency receiver, it comprises the first fpga chip, the second fpga chip, the 3rd fpga chip, the first dsp chip, the second dsp chip, the first multichannel ADC module, the second multichannel ADC module and clock distribution module, the signal output of the first multichannel ADC module is connected with the signal input of the first fpga chip, between the first fpga chip and the first dsp chip, by two-way multi-channel data line, be connected, the signal output of the second multichannel ADC module is connected with the signal input of the second fpga chip, between the second fpga chip and the second dsp chip, there are two-way multi-channel data to be connected, the first fpga chip is connected with the second fpga chip by bus, the first dsp chip is connected with the second dsp chip by bus, the first fpga chip is connected with the Big Dipper/GPS interface respectively with the second fpga chip, the 3rd fpga chip is connected with the Big Dipper/GPS interface by spi bus, the first fpga chip is connected with the 3rd fpga chip by bus, the first dsp chip is connected with nonvolatile flash memory with DDR2 internal memory respectively by bus, the second dsp chip is connected with nonvolatile flash memory with DDR2 internal memory respectively by bus, the first fpga chip is connected with four-way digital down converter with nonvolatile flash memory respectively by bus, the second fpga chip is connected with four-way digital down converter with nonvolatile flash memory respectively by bus, the output of clock distribution module is connected with the second multichannel ADC module with the first multichannel ADC module respectively,
Multichannel ADC module: the signal to a plurality of AD passages is sampled, and carry out analog-to-digital conversion;
Fpga chip: coordinate four-way Digital Down Convert to complete baseband-converted, and extract I/Q component, I, Q component through pulse-width matched filter are sent into dsp chip;
The Big Dipper/GPS interface: the function with the two navigation of the Big Dipper and GPS;
Clock distribution module: for the first multichannel ADC module and the second multichannel ADC module provide respectively internal clock or external clock, or carry out clock switching.
The signal input part of described clock distribution module is connected with the signal output part of temperature compensating crystal oscillator and the signal end of external clock respectively.
Described the first multichannel ADC module and passage AD4, passage AD5, passage AD6 are one group, the second multichannel ADC module and passage AD1, passage AD2, passage AD3 are one group, the sampling clock of two groups of AD is mutually independent, under the cooperation of clock distribution module, all can realize any switching between internal clock and external clock for every group, when two groups of AD are used homology clock, require each road AD synchronous.
The 3rd described fpga chip is also connected with CPCIe*4 interface by GPIO bus, and CPCIe*4 Interface realization intermediate frequency acquisition process plate is with the data interaction of host computer.
Receiver inside is also provided with independently-powered interface and power management module, with the normal use power supply to each function element.
The present invention has following advantage:
1, have a plurality of AD passages, the sampling clock of multichannel ADC module is mutually independent, can carry out synchronous acquisition when shared external clock and internal clock simultaneously;
2, be provided with internal clock and external clock, can carry out any switching between internal clock and external clock;
3, be provided with CPCIe*4 interface, can realize intermediate frequency acquisition process plate with the data interaction of host computer;
4, be provided with the Big Dipper/GPS interface, there is the function of the two navigation of the Big Dipper and GPS;
5, ASIC, DSP and tri-kinds of technology of FPGA are carried out to combination, disposal ability is stronger, has higher treatment effeciency;
6, cost is low, and cost performance is high, passage configuration and compound mode applying flexible, and intelligent degree is high, is beneficial to industrialization and produces and use.
Accompanying drawing explanation
Fig. 1 is structural representation of the present invention.
Embodiment
Below in conjunction with accompanying drawing, technical scheme of the present invention is described in further detail, but protection scope of the present invention is not limited to the following stated.
As shown in Figure 1, multichannel ADC synchronized sampling intermediate-frequency receiver, it comprises the first fpga chip, the second fpga chip, the 3rd fpga chip, the first dsp chip, the second dsp chip, the first multichannel ADC module, the second multichannel ADC module and clock distribution module, the signal output of the first multichannel ADC module is connected with the signal input of the first fpga chip, between the first fpga chip and the first dsp chip, by two-way multi-channel data line, be connected, the signal output of the second multichannel ADC module is connected with the signal input of the second fpga chip, between the second fpga chip and the second dsp chip, there are two-way multi-channel data to be connected, the first fpga chip is connected with the second fpga chip by bus, the first dsp chip is connected with the second dsp chip by bus, the first fpga chip is connected with the Big Dipper/GPS interface respectively with the second fpga chip, the 3rd fpga chip is connected with the Big Dipper/GPS interface by spi bus, the first fpga chip is connected with the 3rd fpga chip by bus, the first dsp chip is connected with nonvolatile flash memory with DDR2 internal memory respectively by bus, the second dsp chip is connected with nonvolatile flash memory with DDR2 internal memory respectively by bus, the first fpga chip is connected with four-way digital down converter with nonvolatile flash memory respectively by bus, the second fpga chip is connected with four-way digital down converter with nonvolatile flash memory respectively by bus, the output of clock distribution module is connected with the second multichannel ADC module with the first multichannel ADC module respectively,
Multichannel ADC module: the signal to a plurality of AD passages is sampled, and carry out analog-to-digital conversion;
Fpga chip: coordinate four-way Digital Down Convert to complete baseband-converted, and extract I/Q component, I, Q component through pulse-width matched filter are sent into dsp chip;
The Big Dipper/GPS interface: the function with the two navigation of the Big Dipper and GPS;
Clock distribution module: for the first multichannel ADC module and the second multichannel ADC module provide respectively internal clock or external clock, or carry out clock switching.
The signal input part of described clock distribution module is connected with the signal output part of temperature compensating crystal oscillator and the signal end of external clock respectively.
Described the first multichannel ADC module and passage AD4, passage AD5, passage AD6 are one group, the second multichannel ADC module and passage AD1, passage AD2, passage AD3 are one group, the sampling clock of two groups of AD is mutually independent, under the cooperation of clock distribution module, all can realize any switching between internal clock and external clock for every group, when two groups of AD are used homology clock, require each road AD synchronous.
The 3rd described fpga chip is also connected with CPCIe*4 interface by GPIO bus, and CPCIe*4 Interface realization intermediate frequency acquisition process plate is with the data interaction of host computer.
Receiver inside is also provided with independently-powered interface and power management module, with the normal use power supply to each function element.
Described PCIe bridging chip is LX50T, is connected in CPCIe*4 interface, realizes intermediate frequency acquisition process plate with the data interaction of host computer.It is upper that LX50T chip has 15 GPIO after driving, to link CPCIe connector Xj4, for FPGA, to external equipment, sends order, reach+5V of the signal level after driving or+12V.
Described dsp chip is the DSP:TMS320C6455 of 1GHz dominant frequency, connects Rapid IO*4 (1.25Gbps) interface He Yi road McBSP interface between the first described dsp chip and the second dsp chip.
Claims (4)
1. multichannel ADC synchronized sampling intermediate-frequency receiver, it is characterized in that: it comprises the first fpga chip, the second fpga chip, the 3rd fpga chip, the first dsp chip, the second dsp chip, the first multichannel ADC module, the second multichannel ADC module and clock distribution module, the signal output of the first multichannel ADC module is connected with the signal input of the first fpga chip, between the first fpga chip and the first dsp chip, by two-way multi-channel data line, be connected, the signal output of the second multichannel ADC module is connected with the signal input of the second fpga chip, between the second fpga chip and the second dsp chip, there are two-way multi-channel data to be connected, the first fpga chip is connected with the second fpga chip by bus, the first dsp chip is connected with the second dsp chip by bus, the first fpga chip is connected with the Big Dipper/GPS interface respectively with the second fpga chip, the 3rd fpga chip is connected with the Big Dipper/GPS interface by spi bus, the first fpga chip is connected with the 3rd fpga chip by bus, the first dsp chip is connected with nonvolatile flash memory with DDR2 internal memory respectively by bus, the second dsp chip is connected with nonvolatile flash memory with DDR2 internal memory respectively by bus, the first fpga chip is connected with four-way digital down converter with nonvolatile flash memory respectively by bus, the second fpga chip is connected with four-way digital down converter with nonvolatile flash memory respectively by bus, the output of clock distribution module is connected with the second multichannel ADC module with the first multichannel ADC module respectively,
Multichannel ADC module: the signal to a plurality of AD passages is sampled, and carry out analog-to-digital conversion;
Fpga chip: coordinate four-way Digital Down Convert to complete baseband-converted, and extract I/Q component, I, Q component through pulse-width matched filter are sent into dsp chip;
The Big Dipper/GPS interface: the function with the two navigation of the Big Dipper and GPS;
Clock distribution module: for the first multichannel ADC module and the second multichannel ADC module provide respectively internal clock or external clock, or carry out clock switching.
2. multichannel ADC synchronized sampling intermediate-frequency receiver according to claim 1, is characterized in that: the signal input part of described clock distribution module is connected with the signal output part of temperature compensating crystal oscillator and the signal end of external clock respectively.
3. multichannel ADC synchronized sampling intermediate-frequency receiver according to claim 1, it is characterized in that: described the first multichannel ADC module and passage AD4, passage AD5, passage AD6 are one group, the second multichannel ADC module and passage AD1, passage AD2, passage AD3 are one group, the sampling clock of two groups of AD is mutually independent, under the cooperation of clock distribution module, all can realize any switching between internal clock and external clock for every group, when two groups of AD are used homology clock, require each road AD synchronous.
4. multichannel ADC synchronized sampling intermediate-frequency receiver according to claim 1, it is characterized in that: the 3rd described fpga chip is also connected with CPCIe*4 interface by GPIO bus, CPCIe*4 Interface realization intermediate frequency acquisition process plate is with the data interaction of host computer.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110505018A (en) * | 2019-08-08 | 2019-11-26 | 中国科学院光电技术研究所 | A kind of large-scale optical fiber swashs the high-speed processing circuits of combiner and coupling array |
| CN111812686A (en) * | 2020-07-21 | 2020-10-23 | 山东大学 | Navigation signal receiver and clock distribution method thereof |
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| CN101640545A (en) * | 2009-08-31 | 2010-02-03 | 北京航空航天大学 | Programmable radio frequency down-conversion device |
| CN103036582A (en) * | 2012-12-03 | 2013-04-10 | 高攀峰 | Universal type digital intermediate frequency receiver |
| CN103117767A (en) * | 2013-01-15 | 2013-05-22 | 武汉大学 | Multi-mode multi-frequency global navigational satellite system receiver radio frequency front end device |
| CN203722622U (en) * | 2013-11-25 | 2014-07-16 | 成都九华圆通科技发展有限公司 | Multichannel ADC synchronous-sampling intermediate-frequency receiver |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101640545A (en) * | 2009-08-31 | 2010-02-03 | 北京航空航天大学 | Programmable radio frequency down-conversion device |
| CN103036582A (en) * | 2012-12-03 | 2013-04-10 | 高攀峰 | Universal type digital intermediate frequency receiver |
| CN103117767A (en) * | 2013-01-15 | 2013-05-22 | 武汉大学 | Multi-mode multi-frequency global navigational satellite system receiver radio frequency front end device |
| CN203722622U (en) * | 2013-11-25 | 2014-07-16 | 成都九华圆通科技发展有限公司 | Multichannel ADC synchronous-sampling intermediate-frequency receiver |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110505018A (en) * | 2019-08-08 | 2019-11-26 | 中国科学院光电技术研究所 | A kind of large-scale optical fiber swashs the high-speed processing circuits of combiner and coupling array |
| CN111812686A (en) * | 2020-07-21 | 2020-10-23 | 山东大学 | Navigation signal receiver and clock distribution method thereof |
| CN111812686B (en) * | 2020-07-21 | 2023-07-14 | 山东大学 | Navigation signal receiver and clock distribution method thereof |
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Denomination of invention: A multichannel ADC synchronization sampling intermediate frequency receiver Effective date of registration: 20160728 Granted publication date: 20151104 Pledgee: Agricultural Bank of China Limited by Share Ltd Chengdu West Branch Pledgor: Jiuhua Yuantong Science and Technology Development Co., Ltd., Chengdu Registration number: 2016510000036 |
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Date of cancellation: 20201224 Granted publication date: 20151104 Pledgee: Agricultural Bank of China Limited by Share Ltd. Chengdu West Branch Pledgor: CHENGDU JIUHUA YUANTONG TECHNOLOGY DEVELOPMENT Co.,Ltd. Registration number: 2016510000036 |