CN217135476U - Signal receiving device based on ELoran system - Google Patents
Signal receiving device based on ELoran system Download PDFInfo
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- CN217135476U CN217135476U CN202220325741.7U CN202220325741U CN217135476U CN 217135476 U CN217135476 U CN 217135476U CN 202220325741 U CN202220325741 U CN 202220325741U CN 217135476 U CN217135476 U CN 217135476U
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Abstract
The utility model discloses a signal receiving device based on ELoran system, include: the device comprises a power supply module, a radio frequency signal processing module, an analog-to-digital signal conversion module and a baseband signal processing module; the radio frequency signal processing module is used for acquiring and obtaining an ELoran antenna signal, performing primary processing on the ELoran antenna signal and outputting the ELoran signal after the primary processing; the analog-digital signal conversion module is used for inputting the ELoran signal after the primary processing, performing single-ended signal conversion differential signal and analog-digital signal conversion processing and outputting a low-voltage differential signal; the baseband signal processing module is used for inputting a low-voltage differential signal and carrying out signal demodulation and decoding processing to obtain demodulation and decoding data; outputting the pulse per second based on the demodulated decoded data. The utility model discloses can simplify the hardware and constitute, can optimize signal data transmission process simultaneously, improve the signal reception processing speed of device.
Description
Technical Field
The utility model belongs to the technical field of signal receiving device, in particular to signal receiving device based on ELoran system.
Background
The Loran-C system (illustratively explained, including BPL long wave time service system and the longhe second navigation system) maintains synchronization with coordinated Universal Time (UTC) by establishing a traceability relationship with national standard time UTC (ntsc), and further realizes high-precision time service by broadcasting radio signals, and has the advantages of stable ground wave phase, strong anti-interference capability, wide coverage range, low construction cost, differential enhancement function, and the like, and has become the most important ground-based time service means, and is an indispensable important component in the national time frequency system architecture.
The BPL long-wave time service system and the Changhe navigation system II are upgraded and modified in 2008, data transmission functions such as time code information are added by adopting the Eurofix technology, and the ELoran system is constructed under ELoran signal transmission conditions. Based on this, the existing signal receiving device is generally based on an FPGA + DSP architecture or an FPGA + MCU architecture, the hardware structure of the device is complex, the transmission process of signal data is complex, the time consumption is long, and a new signal receiving device is urgently needed.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a signal receiving arrangement based on ELoran system to solve above-mentioned one or more technical problem who exists.
In order to achieve the above purpose, the utility model adopts the following technical scheme:
the utility model provides a pair of signal receiving arrangement based on ELoran system, include: the device comprises a power supply module, a radio frequency signal processing module, an analog-to-digital signal conversion module and a baseband signal processing module;
the power supply module is used for supplying power to the radio frequency signal processing module, the analog-digital signal conversion module and the baseband signal processing module;
the radio frequency signal processing module is used for acquiring and obtaining an ELoran antenna signal, performing primary processing on the ELoran antenna signal and outputting the ELoran signal after the primary processing; the primary processing comprises band-pass filtering, adaptive notch and automatic gain control processing;
the analog-digital signal conversion module is used for inputting the ELoran signal after the primary processing, performing single-ended signal conversion differential signal and analog-digital signal conversion processing and outputting a low-voltage differential signal;
the baseband signal processing module is used for inputting the low-voltage differential signal and carrying out signal demodulation and decoding processing to obtain demodulation and decoding data; outputting a second pulse based on the demodulated decoded data;
the baseband signal processing module adopts a Xilinx ZYNQ7Z020 processor chip, and the XilinxZYNQ7Z020 processor chip is integrated with directly connected programmable logic resources and a processing system.
The utility model discloses the further improvement of device lies in, power module includes:
the direct-current voltage conversion chip LMR16030 is used for inputting DC + 18- +24V voltage and converting and outputting +5V voltage;
the direct-current voltage conversion chip LT1931 is used for inputting +5V voltage and converting and outputting-5V voltage;
the direct-current voltage conversion chip LD1117-3.3V is used for inputting +5V voltage and converting and outputting +3.3V voltage;
the direct-current voltage conversion chip LD1117-1.8V is used for inputting +3.3V voltage and converting and outputting +1.8V voltage.
The utility model discloses the further improvement of the device lies in, the input of power module is provided with self-resuming fuse, piezo-resistor and diode; the self-recovery fuse is used for preventing current in a power supply loop from being overlarge, the voltage dependent resistor is used for preventing the amplitude of input voltage from being overlarge, and the diode is used for preventing the reverse connection of the input power supply.
The utility model discloses the further improvement of the device lies in, the radio frequency signal processing module includes band-pass filter, self-adaptation wave trap and automatic gain control circuit; the band-pass filter is used for inputting an ELoran antenna signal to perform band-pass filtering processing and outputting a signal after primary processing; the self-adaptive notch filter is used for inputting the signal subjected to the primary processing to perform self-adaptive notch processing and outputting a signal subjected to secondary processing; the automatic gain control circuit is used for inputting the signals after the secondary processing to perform automatic gain control processing and outputting ELoran signals after primary processing.
The device of the present invention is further improved in that the analog-to-digital signal conversion module comprises a high-speed operational amplifier LT1819CS8 and a high-speed analog-to-digital conversion chip LTC2324 UKG-16; the high-speed operational amplifier LT1819CS8 is used for inputting the ELoran signal after the primary processing, and converting the ELoran signal into a differential signal for outputting; the high-speed analog-to-digital conversion chip LTC2324UKG-16 is used for inputting the differential signal and converting the differential signal into a low-voltage differential signal for outputting.
The utility model discloses the further improvement of device lies in, the reference ground wire end input of ELoran signal after the preliminary treatment No. 5 pin of high-speed operational amplifier LT1819CS8, the signal wire end input of ELoran signal after the preliminary treatment No. 3 pin of high-speed operational amplifier LT1819CS8, No. 1 pin and No. 7 pin of high-speed operational amplifier LT1819CS8 output are as the both ends of a passageway difference signal line.
The device of the present invention is further improved in that the input pin 14 and the input pin 13 of the high-speed analog-to-digital conversion chip LTC2324UKG-16 are input pins of a first pair of differential signals, and the output pin 27 and the output pin 28 are output pins of a corresponding first pair of low-voltage differential signals; the number of an input pin 11 and the number of an input pin 10 of the high-speed analog-to-digital conversion chip LTC2324UKG-16 are input pins of a second pair of differential signals, and an output pin 29 and an output pin 30 are corresponding output pins of a second pair of low-voltage differential signals; the number 4 of the input pin and the number 5 of the input pin of the high-speed analog-to-digital conversion chip LTC2324UKG-16 are input pins of a third pair of differential signals, and the output pin 35 and the output pin 36 are corresponding output pins of the third pair of low-voltage differential signals; and the number of the input pin 24 of the high-speed analog-to-digital conversion chip LTC2324UKG-16 is an enabling working pin of the chip.
The device of the utility model is further improved in that the processing system is a dual-core ARM Cortex-A9 processor; the programmable logic resource is an ARTIX-7 architecture 28nm programmable logic resource.
The device of the utility model is further improved in that the pin Y14 and the pin AA14 of the Xilinx ZYNQ7Z020 processor chip are the input of a first pair of low voltage differential signals; the AA17 pin and the AB17 pin of the Xilinx ZYNQ7Z020 processor chip are used as the input of a second pair of low-voltage differential signals; the pin Y19 and the pin AA19 of the Xilinx ZYNQ7Z020 processor chip are used for inputting a third pair of low-voltage differential signals; and a pin V15 of the Xilinx ZYNQ7Z020 processor chip is an enabling working pin of the control chip LTC2324UKG, and a pin V9 is an output pin of the pulse per second.
Compared with the prior art, the utility model discloses following beneficial effect has:
the utility model provides a signal receiving device adopts ZYNQ7Z020 as the main chip of device, and its inside has PL (Program Logic) and PS (Program System, processing System) simultaneously, can accomplish multiple signal receiving device function, can simplify the hardware composition; meanwhile, partial functional modules in the device are integrated in the chip, so that the transmission process of signal data can be optimized, and the signal receiving and processing speed of the device is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art are briefly introduced below; it is obvious that the drawings in the following description are some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
Fig. 1 is a schematic block diagram of a signal receiving apparatus based on an ELoran system according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a power module according to an embodiment of the present invention; wherein, fig. 2 (a) is a schematic diagram of a +5V power module, fig. 2 (b) is a schematic diagram of a-5V power module, fig. 2 (c) is a schematic diagram of a +3.3V power module, and fig. 2 (d) is a schematic diagram of a +1.8V power module;
fig. 3 is a schematic diagram of a radio frequency signal processing module according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a single-ended signal conversion principle of the analog-to-digital signal conversion module according to the embodiment of the present invention;
fig. 5 is a schematic diagram illustrating an embodiment of the present invention, wherein the analog-to-digital signal conversion module LTC2324UKG-16 is shown in the embodiment;
fig. 6 is a schematic block diagram of the baseband signal processing module hardware according to the embodiment of the present invention.
Detailed Description
Referring to fig. 1, a signal receiving apparatus based on an ELoran system according to an embodiment of the present invention includes: the device comprises a power module, a radio frequency signal processing module, an analog-to-digital signal conversion module and a baseband signal processing module.
The power supply module is used for supplying power to the radio frequency signal processing module, the analog-to-digital signal conversion module and the baseband signal processing module;
the radio frequency signal processing module is used for acquiring and obtaining an ELoran antenna signal, performing primary processing on the ELoran antenna signal and outputting the ELoran signal after the primary processing; wherein the preliminary processing comprises: band-pass filtering, radio frequency amplification, adaptive notch and automatic gain control processing;
the analog-to-digital signal conversion module is used for inputting the ELoran signal after the primary processing, performing single-ended signal conversion differential signal and analog-to-digital signal conversion processing and outputting a low-voltage differential signal;
the baseband signal processing module is used for inputting the low-voltage differential signal and carrying out signal demodulation and decoding processing to obtain demodulation and decoding data; outputting a second pulse based on the demodulated decoded data;
the baseband signal processing module adopts ZYNQ7Z020 as a main chip, and has PL (programmable Logic) and PS (Program System) inside the baseband signal processing module, and is used for completing functions of various signal receiving devices.
Referring to fig. 2, a power module in the device according to the embodiment of the present invention mainly includes a dc voltage conversion chip and a power status indicator, and is used to complete power supply of each module of the whole device, thereby ensuring normal operation of the device. As shown in fig. 2 (a), the input voltage of the POWER module is DC +18 to +24V, pin 1 of the POWER terminal POWER is the input voltage, pin 2 is the signal ground, pin 3 is the reference ground of the input voltage, a self-recovery fuse F500, a voltage dependent resistor RL500 and a diode D500 (illustratively, the self-recovery fuse is used to prevent the current in the POWER circuit from being too large; the voltage dependent resistor is used to prevent the amplitude of the input voltage from being too large; the diode is used to prevent the reverse connection of the input POWER) are added to the input end to self-protect the POWER module, the input voltage is converted into +5V output by the DC voltage conversion chip LMR16030, pin 2 of LMR16030 is the input voltage, pin 7 and pin 8 are the reference ground of the input voltage and the output voltage, and pin 8 is the output voltage; the resistors R503 and R504 determine the amplitude of the output voltage after conversion, the calculation formula is that the output voltage Vout is (R503/R504+1) × 0.75, the capacitors C501 and C502 are used as filter capacitors of +5V output voltage to reduce the influence of voltage ripple change, R501 is used for current limitation of an enable pin (pin No. 3) of the chip EN, R502 is used for controlling the switching frequency of the power supply chip, and D501 is a freewheeling diode to provide a reverse discharge loop for the inductor L500 to protect a rear-stage circuit.
When there is +5V power output, the LED indicator PWR is normally on, as shown in fig. 2 (b), the dc voltage conversion chip LT1931 converts +5V input into-5V output, pin 5 is +5V voltage input, pin 2 is +5V input and-5V output reference power ground, pin 1 is-5V voltage output, where R506 and R507 determine the amplitude of the output voltage after conversion, the calculation formula is that the output voltage Vout is (R507/R506+0.9996) × 1.255, capacitors C521 and C520 are filter capacitors for the +5V output voltage, the influence of the voltage ripple variation is reduced, and R505 is used for pin 4 of the chip
Enabling current limiting of the pin, D502 provides a freewheeling diode with a reverse discharge loop for inductor L502 to protect the subsequent circuitry.
As shown in (C) of fig. 2, the dc voltage converting chip LD1117-3.3V converts the input +5V into +3.3V output, pin 3 is +5V voltage input, pin 1 is the reference ground for +5V voltage input and +3.3V voltage output, and pin 2 is +3.3V voltage output, where the capacitors C508 and C509 are used as filter capacitors for the +3.3V power output, so as to reduce the influence of the voltage ripple variation.
As shown in (d) of fig. 2, the dc voltage converting chip LD1117-1.8V converts the input +3.3V into +1.8V output, pin 3 is +3.3V voltage input, pin 1 is the reference ground for +3.3V voltage input and +1.8V voltage output, pin 2 is +1.8V voltage output, and 3, wherein the capacitors C512 and C513 are used as filter capacitors for the +1.8V power output, thereby reducing the influence of the voltage ripple variation.
Please refer to fig. 3, the embodiment of the present invention provides a radio frequency signal processing module in a device, which mainly comprises a band pass filter, an automatic gain control circuit, a wave trap, etc., wherein an antenna signal interface is connected to the input of the band pass filter, the output of the band pass filter is connected to the input of the adaptive wave trap, the output of the adaptive wave trap is connected to the input of the automatic gain controller, the automatic gain controller outputs an initial processed ELoran signal, the module is used for completing the acquisition and simple initial processing of the ELoran antenna signal, and the initial processed ELoran signal is transmitted to an analog-to-digital signal conversion module. As shown in fig. 3, after the ELoran signal collected by the antenna is processed by the band pass filter, the adaptive notch filter and the automatic gain controller, a single-ended signal is obtained and transmitted to the analog-to-digital signal conversion module.
Referring to fig. 4 and 5, an analog-to-digital signal conversion module in an apparatus according to an embodiment of the present invention mainly includes a synchronous sampling analog-to-digital converter and its related supporting circuits, and the module is used to complete single-ended signal conversion and analog-to-digital signal conversion. Illustratively, as shown in fig. 4, a high-speed operational amplifier LT1819CS8 is used to convert an input single-ended signal into a differential signal, and three channels of data can be processed simultaneously in the analog-to-digital signal conversion module, and only one channel connection relationship is described because the three channels have the same structure. The eleran signal after the preliminary processing is input into pin No. 5 of LT1819CS8 with reference to the ground terminal, pin No. 3 is input into the signal terminal, and pin No. 1 and pin No. 7 output are two ends of a channel differential signal line. As shown in fig. 5, the module employs a high-speed analog-to-digital conversion chip LTC2324UKG-16, which supports four-channel high-speed synchronous sampling, and has 16-bit resolution, differential input, and wide input common mode range. The module uses an operational amplifier chip LT1819CS8 to convert the single-ended signal transmitted by the radio frequency signal processing module into a differential signal, and then the analog-to-digital conversion chip converts the signal into LVDS (low voltage differential signal) and transmits the LVDS to the baseband signal processing module, LTC2324UKG-16 can process the differential signal of four channels, only three channels exist in the device, the input pin 14 and the input pin 13 are input pins of a first pair of differential signals, the output pin 27 and the output pin 28 are corresponding first pair of LVDS output pins, the input pin 11 and the input pin 10 are input pins of a second pair of differential signals, the output pin 29 and the output pin 30 are corresponding second pair of LVDS output pins, the input pin 4 and the input pin 5 are input pins of a third pair of differential signals, the output pin 35 and the output pin 36 are corresponding third pair of LVDS output pins, and the input pin 24 is an enable working pin of the chip.
Referring to fig. 6, the baseband signal processing module in the device according to the embodiment of the present invention mainly comprises Xilinx ZYNQ7Z020 programmable SoC (SoC: system on chip/system on chip) and its related supporting circuits, and the module mainly completes the functions of ELoran signal search and capture, carrier phase tracking and period identification, information demodulation and decoding, and timing signal generation. The module adopts a Xilinx ZYNQ7Z020 processor chip which has excellent calculation and graphic display performance, a dual-core ARM Cortex-A9 processor (PS: Program System) is integrated on the chip, and an ARTIX-7 architecture 28nm programmable Logic resource (PL: Program Logic) is integrated; the module is simultaneously provided with 1GB DDR3L SDRAM (adopting 32-bit bus, data rate of 1066MHz), 256MB SPI FLASH, 64GB eMMC memory and the like, which can meet the requirement of baseband signal processing, the module receives LVDS signals transmitted by the analog-digital signal conversion module, performs signal peak detection by using a signal processing algorithm to complete ELoran signal search and capture, then completes carrier phase tracking and period identification, and obtains time code data by ELoran information demodulation, RS decoding, CRC decoding and text resolution, and generating a timing signal second pulse 1PPS (pulse Per second) according to the time code data, wherein a pin Y14 and a pin AA14 of ZYNQ7Z020 are used as input of a first pair of LVDS signals, a pin AA17 and a pin AB17 are used as input of a second pair of LVDS signals, a pin Y19 and a pin AA19 are used as input of a third pair of LVDS signals, a pin V15 is used as work enabling of a control chip LTC2324UKG, and a pin V9 is used as an output pin of the second pulse. The input LVDS signals are processed by PS and PL inside the chip, and the PS and PL are directly connected inside the chip, so that the signal processing transmission rate is greatly improved, and the hardware composition of the system is simplified.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present invention and not for limiting the same, and although the present invention is described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: modifications and equivalents of the embodiments of the invention may be made without departing from the spirit and scope of the invention, which should be construed as falling within the scope of the claims of the invention.
Claims (9)
1. A signal receiving apparatus based on an ELoran system, comprising: the device comprises a power supply module, a radio frequency signal processing module, an analog-to-digital signal conversion module and a baseband signal processing module;
the power supply module is used for supplying power to the radio frequency signal processing module, the analog-digital signal conversion module and the baseband signal processing module;
the radio frequency signal processing module is used for acquiring and obtaining an ELoran antenna signal, performing primary processing on the ELoran antenna signal and outputting the ELoran signal after the primary processing; the primary processing comprises band-pass filtering, adaptive notch and automatic gain control processing;
the analog-digital signal conversion module is used for inputting the ELoran signal after the primary processing, performing single-ended signal conversion differential signal and analog-digital signal conversion processing and outputting a low-voltage differential signal;
the baseband signal processing module is used for inputting the low-voltage differential signal and carrying out signal demodulation and decoding processing to obtain demodulation and decoding data; outputting a second pulse based on the demodulated decoded data;
the baseband signal processing module adopts a Xilinx ZYNQ7Z020 processor chip, and the Xilinx ZYNQ7Z020 processor chip is integrated with directly connected programmable logic resources and a processing system.
2. The ELoran-system-based signal receiving apparatus according to claim 1, wherein the power module includes:
the direct-current voltage conversion chip LMR16030 is used for inputting DC + 18- +24V voltage and converting and outputting +5V voltage;
the direct-current voltage conversion chip LT1931 is used for inputting +5V voltage and converting and outputting-5V voltage;
the direct-current voltage conversion chip LD1117-3.3V is used for inputting +5V voltage and converting and outputting +3.3V voltage;
the direct-current voltage conversion chip LD1117-1.8V is used for inputting +3.3V voltage and converting and outputting +1.8V voltage.
3. The signal receiving device based on the ELoran system of claim 1, wherein the input terminal of the power module is provided with a self-recovery fuse, a voltage dependent resistor and a diode; the self-recovery fuse is used for preventing current in a power supply loop from being overlarge, the voltage dependent resistor is used for preventing the amplitude of input voltage from being overlarge, and the diode is used for preventing the reverse connection of the input power supply.
4. The signal receiving device based on the ELoran system of claim 1, wherein the rf signal processing module comprises a band pass filter, an adaptive notch filter and an automatic gain control circuit; the band-pass filter is used for inputting an ELoran antenna signal to perform band-pass filtering processing and outputting a signal after primary processing; the self-adaptive notch filter is used for inputting the signal subjected to the primary processing to perform self-adaptive notch processing and outputting a signal subjected to secondary processing; and the automatic gain control circuit is used for inputting the signals after the secondary processing to perform automatic gain control processing and outputting the ELoran signals after the primary processing.
5. The signal receiving device of claim 1, wherein the analog-to-digital signal conversion module comprises a high-speed operational amplifier LT1819CS8 and a high-speed analog-to-digital conversion chip LTC2324 UKG-16; the high-speed operational amplifier LT1819CS8 is used for inputting the ELoran signal after the primary processing, and converting the ELoran signal into a differential signal for outputting; the high-speed analog-to-digital conversion chip LTC2324UKG-16 is used for inputting the differential signal and converting the differential signal into a low-voltage differential signal for outputting.
6. The signal receiving device according to claim 5, wherein the reference ground terminal of the preliminary processed ELoran signal is inputted to pin No. 5 of said high speed operational amplifier LT1819CS8, the signal terminal of the preliminary processed ELoran signal is inputted to pin No. 3 of said high speed operational amplifier LT1819CS8, and pin No. 1 and pin No. 7 outputted from said high speed operational amplifier LT1819CS8 are used as both ends of a channel differential signal line.
7. The signal receiving device of claim 6, wherein the signal receiving device comprises a first signal receiving unit,
the input pin 14 and the input pin 13 of the high-speed analog-to-digital conversion chip LTC2324UKG-16 are input pins of a first pair of differential signals, and the output pin 27 and the output pin 28 are corresponding first pair of low-voltage differential signal output pins;
the number of an input pin 11 and the number of an input pin 10 of the high-speed analog-to-digital conversion chip LTC2324UKG-16 are input pins of a second pair of differential signals, and an output pin 29 and an output pin 30 are corresponding output pins of a second pair of low-voltage differential signals;
the number 4 of the input pin and the number 5 of the input pin of the high-speed analog-to-digital conversion chip LTC2324UKG-16 are input pins of a third pair of differential signals, and the output pin 35 and the output pin 36 are corresponding output pins of the third pair of low-voltage differential signals;
and the number of the input pin 24 of the high-speed analog-to-digital conversion chip LTC2324UKG-16 is an enabling working pin of the chip.
8. The signal receiving device of claim 7, wherein the signal receiving device comprises a first signal receiving unit,
the processing system is a dual-core ARM Cortex-A9 processor;
the programmable logic resource is an ARTIX-7 architecture 28nm programmable logic resource.
9. The signal receiving device of claim 8, wherein the signal receiving device comprises a first signal receiving unit,
the pin Y14 and the pin AA14 of the Xilinx ZYNQ7Z020 processor chip are used as the input of a first pair of low-voltage differential signals; the AA17 pin and the AB17 pin of the Xilinx ZYNQ7Z020 processor chip are input of a second pair of low-voltage differential signals; the pin Y19 and the pin AA19 of the Xilinx ZYNQ7Z020 processor chip are used for inputting a third pair of low-voltage differential signals;
and a pin V15 of the Xilinx ZYNQ7Z020 processor chip is an enabling working pin of the control chip LTC2324UKG, and a pin V9 is an output pin of the pulse per second.
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