CN113965220A

CN113965220A - Universal interface processing device for radio frequency terminal

Info

Publication number: CN113965220A
Application number: CN202111159171.5A
Authority: CN
Inventors: 赵小刚; 张晓波; 吴江; 李超然; 胡洪
Original assignee: Southwest Electronic Technology Institute No 10 Institute of Cetc
Current assignee: Southwest Electronic Technology Institute No 10 Institute of Cetc
Priority date: 2021-09-30
Filing date: 2021-09-30
Publication date: 2022-01-21
Anticipated expiration: 2041-09-30
Also published as: CN113965220B

Abstract

The universal interface processing device for the radio frequency terminal disclosed by the invention has the advantages of high degree of generalization, reasonable functional area division and strong expandability. The invention is realized by the following technical scheme: the rigid-flex board is combined with the high-speed signal processing main board and the interface processing auxiliary board through the magnetic suction connector with the buckle to complete interface connection of the main board and the auxiliary board; the interface processing subplate completes module interface processing and state detection, and detection of the high-speed interface conversion circuit, the low-speed interface conversion circuit and the detection circuit, the high-speed data processing circuit adopts a DSP of an external DDR, an FPGA and an external memory SDRAM, an interactive architecture is connected through an external memory interface EMIF interface, the FPGA receives, analyzes and processes telemetering data, real-time processed data is sent into the DSP through the external memory interface EMIF and then is returned to the FPGA through the EMIF, the FPGA completes control and management of each interface, and meanwhile, the working state of the radio frequency terminal is monitored and reported.

Description

Universal interface processing device for radio frequency terminal

Technical Field

The invention relates to the fields of space measurement and control, communication and the like, in particular to a universal interface processing device.

Background

At present, the aerospace measurement and control radio frequency equipment generally adopts a design idea based on a special hardware circuit, and each radio frequency equipment realizes a specific function. With the rapid development of wireless measurement and control technology, the implementation approaches of radio frequency electronic equipment are continuously enriched and improved, and the difficulties of increased number of radio frequency equipment, complex electromagnetic environment among equipment, large system volume, large workload of test operation and maintenance, large personnel demand and the like are brought while the measurement and control reliability is improved.

The interfaces of the electronic product are bridges for communication between the same equipment and different equipment, and the interfaces use a uniform protocol standard, so that the interaction between the equipment with no difference at the user end can be really realized. Along with the more and more complicated interface requirements, the radio frequency terminal interfaces required by various products are various, and the common interfaces at present are interfaces such as a low voltage differential signal interface LVDS, a serial interface RS485/422, an LVTTL/TTL and the like. In addition, TTL multi-channel data signals are transmitted in a flat cable mode, the quantity of the whole flat cable reaches dozens of circuits, and the liquid crystal display driving board is inconvenient to connect and not suitable for the trend of ultra-thinning. In a communication system, a radio frequency front end generally includes: amplifiers, filters, frequency converters, and some rf connections and matching circuits. The traditional interface processing device usually adopts a common connector for direct connection, which not only causes high module customization degree and serious repeated design phenomenon, but also causes unreasonable function area division and weak expansibility, thereby not only increasing the system complexity and reducing the system reliability, but also causing the interface device to be difficult to adapt to installation environments with higher space requirements such as missile-borne and the like. The aerospace measurement and control system refers to a special technical facility for tracking, measuring and controlling each stage of aircrafts such as rockets, missiles, satellites and the like. With the development of application satellites, particularly the convergence and butt joint of navigation satellites, high-resolution remote sensing satellites and manned spacecrafts, space shuttles and interplanetary and longer-distance navigation, higher requirements are put forward on a space flight measurement and control system. The radio frequency terminal general interface processing device is a core component of an aerospace measurement and control integrated radio frequency terminal system, and the functions of the radio frequency terminal general interface processing device generally comprise: 1) receiving and analyzing telemetry data; 2) monitoring and reporting the working state of the radio frequency terminal; 3) and controlling and managing other functional modules. Due to the missile-borne application environment, the parts are required to be miniaturized, light in weight, compact in structure, high in integration and the like as far as possible, and meanwhile, the reliable work of the radio frequency terminal is guaranteed. In recent years, based on the rapid development of an embedded micro-kernel data processing technology, the appearance of software radio design ideas, open system architecture and a generalized hardware platform design concept, a solid technical foundation is provided for the research and the manufacture of an aircraft-mounted comprehensive radio frequency terminal with high efficiency-cost ratio, low cost and good expansibility.

Disclosure of Invention

Aiming at the problems and the defects existing in the prior art, the invention provides the universal interface processing device with high generalization degree, reasonable function area division and strong expandability, so as to overcome the problems of high customization degree, unreasonable function area division, low expandability and reusability and the like of the traditional interface processing device.

The above object of the present invention can be achieved by a radio frequency terminal universal interface processing apparatus, comprising: the high-speed signal processing main board, the interface processing auxiliary board and the rigid-flex connecting board for connecting the high-speed signal processing main board and the interface processing auxiliary board provide a working power supply to complete a power supply circuit for supplying power to the main board; the method is characterized in that: the rigid-flex board is combined with the high-speed signal processing main board and the interface processing auxiliary board through the magnetic suction connector with the buckle to complete interface connection of the main board and the auxiliary board; the high-speed signal processing mainboard is provided with a high-speed data processing circuit and an interface processing subplate thereof, the high-speed data processing circuit is connected with a power supply circuit and a clock circuit, the clock circuit provides a mainboard working clock, the high-speed data processing circuit completes a real-time data processing function, the interface processing subplate completes module interface processing and state detection, and the high-speed interface conversion circuit, the low-speed interface conversion circuit and the detection circuit detect, wherein the high-speed interface conversion circuit and the low-speed interface conversion circuit complete various interface conversions of the module, and the detection circuit completes module working voltage and environment temperature monitoring and reports to the control terminal through the interface conversion circuit; the high-speed data processing circuit adopts a plug-in double-rate synchronous dynamic random access memory DDR, a field programmable gate array FPGA and a digital signal processor DSP of a plug-in synchronous dynamic random access memory SDRAM, an interactive architecture is connected through an external memory interface EMIF interface, the FPGA receives, analyzes and processes telemetering data, real-time processed data are sent to the DSP through the external memory interface EMIF, the data are returned to the FPGA through the EMIF after being processed, the FPGA controls and manages each interface, and simultaneously monitors and reports the working state of the radio frequency terminal.

Compared with the prior art, the invention has the following beneficial effects:

simple structure, reliable connection and convenient replacement. The rigid-flex connecting plate is connected between the high-speed signal processing main board and the interface processing auxiliary board, and the rigid-flex connecting plate is directly connected with the main board and the auxiliary board through the magnetic connector, so that the use is simple and convenient, the replacement is convenient, the direct connection of cables is reduced, and the risk of wiring errors is reduced; the magnetic connector with the buckle is selected for use, so that the maintainability and the reliability of the device are powerfully improved under the condition of ensuring reliable connection. Through the organic combination of magnetism connector and rigid-flex board, satisfying under the prerequisite of connecting the reliability requirement, it is also very convenient to change, can adapt to the scene demand of different connection length simultaneously, provides maintainability and the scalability of device. The LVDS overcomes the defects of large power consumption, large EMI electromagnetic interference and the like when broadband high-code-rate data is transmitted in a TTL level mode, and has good universality and reusability. The invention places the high-speed data processing function on the main board, places the interface processing part on the auxiliary board, can meet the design requirements of most application scenes on the main board by reasonably dividing the functions of the main board and the auxiliary board, can meet the requirements of new application scenes only by changing the rigid-flexible connecting board or the interface processing auxiliary board, and improves the universality and the reusability of the device. The mainboard can satisfy the high-speed data real-time processing functional requirement of most scenes, and provides enough IO mouth through magnetism connector of inhaling. When the connection length between the main plate and the auxiliary plate does not meet the design requirement, the design requirement can be met only by changing the rigid-flex connector plate; when the type and the number of the interfaces of the auxiliary plate do not meet the requirements, only the design of the auxiliary plate can be changed; and in the case of comparative limit, the interface processing auxiliary plate and the rigid-flexible connector plate or even the signal processing main plate need to be changed together. Therefore, the device can greatly save development period and has good universality and reusability.

The invention adopts the high-speed signal processing mainboard of the high-speed data processing circuit connected with the power circuit and the clock reset circuit, simultaneously realizes the temperature detection and the voltage detection circuit, can conveniently monitor the working state of the device, improves the fault detection rate and increases the testability.

Drawings

The invention is further described with reference to the following figures and examples.

FIG. 1 is a schematic diagram of a universal interface device for RF terminals according to the present invention;

FIG. 2 is a schematic circuit diagram of the high speed data processing circuit of FIG. 1;

FIG. 3 is a schematic diagram of the clock circuit of FIG. 2;

FIG. 4 is a schematic diagram of the power supply circuit of FIG. 1;

FIG. 5 is a schematic diagram of the circuit for supplying power and interface signals to the FPGA of FIG. 1 via the rigid-flex board;

FIG. 6 is a schematic circuit diagram of the detection circuit of FIG. 1;

the technical scheme of the invention is further described in detail in the following with reference to the attached drawings.

Detailed Description

See fig. 1 and 2. In an exemplary preferred embodiment described below, a radio frequency terminal universal interface processing apparatus includes: the high-speed signal processing main board, the interface processing auxiliary board and the rigid-flex connecting board for connecting the high-speed signal processing main board and the interface processing auxiliary board provide a working power supply to complete a power supply circuit for supplying power to the main board; the method is characterized in that: the rigid-flex board is combined with the high-speed signal processing main board and the interface processing auxiliary board through the magnetic suction connector with the buckle to complete interface connection of the main board and the auxiliary board; the high-speed signal processing mainboard is provided with a high-speed data processing circuit and an interface processing subplate thereof, the high-speed data processing circuit is connected with a power supply circuit and a clock circuit, the clock circuit provides a mainboard working clock, the high-speed data processing circuit completes a real-time data processing function, the interface processing subplate completes module interface processing and state detection, and the high-speed interface conversion circuit, the low-speed interface conversion circuit and the detection circuit detect, wherein the high-speed interface conversion circuit and the low-speed interface conversion circuit complete various interface conversions of the module, and the detection circuit completes module working voltage and environment temperature monitoring and reports to the control terminal through the interface conversion circuit; the high-speed data processing circuit adopts a plug-in double-rate synchronous dynamic random access memory DDR, a field programmable gate array FPGA and a digital signal processor DSP of a plug-in synchronous dynamic random access memory SDRAM, an interactive architecture is connected through an external memory interface EMIF interface, the FPGA receives, analyzes and processes telemetering data, real-time processed data are sent to the DSP through the external memory interface EMIF, the data are returned to the FPGA through the EMIF after being processed, the FPGA controls and manages each interface, and simultaneously monitors and reports the working state of the radio frequency terminal.

The rigid-flex board is combined with the high-speed signal processing main board and the interface processing auxiliary board through the magnetic suction connector with the buckle, and the interface connection of the main board and the auxiliary board is mainly completed. The magnetic connector is realized by oppositely inserting two parts of a male head and a female head, wherein the male head is welded on a PCB (printed Circuit Board), the female head is welded on a rigid flexible board, the male head and the female head are butted through a contact pin jack, the periphery of the connector has a magnetic function, the connection reliability is enhanced, and the connector is finally reinforced through a buckle; similarly, the auxiliary board is also connected with the rigid-flex board by the same method, the rigid-flex connecting board mainly completes the connection of the working power supply of the auxiliary board and the required input and output signals, and the length of the connecting board is determined according to actual requirements. The connector and the rigid-flex board are convenient to replace after the connector and the rigid-flex board are connected, and the connection reliability is also guaranteed through the magnetic attraction and the buckle. The interface processing sub-board mainly completes high-speed interface conversion and low-speed interface conversion functions, wherein the high-speed interface covers an LVDS low-voltage differential signal interface, and the low-speed interface covers an intelligent terminal RS485/422, an LVTTL/TTL level signal interface and the like.

See fig. 3. Clock circuit is by crystal oscillator 25MH_ZAnd outputting the clock signal to the FPGA, and generating a DSP clock by the FPGA.

See fig. 4. The power circuit is realized by connecting two DC/DC buck type micro module voltage regulators LTM4644 and LTM4622 and 1 low dropout regulator LDO power chip SW1764 in parallel, the power input is 5.4V, five voltages of 5.0V, 3.3V, 1.8V, 1.2V and 1.0V are converted, and the five voltages are respectively used for supplying power to FPGA, DSP and other peripheral circuits.

See fig. 5. The power supply required by the interface processing auxiliary board is directly provided by the high-speed signal processing main board in a PCB wiring mode through the rigid-flex connecting board. The IO interface of the FPGA chip of the high-speed signal processing main board is connected to the interface processing auxiliary board through rigid flexible Printed Circuit Board (PCB) wiring, and then is correspondingly connected with the input interface of each conversion chip. The high-speed interface conversion circuit relates to an LVDS circuit, a low-voltage differential signal is realized through a GM8108 chip, signals with opposite polarities are transmitted on two lines used for differential transmission, and common-mode noise is uniformly superposed on the two signals, so that the communication distance and the signal quality of the LVDS are ensured; the LVDS signal transmission is carried out by a differential signal transmitter, a differential signal interconnection device and a differential signal receiver, a LVDS driver firstly converts a TTL/CMOS signal into a differential signal, the differential signal is transmitted to the LVDS receiver through a transmission medium (such as a copper wire, a PCB connecting wire and the like), and the LVDS receiver receives the signal and converts the TTL/CMOS signal into the TTL/CMOS signal. The differential signal transmitter converts the unbalanced TTL signal into the balanced LVDS signal, which may be implemented by an IC, for example: DS90C 031; the differential signal receiver converts the LVDS signal with balanced transmission into the TTL signal with unbalanced transmission, which can be implemented by an IC, such as: DS90C032, the differential signal interconnect comprising: connecting wires (cables or PCB traces), and terminals matching resistors. The LVDS output interface performs data transmission by differential, i.e., low voltage differential signaling, on two PCB traces or a pair of balanced cables with a very low voltage swing (about 350 mV). By adopting the LVDS output interface, signals can be transmitted at the speed of hundreds of Mbit/s on a differential PCB or a balanced cable, and low noise and low power consumption are realized due to the adoption of a low-voltage and low-current driving mode. The low-speed conversion interface part completes TTL and RS485/422 interface conversion through SN74LVC8T245PW and MAX3490, and a welding port is externally provided in a pad or connector mode.

See fig. 6. The detection circuit comprises a temperature detection and voltage detection circuit. The temperature detection is realized by a TMP423, and the temperature information is transmitted back to the FPGA through an I2C channel; the voltage detection is realized by MAX1290, the voltage detection can be carried out on the 5 paths of power supplies of the board, and the detection result is returned to the FPGA through a BPI interface.

While the foregoing is directed to the preferred embodiment for implementing a universal interface processing device, it is to be understood that the invention is not limited to the form disclosed herein, but is not intended to be exhaustive of other embodiments, and that various other combinations, modifications, and environments may be used, and changes may be made within the scope of the inventive concept as described herein, commensurate with the above teachings, or the skill or knowledge of the relevant art. And that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A radio frequency terminal universal interface processing device comprises: the high-speed signal processing main board, the interface processing auxiliary board and the rigid-flex connecting board for connecting the high-speed signal processing main board and the interface processing auxiliary board provide a working power supply to complete a power supply circuit for supplying power to the main board; the method is characterized in that: the rigid-flex board is combined with the high-speed signal processing main board and the interface processing auxiliary board through the magnetic suction connector with the buckle to complete interface connection of the main board and the auxiliary board; the high-speed signal processing mainboard is provided with a high-speed data processing circuit and an interface processing subplate thereof, the high-speed data processing circuit is connected with a power supply circuit and a clock circuit, the clock circuit provides a mainboard working clock, the high-speed data processing circuit completes a real-time data processing function, the interface processing subplate completes module interface processing and state detection, and the high-speed interface conversion circuit, the low-speed interface conversion circuit and the detection circuit detect, wherein the high-speed interface conversion circuit and the low-speed interface conversion circuit complete various interface conversions of the module, and the detection circuit completes module working voltage and environment temperature monitoring and reports to the control terminal through the interface conversion circuit; the high-speed data processing circuit adopts a plug-in double-rate synchronous dynamic random access memory DDR, a field programmable gate array FPGA and a digital signal processor DSP of a plug-in synchronous dynamic random access memory SDRAM, an interactive architecture is connected through an external memory interface EMIF interface, the FPGA receives, analyzes and processes telemetering data, real-time processed data are sent to the DSP through the external memory interface EMIF, the data are returned to the FPGA through the EMIF after being processed, the FPGA controls and manages each interface, and simultaneously monitors and reports the working state of the radio frequency terminal.

2. The radio frequency terminal universal interface processing apparatus according to claim 1, wherein: the connector is inhaled to magnetism is realized by public female two parts butt joint, and wherein public first welding is on mainboard printed circuit board PCB, and female welding is on the rigid flexible board, through the butt joint of contact pin jack between the public female, and the connector periphery has magnetism to inhale the function, strengthens the connection reliability, and finally consolidates through the buckle, and the subplate also adopts same method and rigid flexible board to link to each other.

3. The radio frequency terminal universal interface processing apparatus according to claim 2, wherein: the rigid-flexible connection board completes the auxiliary board working power supply and required input and output signals, and the interface processing auxiliary board completes the functions of high-speed interface conversion and low-speed interface conversion.

4. The radio frequency terminal universal interface processing apparatus according to claim 1, wherein: clock circuit is by crystal oscillator 25MH_ZAnd outputting the clock signal to the FPGA, and generating a DSP clock by the FPGA.

5. The radio frequency terminal universal interface processing apparatus according to claim 1, wherein: the power circuit is realized by connecting two DC/DC buck type micro module voltage regulators LTM4644 and LTM4622 and 1 low dropout regulator LDO power chip SW1764 in parallel, the power input is 5.4V, five voltages of 5.0V, 3.3V, 1.8V, 1.2V and 1.0V are converted, and the five voltages are respectively used for supplying power to FPGA, DSP and other peripheral circuits.

6. The radio frequency terminal universal interface processing apparatus according to claim 1, wherein: the IO interface of the FPGA chip of the high-speed signal processing main board is connected to the interface processing auxiliary board through rigid flexible Printed Circuit Board (PCB) wiring, and then is correspondingly connected with the input interface of each conversion chip.

7. The radio frequency terminal universal interface processing apparatus according to claim 1, wherein: the high-speed interface conversion circuit relates to an LVDS circuit, a low-voltage differential signal is realized through a GM8108 chip, signals with opposite polarities are transmitted on two lines used for differential transmission, common-mode noise is uniformly superposed on the two signals, and the communication distance and the signal quality of the LVDS are ensured.

8. The radio frequency terminal universal interface processing apparatus according to claim 2, wherein: the low-speed conversion interface completes TTL and RS485/422 interface conversion through SN74LVC8T245PW and MAX3490, and a welding port is externally provided in a pad or connector mode.

9. The radio frequency terminal universal interface processing apparatus according to claim 1, wherein: the detection circuit comprises a temperature detection circuit and a voltage detection circuit, wherein the temperature detection is realized by a TMP423, and temperature information is transmitted back to the FPGA through an I2C channel; the voltage detection is realized by MAX1290, the voltage detection is carried out on the 5 paths of power supplies of the board, and the detection result is returned to the FPGA through a BPI interface.

10. The radio frequency terminal universal interface processing apparatus according to claim 1, wherein: the LVDS signal transmission is carried out by a differential signal transmitter, a differential signal interconnector and a differential signal receiver, a LVDS driver firstly converts a TTL/CMOS signal into a differential signal, the differential signal is transmitted to the LVDS receiver through a transmission medium, the LVDS receiver receives the signal and converts the TTL/CMOS signal into a TTL/CMOS signal, and the differential signal transmitter converts a TTL signal which is transmitted in an unbalanced mode into an LVDS signal which is transmitted in a balanced mode; the differential signal receiver converts the LVDS signals transmitted in a balanced mode into TTL signals transmitted in an unbalanced mode.