CN207884602U - The processing board of transmitting is received and processed for signal - Google Patents

Abstract

The utility model discloses the processing boards that transmitting is received and processed for signal, including signal acquisition playback plate and digital signal panel；The signal acquisition playback plate includes 8 road AD acquisition modules, 2 road frequency agility RF receiving and transmission modules, clock circuit；The signal acquisition playback plate is connect using FMC connectors with digital signal panel；The A/D acquisitions, array received processing, integrated navigation reception that transceiver processing board mainly completes array signal are handled, transmitting signal generates and monitoring information transmitting and receiving service, FMC subcard structures are used by ADC, it arranges in pairs or groups and uses with the digital signal panel of FMC interfaces, data exchange includes between plate：AD acquisition modules include 16 pairs of high speed serialization LVDS bus transfer adc datas in total；The two panels chip of frequency agility RF receiving and transmission module includes 24 pairs of high speed serialization LVDS signal transmission ADC and DAC data in total, and realization has 8 channels and fixes frequency point array signal A/D acquisitions and receive processing capacity, has 2 channel frequency agility signal transmitting and receiving processing capacities.

Description

The processing board of transmitting is received and processed for signal

Technical field

The utility model is related to transceivers to handle board, and in particular to the processing board of transmitting is received and processed for signal Card.

Background technology

With the development and progress of electronic technology, the generally use of various electronic instruments and equipment, for electronic signal It is required that higher and higher, the reception and transmitting of signal are played a crucial role in electronic communication field, improve the transmission of signal Rate, increases the data processing of signal transceiver, needs more functions in use to meet R＆D and production needs.

Existing electronic instrument and equipment have the function of telecommunication, are substantially through transmitting antenna and reception antenna Collective effect, signal emitted and received to realize the transmission of information and data, but with data-handling capacity Transceiver plate is not yet.

Utility model content

The processing board for receiving and processing transmitting for signal is provided, has 8 channels and fixes the A/D acquisitions of frequency point array signal With reception processing capacity, have 2 channel frequency agility signal transmitting and receiving processing capacities.

The utility model is achieved through the following technical solutions：

The processing board of transmitting, including signal acquisition playback plate and Digital Signal Processing are received and processed for signal Plate；The signal acquisition playback plate includes 8 road AD acquisition modules, 2 road frequency agility RF receiving and transmission modules, clock circuit；The letter Number acquisition playback plate connect with digital signal panel using FMC connectors.The versatility for considering board uses FMC by ADC The collocation of the digital signal panel of subcard structure and FMC interfaces uses, and data exchange includes between plate：AD acquisition modules wrap in total 16 pairs of high speed serialization LVDS bus transfer adc datas, 4 pairs of LVDS clocks and SPI and control IO are included, wherein in order to ensure two panels The synchronization of the acquisition signal of AD acquisition module chips, LVDS data and clock will be put on the same FPGA_bank；Frequency agility is penetrated The two panels chip of frequency transceiver module includes 24 pairs of high speed serialization LVDS signal transmission ADC and DAC data in total, in total 16 controls IO processed, two groups of CLK and SPI controlling bus guide to FMC connectors, and wherein LVDS high-speed serial signals and clock will be put into same A FPGA_bank；Realization has 8 channels and fixes frequency point array signal A/D acquisitions and receive processing capacity, has 2 channel agiles Frequency signal transmitting and receiving processing capacity.

Further, AD acquisition chips select AD9653BCPZ-125.AD9653 is a 4 channel, 16,125MSPS Analog-digital converter (ADC), sampling hold circuit in built-in piece, sets specifically for low cost, low-power consumption, small size and ease for use Meter；The conversion rate of the product reaches as high as 125MSPS, has outstanding dynamic property and low power consumption characteristic, to small package ruler Very little application is meaningful, which requires using the power supply of 1.8V single supplies and LVPECL/CMOS/LVDS compatible types sampling speed Rate clock signal, to give full play to its working performance；For most of applications, it is not necessarily to external reference-voltage source or driving Device.

Further, frequency agility transceiving chip selects two panels AD9364BBCZ.AD9364 be 1 channel high-performance of a 1x, High integration RF agile transceivers；The programmability and broadband ability of the device become the ideal choosing of a variety of transceiver applications It selects；The device integrates the front ends RF and flexible mixed signal baseband part, integrates frequency synthesizer, being provided for processor can Digital interface is configured, is imported to simplify design；AD9364 operating frequency ranges are 70MHz to 6.0GHz, cover most of spy Perhaps license and unlicensed band, the bandwidth chahnel ranging from 200kHz of support is with down toward 56MHz.

Further, digital signal panel uses the framework of DSP+FPGA, DSP to use TMS320C6455BZTZA processing Device, FPGA use XC7VX485T-2FFG1157.The I/O signal of XC7VX485T-2FFG1157 has 600 I/O signals, 20 pairs Serdes high speed transmitting-receiving universal serial bus, the signal of comprehensive whole plate, the I/O signal being connect with DSP is no more than 100, removing and FMC The signal of playback card connection is acquired, other all I/O interface signal statistics are no more than 150, and therefore, the IO and FMC of FPGA connect No less than 350 are connect, the general purpose I/O bus of practical FMC is no more than 200, and FPGA can draw the I/O port of FMC full, it is contemplated that logical With property, all I/O ports are all made of LVDS difference cablings；Both it can be used for LVDS high-speed serial bus, and can be used for single-ended control Signal processed.

The utility model compared with prior art, has the following advantages and advantages：

1, the utility model receives and processes the processing board of transmitting for signal, and FMC subcard structures are used by ADC, It arranges in pairs or groups and uses with the digital signal panel of FMC interfaces, data exchange includes between plate：AD acquisition modules include 16 pairs of high speeds in total Serial LVDS bus transfer adc datas, 4 pairs of LVDS clocks and SPI and control IO, wherein in order to ensure two panels AD acquisition modules The synchronization of the acquisition signal of chip, LVDS data and clock will be put on the same FPGA_bank；Frequency agility RF receiving and transmission module Two panels chip include 24 pairs of high speed serialization LVDS signal transmission ADC and DAC data in total, in total 16 control IO, two groups CLK and SPI controlling bus guides to FMC connectors, and wherein LVDS high-speed serial signals and clock will be put into the same FPGA_ bank；Realization has 8 channels and fixes frequency point array signal A/D acquisitions and receive processing capacity, has 2 channel frequency agility signals and receives Send out processing capacity；

2, the utility model receives and processes the processing board of transmitting for signal, AD9653 be a 4 channel, 16, 125MSPS analog-digital converters (ADC), sampling hold circuit in built-in piece, specifically for low cost, low-power consumption, small size and easily It is designed with property；The conversion rate of the product reaches as high as 125MSPS, has outstanding dynamic property and low power consumption characteristic, right The application of small package size is meaningful, which requires using the power supply of 1.8V single supplies and LVPECL/CMOS/LVDS compatibilities Type sample rate clock signal, to give full play to its working performance；For most of applications, it is not necessarily to external reference voltages Source or driving element；

3, the utility model receives and processes the processing board of transmitting for signal, and AD9364 is the high property in a channels 1x1 Energy, high integration RF agile transceivers；The programmability and broadband ability of the device become the reason of a variety of transceiver applications Want to select；The device integrates the front ends RF and flexible mixed signal baseband part, integrates frequency synthesizer, is carried for processor For can configure digital interface, imported to simplify design；AD9364 operating frequency ranges are 70MHz to 6.0GHz, cover big portion Divide charter and unlicensed band, the bandwidth chahnel ranging from 200kHz of support is with down toward 56MHz.

Description of the drawings

Attached drawing described herein is used for providing further understanding the utility model embodiment, constitutes the one of the application Part does not constitute the restriction to the utility model embodiment.In the accompanying drawings：

Fig. 1 is the utility model main assembly block diagram.

Specific implementation mode

To make the purpose of this utility model, technical solution and advantage be more clearly understood, with reference to embodiment and attached drawing, The utility model is described in further detail, and the exemplary embodiment and its explanation of the utility model are only used for explaining this Utility model is not intended to limit the scope of the present invention.

Embodiment

As shown in Figure 1, the utility model receives and processes the processing board of transmitting, including signal acquisition playback for signal Plate and digital signal panel；The signal acquisition playback plate includes 8 road AD acquisition modules, 2 road frequency agility radio-frequency receiving-transmitting moulds Block, clock circuit；The signal acquisition playback plate is connect using FMC connectors with digital signal panel；AD acquisition module cores Piece uses AD9653BCPZ-125；Frequency agility transceiving chip selects two panels AD9364BBCZ；Digital signal panel uses DSP+ The framework of FPGA, DSP use TMS320C6455BZTZA processors, FPGA to use XC7VX485T-2FFG1157.When implementation, receive The integrated board of hair plays back plate by signal acquisition and digital signal panel forms, and overall dimension is no more than 135 × 135 × 40mm, due to entire transceiving integrated board J30J connectors to be mounted, the interfaces such as LED etc., RJ45 are all to be put into digital letter In number processing board, then the position that reserve above-mentioned connector will be snapped on digital signal panel by acquiring playback board size； Digital Signal Processing card is according to 135 × 135mm full scale designs, and signal acquisition playback card is then necessarily less than the size, tentatively It is set to 115 × 115mm；Entire transceiving integrated board height is designed according to no more than 40mm；When implementation, whole plate Power Management Design, Subcard power supply is by DC-DC power supplies on plate, and support plate provides 5V power supplies and IO accessory power supplys, and according to data, AD9653 needs to power Respectively+1.8VA ,+1.8VD ,+1.3VREF, monolithic maximum power dissipation 708mW；It is respectively+1.3V, auxiliary that AD9364, which needs to power, DAC voltage 3.3V ,+1.0VREF reference voltage, 1.8V maximum currents are no more than 330mA, and+3.3V maximum currents are no more than； It is+3.3V that AD9522, which mainly powers, and maximum power dissipation is no more than 1.3W, to ensure good power supply noise performance, improves ADC acquisitions SNR, power supply first lowered voltage using switch, all uses the voltage that LDO is converted to each chip power supply later.

Above-described specific implementation mode, to the purpose of this utility model, technical solution and advantageous effect carried out into One step is described in detail, it should be understood that the foregoing is merely specific embodiment of the present utility model, is not used to limit Determine the scope of protection of the utility model, within the spirit and principle of the utility model, any modification for being made equally is replaced It changes, improve, should be included within the scope of protection of this utility model.

Claims (4)

1. receiving and processing the processing board of transmitting for signal, which is characterized in that play back plate and number including signal acquisition Signal-processing board；The signal acquisition playback plate includes 8 road AD acquisition modules, 2 road frequency agility RF receiving and transmission modules, clock electricity Road；The signal acquisition playback plate is connect using FMC connectors with digital signal panel.

2. the processing board according to claim 1 for receiving and processing transmitting for signal, which is characterized in that the AD is adopted Collect module chip and uses AD9653BCPZ-125.

3. the processing board according to claim 1 for receiving and processing transmitting for signal, which is characterized in that the agile Frequency transceiving chip selects two panels AD9364BBCZ.

4. the processing board according to claim 1 for receiving and processing transmitting for signal, which is characterized in that the number Signal-processing board uses the framework of DSP+FPGA, DSP that TMS320C6455BZTZA processors, FPGA is used to use XC7VX485T- 2FFG1157。