CN115022148A

CN115022148A - Four-channel single-bit frequency measurement system and method

Info

Publication number: CN115022148A
Application number: CN202210698014.XA
Authority: CN
Inventors: 陈军; 黄一平; 伍平
Original assignee: Chengdu Fuyuanchen Technology Co ltd
Current assignee: Chengdu Fuyuanchen Technology Co ltd
Priority date: 2022-06-20
Filing date: 2022-06-20
Publication date: 2022-09-06
Anticipated expiration: 2042-06-20
Also published as: CN115022148B

Abstract

The invention discloses a four-channel single-bit frequency measurement system and a four-channel single-bit frequency measurement method, which comprise a radio frequency front-end module, a four-channel single-bit instantaneous measurement module, a comprehensive processing module and a correction source, wherein the radio frequency front-end module receives four paths of radio frequency signals, outputs the signals to the four-channel single-bit instantaneous measurement module after filtering, amplifying and balancing, completes high-speed single-bit processing in four paths of 2 GHz-18 GHz frequency bands by the four-channel single-bit instantaneous measurement module, outputs PDW information containing frequency, amplitude, phase and pulse width to the comprehensive processing module, and the correction source module is used for carrying out phase correction on a plurality of powered channels. The invention can simultaneously carry out signal detection, digital acquisition and parameter measurement on 4 paths of intermediate frequency signals output by the microwave front-end module.

Description

Four-channel single-bit frequency measurement system and method

Technical Field

The invention relates to the field of radio frequency of four-channel single-bit frequency measurement, in particular to a four-channel single-bit frequency measurement system and a four-channel single-bit frequency measurement method.

Background

With the development of communication technology, in order to realize the purpose of rapid signal measurement, frequency conversion processing of multiple signals is generally required to be realized simultaneously, and after a frequency converter has a mode of converting a single channel into multiple channels, frequency conversion equipment is required to be optimally designed in order to overcome the problems of complex wiring of multiple channels and signal interference of each channel, so as to meet the use requirement.

Disclosure of Invention

In view of the above problems, the present invention provides a four-channel single-bit frequency measurement system and method.

The invention is realized by the following technical scheme:

a four-channel single-bit frequency measurement system comprises a radio frequency front-end module, a four-channel single-bit instantaneous measurement module, a comprehensive processing module and a correction source, wherein the radio frequency front-end module receives four channels of radio frequency signals, outputs the signals to the four-channel single-bit instantaneous measurement module after filtering, amplifying and balancing, the four-channel single-bit instantaneous measurement module completes high-speed single-bit processing in four channels of 2 GHz-18 GHz frequency bands, and outputs PDW information containing frequency, amplitude, phase and pulse width to the comprehensive processing module, and the correction source module is used for carrying out phase correction on a plurality of channels after power is on.

Furthermore, the radio frequency front-end module comprises four paths of microwave front-end units, the microwave front-end units are respectively connected with input radio frequencies in 2 GHz-18 GHz frequency bands, and four paths of output radio frequencies in 2 GHz-10 GHz frequency bands are output to the four-channel single-bit transient measurement module through processing.

Further, the microwave front-end unit includes a first power divider, a second power divider, a third power divider, a first filter amplifier, a second filter amplifier, a third filter amplifier, a fourth filter amplifier, a mixer, a first SDLVA, and a second SDLVA, an input end of the first power divider is connected to one path of microwave input radio frequency, an output end of the first power divider is respectively connected to an input end of the first filter amplifier and an input end of the second filter amplifier, an input end of the second power divider is connected to an output end of the first filter amplifier, an output end of the second power divider is respectively connected to an input end of the third filter amplifier and an input end of the first SDLVA, an input end of the third power divider is connected to an output end of the second filter amplifier, an output end of the third power divider is respectively connected to an input end of the second SDLVA and an input end of the mixer, and an output end of the mixer is connected to an input end of the fourth filter amplifier, and the input ends of the third filter amplifier, the fourth filter amplifier, the first SDLVA and the second SDLVA are respectively connected with a four-channel single-bit transient test module.

Furthermore, the four-channel single-bit transient measurement module comprises eight paths of single-bit mADCs, an FPGA chip, a video ADC and a power supply, wherein the FPGA chip is respectively connected with eight single-bit ADCs, the video ADC and the power supply, four paths of radio frequency outputs output by the radio frequency front-end module are respectively connected with the FPGA chip, the single-bit mADCs are used for completing single-bit quantization of 25Gsps sampling rate and inputting the obtained data to the FPGA chip, and the calculation result obtained by the FPGA chip is transmitted to the outside through an SRIO/LVDS bus.

Furthermore, an interferometer direction finding and amplitude comparison direction finding processing algorithm is integrated in the FPGA chip, and the FPGA chip switches an interferometer direction finding working mode and an amplitude comparison direction finding working mode by receiving a software control command mode.

A four-channel single-bit frequency measurement method comprises the following steps: the 4 paths of radio frequency signals are filtered, amplified and balanced by the radio frequency front-end module, then output to the four-channel single-bit transient measurement module, high-speed single-bit processing in four paths of 2 GHz-18 GHz frequency bands is completed, and PDW information containing frequency, amplitude, phase and pulse width is output to the comprehensive processing module.

Furthermore, the multi-path parallel single-bit mADC realizes homology in a way of sharing a reference in the digital part.

Further, the PDW information processing performed by the integrated processing module specifically includes the following operation modes:

A. interferometer direction finding mode;

B. comparing the amplitude and the direction;

and the interferometer direction finding mode and the amplitude comparison direction finding mode are controlled and switched by an FPGA chip in the comprehensive processing module respectively.

Further, the internal signal processing flow in the interferometer mode is as follows:

A01. collecting 4 paths of intermediate frequency signals, wherein the 4 paths of intermediate frequency signals comprise a path of detection channel AD1 and three paths of phase detection channels AD2, AD3 and AD 4;

A02. performing FFT operation on the AD1, and performing peak searching detection to obtain the frequency code and the phase of the AD 1;

A04. AD1 frequency code guide AD2, AD3 and AD4 channels, and phase discrimination processing is carried out through DFT to obtain the phases of AD2, AD3 and AD4 channels;

A05. PDW is output after the AD1 channel detection pulse, and contains phase information of AD1, AD2, AD3 and AD 4. Further, the internal signal processing flow of the amplitude-versus-direction mode is as follows:

B01. collecting 4 paths of intermediate frequency signals, wherein the signals comprise four paths of detection channels AD1-AD 4;

B02. performing FFT operation on AD1-AD4, and performing peak searching detection to obtain frequency codes and detection pulse signals of AD1-AD 4;

B03. the SDLVA signals of AD1-AD4 are aligned with the width-preserving signal in time domain;

B04. and 4 PDWs are output after the detection pulse, and contain AD1-AD4 amplitude information.

The invention has the beneficial effects that:

(1) the invention can simultaneously carry out signal detection, digital acquisition and parameter measurement on 4 paths of intermediate frequency signals output by the microwave front-end module;

(2) the invention can output 4 paths of PDW parameters including (frequency, pulse width, amplitude and phase);

(3) the invention can adapt to complex electromagnetic environment;

(4) when the invention reaches two signals at the same time, the information of one signal can be correctly given;

(5) when continuous waves exist, the method can identify and report the continuous waves;

(6) the invention can adapt to the linear frequency modulation signal with large slope, and ensure the synchronization of frequency and phase.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required to be used in the description of the embodiments will be briefly introduced below, and it is apparent that the drawings in the description below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings may be obtained according to the drawings without inventive labor.

Fig. 1 is a schematic position diagram of a four-channel single-bit frequency measurement module of a four-channel single-bit frequency measurement system according to an embodiment of the present invention;

fig. 2 is a schematic diagram of the overall hardware components of a rf front-end module of a four-channel single-bit frequency measurement system according to an embodiment of the present invention;

fig. 3 is a schematic diagram of the overall hardware composition of a four-channel single-bit transient measurement module of a four-channel single-bit frequency measurement system according to an embodiment of the present invention;

FIG. 4 is a block diagram of a digital processing circuit of a four-channel single-bit frequency measurement system according to an embodiment of the present invention;

fig. 5 is a block diagram of the internal components of the ADS5271 of a four-channel single-bit frequency measurement system according to an embodiment of the present invention;

FIG. 6 is a diagram of the internal layout of a digital circuit of a four-channel single-bit frequency measurement system according to an embodiment of the present invention;

FIG. 7 is a flowchart of a processing procedure in a direction-finding mode of an interferometer of a four-channel single-bit frequency-measuring system according to an embodiment of the present invention;

fig. 8 is a flowchart of processing in the amplitude direction finding mode of the four-channel single-bit frequency measuring system according to the embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to examples and accompanying drawings, and the exemplary embodiments and descriptions thereof are only used for explaining the present invention and are not meant to limit the present invention.

Example 1

As shown in fig. 1, this embodiment provides a four-channel single-bit frequency measurement system, which includes a radio frequency front end module, a four-channel single-bit transient measurement module, an integrated processing module, and a calibration source, where the radio frequency front end module receives four channels of radio frequency signals, and outputs the signals to the four-channel single-bit transient measurement module after filtering, amplifying, and equalizing, the four-channel single-bit transient measurement module completes high-speed single-bit processing in four channels of 2GHz to 18GHz frequency bands, and outputs PDW information including frequency, amplitude, phase, and pulse width to the integrated processing module, and the calibration source module is configured to perform phase calibration on multiple channels after power-on.

Further, the microwave front-end unit includes a first power divider, a second power divider, a third power divider, a first filter amplifier, a second filter amplifier, a third filter amplifier, a fourth filter amplifier, a mixer, a first SDLVA and a second SDLVA, an input end of the first power divider is connected to one path of microwave input radio frequency, an output end of the first power divider is respectively connected to an input end of the first filter amplifier and an input end of the second filter amplifier, an input end of the second power divider is connected to an output end of the first filter amplifier, an output end of the second power divider is respectively connected to an input end of the third filter amplifier and an input end of the first SDLVA, an input end of the third power divider is connected to an output end of the second filter amplifier, an output end of the third power divider is respectively connected to an input end of the second SDLVA and an input end of the mixer, an output end of the mixer is connected to an input end of the fourth filter amplifier, and the input ends of the third filter amplifier, the fourth filter amplifier, the first SDLVA and the second SDLVA are respectively connected with a four-channel single-bit transient test module.

Specifically, the specific implementation principle flow of this embodiment is as follows:

the index parameters of this example are as follows:

a) inputting a radio frequency:

1) the number of radio frequency paths: 4 ways.

2) Frequency range: 2GHz to 18 GHz.

3) Power range: -60dBm to +10 dBm.

Sensitivity (front end test, front end radio frequency gain 15dB, flatness less than or equal to 6dB, noise coefficient less than or equal to 6 dB):

1) PW > 250 ns: better than-72 dBm.

2) PW is less than or equal to 100ns and less than or equal to 250 ns: better than-65 dBm.

b) Single signal dynamic range: is more than or equal to 72dB (-72 dBm-0 dBm).

c) Adaptation signal form: conventional pulsing, pulse compression, pulse doppler, frequency chopping, continuous wave (when the signal pulse width is greater than 500 mus, it is judged to be continuous wave, giving a continuous wave signature), etc.

d) Frequency measurement precision:

1)PW＞250ns：1MHz（r.m.s）。

2)250ns< PW≤500ns ：(r.m.s）。

3)100ns≤PW≤250ns：3MHz（r.m.s）。

e) amplitude measurement accuracy: is better than 1dB (r.m.s) (the linear dynamic range of amplitude is more than or equal to 50 dB).

f) Phase discrimination accuracy: is less than or equal to 10 degrees (r.m.s) (tested by 8dB above the sensitivity).

g) Measuring time: less than or equal to 800 ns.

h) Adapting the pulse width of the signal: 100 ns-1 ms, CW.

i) Digital width protection:

earlier than the frequency code by not less than 20ns, the rising edge of the pulse signal is less than or equal to 10ns, and the falling edge is less than or equal to 20 ns;

width maintaining precision: the signal range of 0.1-2 mus is plus or minus 0.1 mus, and the wide pulse width range of more than 2 mus is plus or minus (0.1 mus +0.01 PW).

j) The adaptation period range is as follows: CW for 1 μ s to 5 ms.

k) Volume: a standard ASSAC module (233 mm by 160mm by 24 mm).

The principle of the present embodiment is as follows:

according to the mature design experience of the transient measurement module based on the single bit system and the verification result of the stability of the multichannel phase, the hardware scale and the realizability are considered, and according to the technical index requirements of the scheme, the hardware overall composition schematic diagram of the module is shown in fig. 2 and fig. 3. Inputting four paths of 2 GHz-18 GHz radio frequency signals, dividing each path into two sections according to 2 GHz-10 GHz and 10 GHz-18 GHz, wherein the frequency of 10 GHz-18 GHz is changed to 2 GHz-10 GHz, entering a digital processing part, completing high-speed single-bit quantization and processing in the digital processing part, and outputting the obtained result through an LRM seat sub-interface.

The multi-path parallel single-bit ADC in the digital part realizes homology in a common reference mode, and is used for guaranteeing phase consistency among a plurality of channels.

Example 2

On the basis of embodiment 1, this embodiment further proposes a hardware functional component of the digital circuit of the above embodiment, which is specifically as follows:

the hardware functional composition block diagram of the digital circuit is shown in fig. 4. And receiving 8 paths of 2 GHz-10 GHz intermediate frequency signals, respectively completing ultrahigh-speed single-bit acquisition and quantization, sending the signals into an FPGA for digital signal processing, receiving 8 paths of video signals, completing quantization, sending the signals into the FPGA, and outputting the fused final results.

The circuit mainly comprises eight paths of single-bit mADCs, a main processing FPGA (XCKU 115), a video ADC (8-channel ADS 5271), a clock PLL circuit and the like. The single-bit mADC finishes single-bit quantization of 25Gsps sampling rate, obtained data are input into the FPGA, and a calculation result obtained by the FPGA is transmitted to the outside through an SRIO bus or an LVDS bus.

The index parameters of the digital part scheme are as follows:

a) inputting an intermediate frequency:

the number of paths: 8 paths of the reaction solution;

frequency range: 2G to 10 GHz;

power range: -10dBm to +10 dBm;

input of VSWR: less than or equal to 2 dB.

b) Single bit mADC quantization:

sampling rate: not less than 22 Gsps;

quantization bit number: 1 bit;

quantization minimum input power: less than or equal to-12 dBm;

wide radio frequency band: 2 GHz-10 GHz.

c) Video ADC quantization:

the number of paths: 8-path;

sampling rate: not less than 40 Msps;

quantization bit number: 12 bits;

input voltage range: 0.2V-3V;

frequency range: DC is 20 MHz.

d) J30J debugging interface, LED pilot lamp, interface meet the requirements.

Example 3

On the basis of embodiment 1, this embodiment further proposes a detailed design of the key circuit of the above embodiment, which is specifically as follows:

(1) FPGA circuit

According to the basic composition of the digital circuit, 8-path MonoFFT signal processing needs to be completed, the FPGA resource requirement is large, according to the resource requirement FPGA chip model selection, XCKU115-2FLVA1517I in KU series FPGA of XILINX company is adopted, the internal resource mainly comprises 693,120 logic units and 5520 DSP modules, and the DSP module processing capacity is 5,335 GMAC/s and 75.9Mb BLOCK RAM. The main peripheral design is as follows:

a) the XCKU115-2FLVA1517I externally expands 2GB DDR3 SDRAM, and the highest read-write speed can reach 1600 MT/s;

b) XCKU115-2FLVA1517I adopts 16-bit 1Gb BPI FLASH, and the program loading time is less than or equal to 1 s;

c) and (3) optical fiber interface: 1 path of QSFP optical fiber interface is realized;

d) a network port: 1-path 1000M network port is realized;

e) RS232 bus: 2 paths of RS232 buses are realized in total and used for debugging, and an RS232 interface is led out through a contact pin;

(2) high speed single bit quantization

The high-speed single-bit quantization chip is realized by selecting a certain high-speed single-bit ADC, and the main technical performance of the single-bit ADC is as follows:

a) the process type is as follows: GaAs;

b) the speed reduction ratio is as follows: 1: 16;

c) signal bandwidth: 14 GHz;

d) sampling rate: 25 Gsps;

e) input sensitivity: -25dBm- +8 dBm;

f) output level: LVDS;

g) packaging: CQFP 64;

h) the size of the base: 10.2 mmX10.2mm.

The chip adopts a GaAs process, and can output 16 paths of LVDS low-speed digital signals from 1 path of high-frequency analog signals at a 1:16 speed reduction ratio. The outputs provide divide-by-8 and divide-by-16 clocks for data synchronization. The sampling rate can reach 25Gsps, and the dynamic range of data signal input reaches 33dBc (-25 dBm to +8 dBm), so that the method is suitable for the speed reduction processing and the digital receiving front end of high-speed data signals.

(3) Video quantization

The video quantization is realized by selecting a multi-channel video ADC, the chip type is ADS5271, and the internal components are shown in FIG. 5. ADS5271 is a high performance, 50MSPS, 8-channel analog-to-digital converter (ADC). The main technical indexes are as follows:

a) maximum sampling rate: 50 MSPS;

b) a 12-bit resolution;

c) total power consumption: inner reference 927 mW/outer reference 861 mW;

d) a CMOS process;

e) the signal-to-noise ratio of 70.5dB can be achieved under the condition of 10MHz radio frequency signal input.

(4) Circuit layout

The internal layout of the digital circuit portion and the allocation of the main structure according to the inside of the module are shown in fig. 6. The sampling rate of 25Gsps makes the traces of the clock and signal distribution paths no longer able to be handled by the lumped parameter circuit method, but should take into account their transmission line effects, the interference of the clock and signal distribution circuits with each other and with other on-chip critical signal paths, i.e., signal integrity issues. The ultra-high speed sampling technology must be carried out on the premise of effective electromagnetic simulation and actual measurement data combined simulation analysis.

Example 4

On the basis of embodiment 1, this embodiment further provides a four-channel single-bit frequency measurement method, including the following steps: the 4 paths of radio frequency signals are filtered, amplified and balanced by the radio frequency front-end module, then output to the four-channel single-bit transient measurement module, high-speed single-bit processing in four paths of 2 GHz-18 GHz frequency bands is completed, and PDW information containing frequency, amplitude, phase and pulse width is output to the comprehensive processing module.

Further, the multi-path parallel single-bit mADC realizes homology in a digital part by means of a common reference mode.

A. interferometer direction finding mode;

B. comparing the amplitude and the direction;

The working mode and the process of the embodiment are designed as follows:

the module has two working modes, namely an interferometer direction finding mode and a amplitude comparison direction finding mode. The two working modes are switched to work by issuing a software control command mode.

The schematic flow chart of the internal signal processing in the direction finding mode of the interferometer is shown in fig. 7.

In the amplitude-versus-direction mode, the internal processing flow is shown in fig. 8.

And processing algorithms of direction finding and amplitude comparison direction finding of the interferometer are integrated in the FPGA.

The foregoing shows and describes the general principles and broad features of the present invention and advantages thereof. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are described in the specification and illustrated only to illustrate the principle of the present invention, but that various changes and modifications may be made therein without departing from the spirit and scope of the present invention, which fall within the scope of the invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims

1. A four-channel single-bit frequency measurement system is characterized by comprising a radio frequency front-end module, a four-channel single-bit instantaneous measurement module, a comprehensive processing module and a correction source, wherein the radio frequency front-end module receives four paths of radio frequency signals, outputs the signals to the four-channel single-bit instantaneous measurement module after filtering, amplifying and balancing, completes high-speed single-bit processing in four paths of 2 GHz-18 GHz frequency bands by the four-channel single-bit instantaneous measurement module, outputs PDW information containing frequency, amplitude, phase and pulse width to the comprehensive processing module, and the correction source module is used for carrying out phase correction on a plurality of powered-on channels.

2. The four-channel single-bit frequency measurement system according to claim 1, wherein the radio frequency front-end module comprises four microwave front-end units, the microwave front-end units are respectively connected with input radio frequencies in 2 GHz-18 GHz bands, and output four output radio frequencies in 2 GHz-10 GHz bands to the four-channel single-bit transient measurement module through processing.

3. The four-channel single-bit frequency measurement system according to claim 2, wherein the microwave front-end unit includes a first power divider, a second power divider, a third power divider, a first filter amplifier, a second filter amplifier, a third filter amplifier, a fourth filter amplifier, a mixer, a first SDLVA and a second SDLVA, an input end of the first power divider is connected to one path of microwave input radio frequency, an output end of the first power divider is respectively connected to an input end of the first filter amplifier and an input end of the second filter amplifier, an input end of the second power divider is connected to an output end of the first filter amplifier, an output end of the second power divider is respectively connected to an input end of the third filter amplifier and an input end of the first SDLVA, an input end of the third power divider is connected to an output end of the second filter amplifier, and an output end of the third power divider is respectively connected to an input end of the second SDLVA and an input end of the mixer, the output end of the mixer is connected with the input end of a fourth filter amplifier, and the input ends of the third filter amplifier, the fourth filter amplifier, the first SDLVA and the second SDLVA are respectively connected with a four-channel single-bit transient measurement module.

4. The four-channel single-bit frequency measurement system according to claim 1, wherein the four-channel single-bit instantaneous measurement module comprises eight paths of single-bit mADCs, an FPGA chip, a video ADC and a power supply, the FPGA chip is respectively connected with eight pieces of single-bit ADCs, the video ADC and the power supply, four paths of radio frequency outputs output by the radio frequency front end module are respectively connected with the FPGA chip, the single-bit mADCs are used for completing single-bit quantization of 25 Gbps sampling rate and inputting the obtained data to the FPGA chip, and the calculation result obtained by the FPGA chip is transmitted to the outside through an SRIO/LVDS bus.

5. The four-channel single-bit frequency measurement system according to claim 4, wherein processing algorithms for interferometer direction finding and amplitude comparison direction finding are integrated in the FPGA chip, and the FPGA chip switches between an interferometer direction finding working mode and an amplitude comparison direction finding working mode by receiving a software control command mode.

6. A four-channel single-bit frequency measurement method is characterized by comprising the following steps: the 4 paths of radio frequency signals are filtered, amplified and balanced by the radio frequency front-end module, then output to the four-channel single-bit transient measurement module, high-speed single-bit processing in four paths of 2 GHz-18 GHz frequency bands is completed, and PDW information containing frequency, amplitude, phase and pulse width is output to the comprehensive processing module.

7. The method of claim 6, wherein the multiple parallel single-bit mADC in the digital portion implement homology by way of a common reference.

8. The method according to claim 6, wherein the processing of the PDW information by the integrated processing module specifically includes the following operation modes:

interferometer direction finding mode;

comparing the amplitude and the direction;

9. The method according to claim 8, wherein the signal processing procedure in the interferometer mode is as follows:

A05. PDW is output after the AD1 channel detection pulse, and contains phase information of AD1, AD2, AD3 and AD 4.

10. The four-channel single-bit frequency measurement method according to claim 8, wherein the internal signal processing flow of the amplitude direction measurement mode is as follows: