CN106383338A - Multichannel radar signal acquisition device based on digital channelization - Google Patents
Multichannel radar signal acquisition device based on digital channelization Download PDFInfo
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- CN106383338A CN106383338A CN201611009563.2A CN201611009563A CN106383338A CN 106383338 A CN106383338 A CN 106383338A CN 201611009563 A CN201611009563 A CN 201611009563A CN 106383338 A CN106383338 A CN 106383338A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/28—Details of pulse systems
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- Radar Systems Or Details Thereof (AREA)
Abstract
The invention discloses a multichannel radar signal acquisition device based on digital channelization, wherein the device relates to the field of radar signal acquisition technology. The multichannel radar signal acquisition device settles a defect of no multichannel synchronous digital channelization acquisition function in an existing radar signal acquisition device. The multichannel radar signal acquisition device based on digital channelization comprises a first FPGA, a second FPGA, a third FPGA, nine analog-to-digital converters and a multipath clock generator. The nine analog-to-digital converters are averagely distributed to the input ends of the first FPGA, the second FPGA and the third FPGA. Totally nine channelized acquisition channels are arranged on the first FPGA, the second FPGA and the third FPGA. The first FPGA is a main processing chip. The second FPGA and the third FPGA are auxiliary processing chips. The first FPGA supplies a synchronous acquisition signal to the second FPGA and the third FPGA through a differential bus and a GPIO signal, thereby realizing synchronous digital channelization acquisition of nine radar intermediate-frequency signals with instant bandwidth of 800MHz. A channelization result is output through a high-speed serial bus, thereby facilitating subsequent signal processing.
Description
Technical field
The present invention relates to radar signal acquisition technique field is and in particular to a kind of Multichannel radar based on digital channelizing
Signal pickup assembly.
Background technology
The reception of radar ELECTROMAGNETIC RADIATION SIGNATURE and process, are key technology and the research in electronic countermeasure and passive guidance field
Focus, with the high speed development of modern electronic technology, new system radar continuously emerges, and radar is to improve itself service behaviour and do
Disturb antagonism, generally take the multinomial measures such as extension operating frequency, frequency agility, frequency diversity, intra-pulse modulation, and join
Standby radar decoy.For adapting to the change of Radar Technology, passive guidance system needs higher requirement, for realizing to multi-section radar
The tracking of signal and identification bait radar, a lot of passive guidance systems employ the Estimation of Spatial Spectrum based on Array Signal Processing
Technology, for coordinating the realization of array df technology, passive guidance system needs to have the synchronous acquisition work(of Multichannel radar signal
Energy.Radar signal harvester common at present, generally existing instant bandwidth is little, number of channels is few, inter-channel synchronization ability
The shortcomings of, have impact on the Measure direction performance of passive guidance system to a certain extent.
The typical multichannel wideband digital receiver based on digital channelizing technology, complete using multipath high-speed A/D device
Become the digitlization of radiofrequency signal, the channelizing completing multi-path digital signal in FPGA is processed, and then carries out Radar Signal Recognition
And characteristic parameter extraction, the various information required for obtaining, and these information are stored, transmitted by HSSI High-Speed Serial Interface
To rear class signal processor, obtain the relevant information of target radar by computing.As shown in figure 1, patent name is a kind of typical case
Radar signal harvester the Chinese patent (patent No.：CN204215243U) disclose a kind of radar signal harvester,
Radar signal is converted to intermediate frequency letter by microwave down-converter unit, intermediate-freuqncy signal receiving unit by this radar signal harvester
Number, then using A/D and FPGA, digital channelizing process is carried out to radar signal, finally result is passed by PCIE bus
Defeated process and display to computer.
Exist not enough as follows in prior art：
(1) the existing radar signal harvester based on digital channelizing technology, does not possess multichannel synchronousing collection mostly
Function is it is impossible to meet the application scenarios such as Space ball.
(2) data transfer based on PCIE bus, poor real is it is impossible to meet the real-time processing of intensive radar pulse signal
Demand.
Content of the invention
The purpose of the present invention is it is proposed that an instant bandwidth is big, receiving channel is many, inter-channel synchronization is smart for above-mentioned deficiency
A kind of Multichannel radar signal pickup assembly based on digital channelizing that degree is high and data processing real-time is good.
The present invention specifically adopts the following technical scheme that：
A kind of Multichannel radar signal pickup assembly based on digital channelizing, including a FPGA, the 2nd FPGA, the 3rd
FPGA, No. 9 analog-digital converters and multipath clock generator, No. 9 analog-digital converters be evenly distributed in a FPGA, the 2nd FPGA and
The input of the 3rd FPGA, a FPGA, the 2nd FPGA and the 3rd FPGA are designed with 9 articles of channelizing acquisition channels altogether, the
Process chip based on one FPGA, the 2nd FPGA and the 3rd FPGA is from process chip, and a FPGA passes through differential bus and GPIO
Signal provides synchronous acquisition signal for the 2nd FPGA and the 3rd FPGA.
Preferably, described 9 acquisition channels include 1 main acquisition channel and 8 from acquisition channel, a FPGA,
It is designed with 3 articles of acquisition channels in two FPGA and the 3rd FPGA, a FPGA, the 2nd FPGA and the 3rd FPGA are connected to
No. 3 analog-digital converters.
Preferably, described main acquisition channel is located in a FPGA.
Preferably, a described FPGA, the 2nd FPGA and the 3rd FPGA carry out digital channelizing process to input signal, the
One FPGA also includes the configuration to system clock, and the channelizing to main acquisition channel detects and is to provide synchronous letter from acquisition channel
Number.
Preferably, 9 road analog if signals input this device, send into analog-digital converter and be converted to after signal conditioning circuit
Digital medium-frequency signal, 9 railway digital intermediate-freuqncy signals complete 64 road channelizings in FPGA parallel and process, and select 1 road signal to enter to become owner of
Acquisition channel, and Channel Detection is carried out to the baseband signal after its channelizing process, extract pulsewidth, the arrival time of radar pulse
And carrier parameter, remaining 8 road signal respectively enters from acquisition channel, and main acquisition channel provides letter to remaining 8 from acquisition channel
Road synchronizing signal, the channelizing for realizing 9 acquisition channels is synchronous, the effective radar pulse in 9 tunnels after channelized detection
Signal, is respectively stored in a FPGA, the FIFO of the 2nd FPGA and the 3rd FPGA, detects and starts during rising edge of a pulse to deposit
Storage, detect pulse falling edge or memory space full after stop storage, the output of pulse signal then this being gathered, hereafter
Continue the detection of next radar pulse.
Preferably, the sampling clock of described analog-digital converter is produced by phase-locked loop, and sampling clock is after clock buffer
It is divided into 5 road differential clock signals, 5 road differential clock signals are respectively through the sampling clock as analog-digital converter after delayer.
Preferably, choose described main acquisition channel to be detected, main acquisition channel intermediate-freuqncy signal is channelized process after defeated
Go out 32 sub-channels, pulse detection is carried out to 32 sub-channels, when effective impulse signal rising edge is detected in certain sub-channels
When, the channel number that pulse is located, pulse storage FIFO number parameter are sent to other 8 from acquisition channel, and pass through
GPIO signal provide impulsive synchronization storage signal, 8 from acquisition channel according to impulsive synchronization information, effective impulse data is stored in
Data buffer storage, when end-of-pulsing is detected, provides effective FIFO numbering and synchronous storage end signal to from acquisition channel, and
The output transmission of 9 acquisition channel channelized datas of synchronous averaging.
Preferably, the output transmission of described data adopts high-speed serial bus, based on a FPGA, the 2nd FPGA and the 3rd
GTX high-speed transceiver in FPGA carries out data transmission, and each FPGA, the 2nd FPGA and the 3rd FPGA are all using 8
GTX transmitter sends data.
The invention has the advantages that：Realize the multichannel number of radar signal based on analog-digital converter and FPGA
Word Digital Channelized Receiving, instantaneous reception bandwidth 800MHz, each Digital Channelized Receiving passage realizes strict synchronization, through multi-channel digital letter
Radar baseband signal after road reception processing is transferred to follow-up signal processing unit by HSSI High-Speed Serial Interface it is ensured that follow-up believe
Number process and direction finding synchronisation requirement；This device has that instant bandwidth is big, receiving channel is many, inter-channel synchronization high precision, data
The features such as process real-time is good, is very suitable for the application scenario to the passive array df of broadband radar target.
Brief description
Fig. 1 is a kind of broadband signal collector structural representation based on digital channelizing；
Fig. 2 is this Multichannel radar signal pickup assembly structural representation based on digital channelizing；
Fig. 3 is A/D sampling clock synchronization scenario schematic diagram；
Fig. 4 is channelizing synchronization schematic diagram.
Specific embodiment
With specific embodiment, the specific embodiment of the present invention is described further below in conjunction with the accompanying drawings：
FPGA:(Field-Programmable Gate Array), i.e. field programmable gate array.
FIFO：(First Input First Output), First Input First Output.
GPIO：(General-Purpose Input/Output Ports), general purpose I/O port.
A/D：(Analog-to-Digital Converter), analog-digital converter.
As shown in Fig. 2 a kind of Multichannel radar signal pickup assembly based on digital channelizing, including a FPGA,
Two FPGA, the 3rd FPGA, No. 9 analog-digital converters (A/D) and multipath clock generator, No. 9 analog-digital converters are evenly distributed in
One FPGA, the input of the 2nd FPGA and the 3rd FPGA, a FPGA, the 2nd FPGA and the 3rd FPGA are designed with 9 articles altogether
Channelizing acquisition channel, process chip based on a FPGA, the 2nd FPGA and the 3rd FPGA is from process chip, and a FPGA leads to
Crossing differential bus and GPIO signal provides synchronous acquisition signal for the 2nd FPGA and the 3rd FPGA.
Article 9, acquisition channel includes 1 main acquisition channel and 8 from acquisition channel, a FPGA, the 2nd FPGA and the 3rd
It is designed with 3 acquisition channels, wherein, main acquisition channel is located in a FPGA, a FPGA, the 2nd FPGA and the in FPGA
No. 3 analog-digital converters are connected on three FPGA.
First FPGA, the 2nd FPGA and the 3rd FPGA carry out digital channelizing process to input signal, and a FPGA also wraps
Include the configuration to system clock, the channelizing to main acquisition channel detects and is to provide synchronizing signal from acquisition channel.
9 road analog if signals input this device, send into analog-digital converter and be converted in numeral after signal conditioning circuit
Frequency signal, 9 railway digital intermediate-freuqncy signals complete 64 road channelizings in FPGA parallel and process, and select 1 road signal to enter to become owner of collection logical
Road, and Channel Detection is carried out to the baseband signal after its channelizing process, extract pulsewidth, arrival time and the carrier frequency of radar pulse
Parameter, remaining 8 road signal respectively enters from acquisition channel, and main acquisition channel provides channelizing same to remaining 8 from acquisition channel
Step signal, the channelizing for realizing 9 acquisition channels is synchronous, the effective radar pulse signal in 9 tunnels after channelized detection, point
It is not stored in a FPGA, the FIFO of the 2nd FPGA and the 3rd FPGA, detect and start during rising edge of a pulse to store, detect
Stop storage after pulse falling edge or memory space are full, then the pulse signal that this gathers is exported by GTX interface, this
Continue the detection of next radar pulse afterwards.
As shown in figure 3, the sampling clock of analog-digital converter is produced by phase-locked loop, sampling clock divides after clock buffer
For 5 road differential clock signals, 5 road differential clock signals are respectively through the sampling clock as analog-digital converter after delayer.Should
The amount of delay of delayer can adjust, and maximum delay time is 1500ps, resolution ratio 5ps, by arranging amount of delay it is ensured that adopting
Sample clock is alignment in the sampling clock input of every A/D, and this is also the premise of data syn-chronization.Data between 5 A/D is same
As shown in Fig. 2 wherein selecting a piece of A/D to work in Master pattern, remaining 4 work in Slave pattern to step scheme, are operated in
, after clock distributor, the reference clock being supplied to remaining 4 A/D is defeated for the reference clock RCOUT of the A/D output of master pattern
Enter RCLK, realize the synchronization of 5 A/D output datas.Using described clock synchronizing method it is ensured that 9 road A/D sampling clocks same
Step error is within 20ps.
As shown in figure 4, a total of 9 acquisition channels of radar signal harvester of the present invention, if 9 acquisition channels
All carry out Channel Detection and radar pulse characteristic parameter extraction after channelized process, be then easy to that each Air conduct measurement result occurs
Inconsistent situation, for the radar pulse collection mistake avoiding this problem to cause, chooses main acquisition channel and is detected, main collection
Export 32 sub-channels after the channelized process of passage intermediate-freuqncy signal, pulse detection is carried out to 32 sub-channels, when in certain height
When Channel Detection is to effective impulse signal rising edge, the channel number that pulse is located, pulse storage FIFO number parameter send
To other 8 from acquisition channel, and impulsive synchronization is provided to store signal by GPIO signal, 8 from acquisition channel according to pulse
Synchronizing information, effective impulse data is stored in data buffer storage, when end-of-pulsing is detected, provides effectively to from acquisition channel
FIFO numbering and synchronous storage end signal, and the output transmission of 9 acquisition channel channelized datas of synchronous averaging.
The output transmission of data adopts high-speed serial bus, based on the GTX in a FPGA, the 2nd FPGA and the 3rd FPGA
High-speed transceiver carries out data transmission, the GTX interface maximum transmission rate in typical Xilinx company V7 Series FPGA up to
12.5Gbps, the Aurora IP kernel being embedded using FPGA, encoded using 8B10B, single channel GTX valid data transmission bandwidth is
Height is up to 10Gbps.In view of the stability of the overheads such as data-frame sync and system, a FPGA, the 2nd FPGA and
Three FPGA all send data using 8 GTX transmitters, and the transmission bandwidth of single GTX is 6.25Gbps, and 8 passage GTX transmitters can
There is provided effective transmission bandwidth of 40Gbps it is ensured that repetition period 5us, dutycycle are not more than the real-time biography of 30% radar pulse
Defeated.
Certainly, described above is not limitation of the present invention, and the present invention is also not limited to the example above, and this technology is led
Change, remodeling, interpolation or replacement that the technical staff in domain is made in the essential scope of the present invention, also should belong to the present invention's
Protection domain.
Claims (8)
1. a kind of Multichannel radar signal pickup assembly based on digital channelizing it is characterised in that include a FPGA, second
FPGA, the 3rd FPGA, No. 9 analog-digital converters and multipath clock generator, No. 9 analog-digital converters be evenly distributed in a FPGA,
The input of the 2nd FPGA and the 3rd FPGA, a FPGA, the 2nd FPGA and the 3rd FPGA is designed with 9 articles of channelizings altogether and adopts
Collect passage, process chip based on a FPGA, the 2nd FPGA and the 3rd FPGA is from process chip, and it is total that a FPGA passes through difference
Line and GPIO signal provide synchronous acquisition signal for the 2nd FPGA and the 3rd FPGA.
2. as claimed in claim 1 a kind of Multichannel radar signal pickup assembly based on digital channelizing it is characterised in that
Described 9 acquisition channels include 1 main acquisition channel and 8 from acquisition channel, a FPGA, the 2nd FPGA and the 3rd FPGA
In be designed with 3 acquisition channels, a FPGA, the 2nd FPGA and the 3rd FPGA are connected to No. 3 analog-digital converters.
3. as claimed in claim 2 a kind of Multichannel radar signal pickup assembly based on digital channelizing it is characterised in that
Described main acquisition channel is located in a FPGA.
4. a kind of Multichannel radar signal pickup assembly based on digital channelizing as described in claim 1 or 3, its feature exists
In a described FPGA, the 2nd FPGA and the 3rd FPGA carry out digital channelizing process to input signal, and a FPGA also includes
Configuration to system clock, the channelizing to main acquisition channel detects and is to provide synchronizing signal from acquisition channel.
5. as claimed in claim 4 a kind of Multichannel radar signal pickup assembly based on digital channelizing it is characterised in that
9 road analog if signals input this device, send into analog-digital converter and be converted to digital medium-frequency signal after signal conditioning circuit, and 9
Railway digital intermediate-freuqncy signal completes 64 road channelizings in FPGA parallel and processes, and selects 1 road signal to enter to become owner of acquisition channel, and to it
Baseband signal after channelizing is processed carries out Channel Detection, extracts pulsewidth, arrival time and the carrier parameter of radar pulse, remaining
8 road signals respectively enter from acquisition channel, and main acquisition channel provides channelizing synchronizing signal for remaining 8 from acquisition channel, use
Synchronous in the channelizing realizing 9 acquisition channels, after channelized detection the effective radar pulse signal in 9 tunnels, is respectively stored in
In first FPGA, the FIFO of the 2nd FPGA and the 3rd FPGA, detect and start during rising edge of a pulse to store, pulse is detected and decline
Along or memory space full after stop storage, the output of pulse signal then this being gathered, hereafter continue next radar arteries and veins
The detection of punching.
6. as claimed in claim 5 a kind of Multichannel radar signal pickup assembly based on digital channelizing it is characterised in that
The sampling clock of described analog-digital converter is produced by phase-locked loop, and sampling clock is divided into 5 road differential clocks after clock buffer
Signal, 5 road differential clock signals are respectively through the sampling clock as analog-digital converter after delayer.
7. as claimed in claim 5 a kind of Multichannel radar signal pickup assembly based on digital channelizing it is characterised in that
Choose described main acquisition channel to be detected, main acquisition channel intermediate-freuqncy signal is channelized process after export 32 sub-channels, right
32 sub-channels carry out pulse detection, when effective impulse signal rising edge is detected in certain sub-channels, pulse are located
Channel number, pulse storage FIFO number parameter are sent to other 8 from acquisition channel, and provide pulse same by GPIO signal
Step storage signal, 8 from acquisition channel according to impulsive synchronization information, effective impulse data is stored in data buffer storage, when detecting
During end-of-pulsing, provide effective FIFO numbering and synchronous storage end signal to from acquisition channel, and 9 collections of synchronous averaging are logical
The output transmission of road channelized data.
8. as claimed in claim 5 a kind of Multichannel radar signal pickup assembly based on digital channelizing it is characterised in that
The output transmission of described data adopts high-speed serial bus, based on the GTX in a FPGA, the 2nd FPGA and the 3rd FPGA at a high speed
Transceiver carries out data transmission, and each FPGA, the 2nd FPGA and the 3rd FPGA all send number using 8 GTX transmitters
According to.
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106849966A (en) * | 2017-03-31 | 2017-06-13 | 安徽四创电子股份有限公司 | A kind of wideband Larger Dynamic four-way digital receiver |
| CN107942291A (en) * | 2017-10-12 | 2018-04-20 | 西安天和防务技术股份有限公司 | Intermediate frequency digital receiver, IF signal processing method |
| CN109547091A (en) * | 2018-11-27 | 2019-03-29 | 上海航天电子通讯设备研究所 | The processing system of multichannel Channel Detection based on VDE |
| CN110196416A (en) * | 2019-05-30 | 2019-09-03 | 电子科技大学 | A kind of radar multi-channel data acquisition and real-time processing device |
| CN110557121A (en) * | 2019-08-12 | 2019-12-10 | 中国电子科技集团公司第四十一研究所 | multi-channel high-speed sampling data synchronous calibration method based on FPGA |
| CN111413675A (en) * | 2020-04-10 | 2020-07-14 | 扬州宇安电子科技有限公司 | Signal acquisition equipment and acquisition method thereof |
| CN111736517A (en) * | 2020-08-07 | 2020-10-02 | 成都谱信通科技有限公司 | Synchronous acquisition and processing card system based on multichannel ADC and FPGA |
| CN112162126A (en) * | 2020-09-16 | 2021-01-01 | 普源精电科技股份有限公司 | Multi-channel pulse generator, signal generation method, multi-channel synchronization system and method |
| CN112558522A (en) * | 2020-12-11 | 2021-03-26 | 深圳大学 | Electrical signal acquisition system of multichannel friction nanometer generator |
| CN112737626A (en) * | 2020-12-18 | 2021-04-30 | 中国电子科技集团公司第五十四研究所 | Broadband parallel receiving and processing device based on VPX bus |
| CN113311394A (en) * | 2021-05-18 | 2021-08-27 | 中国船舶重工集团公司第七二三研究所 | Ultra-wideband PDW real-time fusion method |
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| CN106849966A (en) * | 2017-03-31 | 2017-06-13 | 安徽四创电子股份有限公司 | A kind of wideband Larger Dynamic four-way digital receiver |
| CN107942291A (en) * | 2017-10-12 | 2018-04-20 | 西安天和防务技术股份有限公司 | Intermediate frequency digital receiver, IF signal processing method |
| CN109547091A (en) * | 2018-11-27 | 2019-03-29 | 上海航天电子通讯设备研究所 | The processing system of multichannel Channel Detection based on VDE |
| CN110196416A (en) * | 2019-05-30 | 2019-09-03 | 电子科技大学 | A kind of radar multi-channel data acquisition and real-time processing device |
| CN110557121B (en) * | 2019-08-12 | 2023-03-24 | 中国电子科技集团公司第四十一研究所 | Multi-channel high-speed sampling data synchronous calibration method based on FPGA |
| CN110557121A (en) * | 2019-08-12 | 2019-12-10 | 中国电子科技集团公司第四十一研究所 | multi-channel high-speed sampling data synchronous calibration method based on FPGA |
| CN111413675A (en) * | 2020-04-10 | 2020-07-14 | 扬州宇安电子科技有限公司 | Signal acquisition equipment and acquisition method thereof |
| CN111736517A (en) * | 2020-08-07 | 2020-10-02 | 成都谱信通科技有限公司 | Synchronous acquisition and processing card system based on multichannel ADC and FPGA |
| CN112162126A (en) * | 2020-09-16 | 2021-01-01 | 普源精电科技股份有限公司 | Multi-channel pulse generator, signal generation method, multi-channel synchronization system and method |
| CN112558522A (en) * | 2020-12-11 | 2021-03-26 | 深圳大学 | Electrical signal acquisition system of multichannel friction nanometer generator |
| CN112737626A (en) * | 2020-12-18 | 2021-04-30 | 中国电子科技集团公司第五十四研究所 | Broadband parallel receiving and processing device based on VPX bus |
| CN112737626B (en) * | 2020-12-18 | 2022-07-01 | 中国电子科技集团公司第五十四研究所 | Broadband parallel receiving and processing device based on VPX bus |
| CN113311394A (en) * | 2021-05-18 | 2021-08-27 | 中国船舶重工集团公司第七二三研究所 | Ultra-wideband PDW real-time fusion method |
| CN113311394B (en) * | 2021-05-18 | 2024-08-23 | 中国船舶重工集团公司第七二三研究所 | Ultra-wideband PDW real-time fusion method |
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