CN110557121A - multi-channel high-speed sampling data synchronous calibration method based on FPGA - Google Patents
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B13/00—Adaptive control systems, i.e. systems automatically adjusting themselves to have a performance which is optimum according to some preassigned criterion
- G05B13/02—Adaptive control systems, i.e. systems automatically adjusting themselves to have a performance which is optimum according to some preassigned criterion electric
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
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- H03M1/1009—Calibration
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
- H03M1/1255—Synchronisation of the sampling frequency or phase to the input frequency or phase
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
the invention discloses a multichannel high-speed sampling data synchronous calibration method based on FPGA (field programmable gate array), belonging to the field of digital signal processing, and the invention relates to a multichannel high-speed sampling data synchronous calibration method based on FPGA, which is a method for synchronously calibrating and implementing sampling data among channels implemented by multichannel high-speed sampling, and effectively solves the problem of data synchronization among the channels after multichannel high-speed ADC (analog to digital converter) sampling.
Description
Technical Field
The invention belongs to the field of digital signal processing, and particularly relates to a multichannel high-speed sampling data synchronous calibration method based on an FPGA (field programmable gate array).
Background
with the progress of chip integration design technology and processing technology, the application of high-speed sampling above GSPS is more and more common in large-bandwidth signal analysis at present, and a high-speed sampling system has high sampling rate, large design implementation difficulty of a front-end analog part, a sampling part and a rear-end signal processing part, high requirement and large real-time data volume, thereby bringing great burden to the real-time processing analysis of signals. In practical application, due to use requirements, the situation of multi-channel high-speed sampling is more and more common, in the application of multi-channel high-speed sampling, besides the problems caused by the high speed, the problem of synchronism among multiple channels caused by design difference, processing process deviation and the like also exists, and for the use situation of multi-channel sampling, the synchronism among the channels is often a key link of the performance of the whole acquisition system, so that the synchronism is a difficult problem of analysis and design of multi-channel high-speed sampling signals.
At present, due to the limitations of design layout, processing technology and the like in the aspect of hardware implementation, no method for ensuring the complete consistency among a plurality of channels exists, and deviation exists among the channels. In the aspect of software implementation, due to high data rate and large data volume, data can only be partially stored through a large storage device and then subsequently analyzed and processed, and the requirement of real-time synchronous processing cannot be met.
The prior art has the following defects:
Due to the limitations of designing and processing processes, the difference between multiple channels cannot be adjusted in hardware implementation at present. In the sampling operation process, an operation method for adjusting data synchronization deviation by adjusting the phase relation of sampling clocks among paths exists at present, but the phase of the sampling clock is adjusted, only one sampling clock period can be adjusted, the adjustment range is narrow, and only some specific conditions can be solved. In addition, the problem of asynchronism between sampling clocks can be caused by the phase adjustment of the sampling clocks, and the problem of asynchronous processing of clock domains between channels caused by clock deviation is also revealed in the subsequent channel signal analysis processing. And the delay setting of the internal channel of the ADC is adjusted to improve the synchronization performance among multiple channels, but the adjustable capacity of the delay setting of the internal channel of the ADC is also narrow, generally about one maximum sampling clock period, and the condition of large deviation among the channels cannot be met. And some ADCs have no channel delay regulating function inside, and need to be used according to the function condition of the specific device of the ADC. The method not only causes the cost of stored hardware to be increased, but also can not meet the requirement of signal real-time processing, and only can carry out synchronous processing and analysis on data among channels subsequently through the upper computer software, thereby increasing the workload in the aspect of software.
Disclosure of Invention
Aiming at the technical problems in the prior art, the invention provides a multichannel high-speed sampling data synchronous calibration method based on FPGA, which is reasonable in design, overcomes the defects of the prior art and has a good effect.
in order to achieve the purpose, the invention adopts the following technical scheme:
a multi-channel high-speed sampling data synchronous calibration method based on FPGA is carried out according to the following steps:
Step 1: for a given n-channel high-speed acquisition system, setting the sampling frequency of the high-speed ADC of each channel as fsfrequency of calibration test signal fbSetting FIFO buffer depth of each channel as m and channel signal level discrimination reference value as V; under the condition that the ADC and the sampling clock of each channel work normally, inputting a synchronous calibration test signal to each channel, sampling data of each channel, and if the synchronous calibration test signals input to each channel are completely synchronous, pausing to receive the ADC data after each channel of the FPGA is full of FIFO data, and then entering step 2;
Step 2: for m-point FIFO data of each channel buffered by n channels according to channel informationJudging the reference value V by the signal level, judging the rising edge of the signal to obtain the data sample point position at the time t of the rising edge of the signal of each channel, and calculating and determining the actual sample point length L of the data sample point cached in the FIFO at the time t of the rising edge position in each channel1、L2...Ln-1、Lnthen entering step 3;
And step 3: by cyclic comparison, L is determined1、L2...Ln-1、LnMinimum and maximum of (3), minimum being denoted as LmixAnd the maximum value is LmaxThen entering step 4;
And 4, step 4: mixing L with1、L2...Ln-1、LnIs sequentially reduced by LmixForm a new FIFO buffer depth of each channel, denoted L'1、L’2...L’n-1、L’n(ii) a Then entering step 5;
And 5: according to L'1、L’2...L’n-1、L’nThe cache depth of the multi-channel data acquisition system is designed, the FIFO cache length of each channel is designed, and the synchronous calibration of the whole multi-channel high-speed sampling data is completed.
preferably, the FIFO buffer depth m of each channel described in step 1 should satisfy the condition:
Preferably, in step 2, the following steps are specifically performed:
step 2.1: setting i as a channel index, and enabling i to be 1; setting c as a channel cache data index; entering the step 2.2;
Step 2.2: acquiring m-point depth FIFO data of the i index channel, enabling c to be 1, and entering step 2.3;
step 2.3: obtaining c-indexed channel FIFO data scEntering step 2.4;
Step 2.4: determining channel FIFO data scjudging the size of the reference value V with the channel signal level;
If: the judgment result is scIf less than V, then orderc, adding 1, and then entering the step 2.5;
Or as a result of the judgment scIf greater than or equal to V, let Li be m-c, add 1 to i, and then go to step 2.6;
step 2.5: judging the sizes of the channel cache data index c and the FIFO cache depth m;
If: if c is larger than m, making Li equal to 0, adding 1 to i, and then entering step 2.6;
Or if the judgment result is that c is less than or equal to m, returning to the step 2.3;
Step 2.6: judging the sizes of the channel index i and the channel number n;
if: if the judgment result is that i is less than or equal to n, returning to the step 2.2;
Or if the judgment result is that i is larger than n, the whole L is obtained1、L2...Ln-1、Lnthe process of (2) ends.
Preferably, in step 3, the following steps are specifically performed:
step 3.1: let j be L1、L2...Ln-1、Lnlet j equal to 2 and let Lmix＝L1，Lmax＝L1entering step 3.2;
Step 3.2: obtain the index data L of jjThen entering step 3.3;
step 3.3: respectively judging the index data Ljand a minimum value LmixMaximum value Lmaxthe size of (d);
If: the judgment result is Ljless than or equal to LmixThen let Lmix＝Lj(ii) a The judgment result is LjGreater than or equal to Lmaxthen let Lmax＝Lj(ii) a Then adding 1 to j, and then entering step 3.4;
or L is judged as a resultjGreater than LmixOr LjLess than LmaxIf yes, adding 1 to j, and then entering step 3.4;
Step 3.4: judging the sizes of j and the number n of channels;
If: if j is less than or equal to n, returning to the step 3.2;
Or if j is larger than n, the solving process is finished.
preferably, L 'described in step 4'1、L’2...L’n-1、L’nIs the corresponding value of L1、L2...Ln-1、LnIs subtracted by LmixThe latter value.
preferably, after the acquisition system is started up hard each time, because the FIFO needs to be filled to achieve the purpose of synchronous adjustment of each channel, the first L data output by the FIFO of each channel in the FPGA are asynchronous and need to be discarded, after delaying the L data, the data output by the FIFO buffer of each channel achieves consistency, and then the data output by the FIFO is received and provided for the back-end processing.
preferably, L ═ Lmax-Lmix。
preferably, the channel signal level discrimination reference value V should be smaller than the maximum amplitude of the calibration test signal and larger than the minimum amplitude of the calibration test signal.
Preferably, the test signal frequency f is calibratedbAt least less than the channel high-speed ADC sampling frequency fsOne tenth of the total.
The invention has the following beneficial technical effects:
the invention relates to a multichannel high-speed sampling data synchronous calibration method based on FPGA (field programmable gate array), which is a method for synchronously calibrating and implementing sampling data among channels implemented by multichannel high-speed sampling, and effectively solves the problem of data synchronization among the channels after the multichannel high-speed ADC (analog to digital converter) is sampled.
Compared with other schemes for subsequent analysis through large-capacity storage, the method effectively solves the real-time processing problem of multi-channel high-speed signal acquisition synchronization, effectively reduces the hardware cost of storage, reduces the workload of subsequent software, and has the effects of reducing cost and improving efficiency; compared with other schemes for adjusting sampling clock or ADC parameters, the method is more flexible and accurate, has wide adjusting range, does not influence the existing hardware condition, and does not bring chain effect influence to sampling and subsequent processing links due to the implementation of the method.
drawings
FIG. 1 is a diagram of the implementation of the method of the present invention.
fig. 2 is a diagram of an implementation process with minimal FPGA resource overhead.
Detailed Description
the invention is described in further detail below with reference to the following figures and detailed description:
The invention relates to a method for realizing multichannel high-speed sampling data synchronous calibration based on FPGA (field programmable gate array), which is specially designed for the problem of data synchronization among channels acquired at a high speed by multiple channels. The method unit directly receives the high-speed data sampled and input by the high-speed ADC to the FPGA interface, then establishes the channel FIFO cache in the FPGA, and adjusts and controls the relative time of the cache output interface data through the channel FIFO cache depth, thereby realizing the time deviation adjustment of the multi-channel sampling data and achieving the complete synchronization function of the multi-channel sampling data.
The implementation process of the method is shown in fig. 1, assuming that n high-speed acquisition channels are designed according to the synchronous design requirement in the aspect of hardware design, and the sampling data is input into the FPGA for signal analysis and processing, wherein the n sampling channels are respectively processed by ch1、ch2...chn-1、chnit is shown that the sample data width is the same for each sampling channel. In the channel calibration stage, the FIFO buffer depth of the channel is setDegree m, as shown in FIG. 1, s1、s2...sm-1、smThe sampling point data cached in the channel FIFO are shown, the marks show that the sampling point data are sequentially cached in the channel FIFO cache according to the time sequence, and the cached data follow the first-in first-out rule. Let the sampling frequency be fsFrequency of calibration test signal fbAssuming that the cache depth m satisfiesWhere the calibration test signal is typically a pulsed or square wave signal fed with a relatively sharp variation along the line, the use of a FIFO depth for each channel during the calibration phase ensures that a sample data period of the calibration test signal is stored.
In the calibration stage, under the condition that ADC and sampling clock of each channel work normally, synchronous calibration test signal is input to each channel to perform data sampling of each channel, and the frequency of the calibration test signal is fbSampling frequency of fsAnd it is assumed that the synchronous calibration test signals input to the channels are completely synchronous. When the FPGA is full of FIFO data, the ADC data is suspended from being received, and the test signal data can be analyzed in the FPGA. And judging a reference value V for a given signal level, comparing and judging the data of each channel with the value V, judging that the signal is sampled in the low level stage of the calibration test signal when the sampling data value is less than V, judging that the signal is sampled in the high level stage of the calibration test signal when the signal sampling data value is more than or equal to V, and marking the signal rising edge change time of the calibration test signal as the time t at the position where the sampling data is changed from the low level to the high level. In theory, under the condition of no channel deviation, the t time of each channel should be kept at one sampling point time of signal sampling, but due to hardware deviation in processing and manufacturing, data sampling points of each channel at the t time cannot be kept at the same time, so that the problem of non-synchronization of multi-channel sampling data is caused.
Through the discrimination processing of the data of each channel, the actual position of the rising edge position t of the calibration signal of each channel in each FIFO in the FPGA can be determined, and therefore each channel can be determinedThe actual sample length of the data sample at the time of the rising edge position t in each channel buffered in the FIFO is recorded as L1、L2...Ln-1、LnI.e. reflects the actual time position deviation of the rising edge of the calibration test signal in the respective channel.
Actual sample length L of data sample buffered in FIFO at time t when rising edge position in each channel is determined1、L2...Ln-1、Lnthen, in order to satisfy the synchronization function of each channel data, the cache depth of each path FIFO is redesigned to be L1、L2...Ln-1、LnAfter the signals of each channel are sampled, the data output by the FIFO buffer can ensure the synchronization requirement.
To reduce FPGA resource consumption, the L resulting from actual testing can be determined1、L2...Ln-1、LnWhich channel has the smallest cache depth is marked as LmixWhich channel has the largest cache depth is marked as Lmax. The cache depth of all channels can be reduced by L correspondinglymixI.e. L1-Lmix、L2-Lmix...Ln-1-Lmix、Ln-LmixIs recorded as L'1、L’2...L’n-1、L’n. Then the cache depth of the way FIFO may be redesigned to L'1、L’2...L’n-1、L’nIn which the least buffered channel will no longer use the FIFO, as shown in FIG. 2, assuming chnL of channel after being discriminated at t momentnMinimum in the channel, chnthe channel data is no longer FIFO buffered, it is also characterized in each channel, chnThe channel data bias is most posterior. Other lane FIFO depth reduction LmixIn fig. 2, the specific cached data depth is identified by the sampling point information marked by the shadow inside the thick frame. Under the condition, the function of multi-channel high-speed sampling data synchronization can be achieved, and meanwhile, the consumption of FPGA resources can be reduced to the minimum.
in the specific using process, the method of the invention is in the situation that the existing hardware and the sampling frequency are not changedIn the case of the above, L 'obtained by calibration can be carried out in the subsequent process only by once calibration'1、L’2...L’n-1、L’nThe channel FIFO depth system achieves the data synchronization use performance of multiple channels without calibration operation. After the channel hardware or the sampling basic parameters are adjusted, the method of the invention can be implemented to carry out calibration again so as to correct the change deviation.
After the acquisition system is started up hard each time, the FIFO is filled to achieve the purpose of synchronous adjustment of each channel, and the front L of FIFO output of each channel in the FPGAmax-LmixThe data is not synchronous and needs to be discarded, at delay Lmax-LmixThe data is received and then FIFO output data is provided for back-end processing.
it is to be understood that the above description is not intended to limit the present invention, and the present invention is not limited to the above examples, and those skilled in the art may make modifications, alterations, additions or substitutions within the spirit and scope of the present invention.
Claims (9)
1. A multichannel high-speed sampling data synchronous calibration method based on FPGA is characterized in that: the method comprises the following steps:
Step 1: for a given n-channel high-speed acquisition system, setting the sampling frequency of the high-speed ADC of each channel as fsFrequency of calibration test signal fbSetting FIFO buffer depth of each channel as m and channel signal level discrimination reference value as V; under the condition that the ADC and the sampling clock of each channel work normally, inputting a synchronous calibration test signal to each channel, sampling data of each channel, and if the synchronous calibration test signals input to each channel are completely synchronous, pausing to receive the ADC data after each channel of the FPGA is full of FIFO data, and then entering step 2;
Step 2: judging the reference value V of m-point FIFO data of each channel cached by n channels according to the signal level of the channel, judging the rising edge of the signal to obtain the data sampling point position at the t moment of the rising edge of the signal of each channel, and calculating and determining the data sampling point position in each channelActual sample length L of data sample at rising edge position t in FIFO buffer1、L2...Ln-1、LnThen entering step 3;
And step 3: by cyclic comparison, L is determined1、L2...Ln-1、LnMinimum and maximum of (3), minimum being denoted as LmixAnd the maximum value is Lmaxthen entering step 4;
And 4, step 4: mixing L with1、L2...Ln-1、Lnis sequentially reduced by LmixForm a new FIFO buffer depth of each channel, denoted L'1、L’2...L’n-1、L’n(ii) a Then entering step 5;
And 5: according to L'1、L’2...L’n-1、L’nthe cache depth of the multi-channel data acquisition system is designed, the FIFO cache length of each channel is designed, and the synchronous calibration of the whole multi-channel high-speed sampling data is completed.
2. the method for synchronously calibrating the multi-channel high-speed sampling data based on the FPGA of claim 1, which is characterized in that: the FIFO cache depth m of each channel in the step 1 needs to satisfy the condition:
3. the method for synchronously calibrating the multi-channel high-speed sampling data based on the FPGA of claim 1, which is characterized in that: in step 2, the method specifically comprises the following steps:
Step 2.1: setting i as a channel index, and enabling i to be 1; setting c as a channel cache data index; entering the step 2.2;
step 2.2: acquiring m-point depth FIFO data of the i index channel, enabling c to be 1, and entering step 2.3;
Step 2.3: obtaining c-indexed channel FIFO data scEntering step 2.4;
Step 2.4: determining channel FIFO data scJudging the size of the reference value V with the channel signal level;
If: the judgment result is scIf the value is less than V, adding 1 to c, and then entering step 2.5;
Or as a result of the judgment scif greater than or equal to V, let Li be m-c, add 1 to i, and then go to step 2.6;
step 2.5: judging the sizes of the channel cache data index c and the FIFO cache depth m;
If: if c is larger than m, making Li equal to 0, adding 1 to i, and then entering step 2.6;
or if the judgment result is that c is less than or equal to m, returning to the step 2.3;
step 2.6: judging the sizes of the channel index i and the channel number n;
If: if the judgment result is that i is less than or equal to n, returning to the step 2.2;
or if the judgment result is that i is larger than n, the whole L is obtained1、L2...Ln-1、LnThe process of (2) ends.
4. The method for synchronously calibrating the multi-channel high-speed sampling data based on the FPGA of claim 1, which is characterized in that: in step 3, the method specifically comprises the following steps:
Step 3.1: let j be L1、L2...Ln-1、Lnlet j equal to 2 and let Lmix＝L1，Lmax＝L1Entering step 3.2;
Step 3.2: obtain the index data L of jjThen entering step 3.3;
step 3.3: respectively judging the index data LjAnd a minimum value LmixMaximum value LmaxThe size of (d);
If: the judgment result is LjLess than or equal to LmixThen let Lmix＝Lj(ii) a The judgment result is LjGreater than or equal to LmaxThen let Lmax＝Lj(ii) a Then adding 1 to j, and then entering step 3.4;
Or the result of judgmentIs LjGreater than LmixOr Ljless than LmaxIf yes, adding 1 to j, and then entering step 3.4;
Step 3.4: judging the sizes of j and the number n of channels;
if: if j is less than or equal to n, returning to the step 3.2;
or if j is larger than n, the solving process is finished.
5. The method for synchronously calibrating the multi-channel high-speed sampling data based on the FPGA of claim 1, which is characterized in that: l 'in step 4'1、L’2...L’n-1、L’nIs the corresponding value of L1、L2...Ln-1、LnIs subtracted by LmixThe latter value.
6. The method for synchronously calibrating the multi-channel high-speed sampling data based on the FPGA of claim 1, which is characterized in that: after the acquisition system is started up hard each time, the FIFO is filled to achieve the purpose of synchronous adjustment of each channel, the first L data output by the FIFO of each channel in the FPGA are asynchronous and need to be discarded, after the L data are delayed, the data output by the FIFO of each channel are cached to achieve consistency and synchronism, and then the data output by the FIFO are received and provided for the back-end processing.
7. The method for synchronously calibrating the multi-channel high-speed sampling data based on the FPGA as recited in claim 6, wherein: l ═ Lmax-Lmix。
8. The method for synchronously calibrating the multi-channel high-speed sampling data based on the FPGA of claim 1, which is characterized in that: the channel signal level discrimination reference value V should be smaller than the maximum amplitude of the calibration test signal and larger than the minimum amplitude of the calibration test signal.
9. the FPGA-based multi-channel high-speed sampling data synchronous calibration method according to claim 1The method is characterized in that: calibrating the test signal frequency fbAt least less than the channel high-speed ADC sampling frequency fsOne tenth of the total.
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| CN114267407A (en) * | 2022-03-03 | 2022-04-01 | 合肥悦芯半导体科技有限公司 | Precision correction method, device and system and precision correction equipment |
| CN114267407B (en) * | 2022-03-03 | 2022-06-10 | 合肥悦芯半导体科技有限公司 | Precision correction method, device and system and precision correction equipment |
| CN114844750A (en) * | 2022-04-15 | 2022-08-02 | 中国电子科技集团公司第五十四研究所 | Rapid amplitude-phase consistency calibration method based on full-synchronous sampling |
| CN116979978A (en) * | 2023-09-22 | 2023-10-31 | 西安乾景防务技术有限公司 | FPGA-based method and device for calibrating amplitude between receiving channels |
| CN116979978B (en) * | 2023-09-22 | 2024-01-23 | 西安乾景防务技术有限公司 | FPGA-based method and device for calibrating amplitude between receiving channels |
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