CN109655644B - Method and device for reducing random wave signal output jitter - Google Patents
Method and device for reducing random wave signal output jitter Download PDFInfo
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Abstract
The invention discloses a method and a device for reducing the output jitter of an arbitrary wave signal, which are realized by an arbitrary wave digital waveform high sampling, filtering, interpolation or extraction method and can realize the jitter reduction of the arbitrary wave signal with a low sampling rate. The method comprises the following steps: sampling a target waveform signal by adopting a high sampling rate to obtain a digital waveform signal sample point with the high sampling rate; carrying out low-pass filtering processing on the data waveform signal sample points; and judging whether the high sampling rate of the data waveform signal sample points is an integral multiple of the corresponding DAC sampling rate, and performing integral multiple extraction or fractional multiple interpolation processing on the filtered data waveform signal sample points to obtain the target jitter data waveform signal of the corresponding DAC sampling rate.
Description
Technical Field
The disclosure belongs to the field of electronic test and measurement, and particularly relates to a processing method for reducing random wave signal output jitter.
Background
The arbitrary wave signal generator is a signal simulator capable of outputting standard function waveforms, complex waveforms and arbitrary waveforms, has the characteristics of flexible waveform generation, large output signal bandwidth, multi-channel synchronous output, rich output signal systems and the like, and has very wide application in the field of signal simulation, generation and other requirements. Modern arbitrary wave signal generators sample signals at a specified sampling rate in a point-by-point waveform output mode to generate sampled digital waveforms, store the sampled digital waveforms in a waveform memory, and output the sampled digital waveforms point by point to a digital-to-analog converter (DAC) to generate corresponding arbitrary wave signals. At present, the sampling rate of the most widely applied arbitrary wave signal generator is about 2GSa/s, and the maximum sampling rate of the arbitrary wave signal generator can reach more than 65 GSa/s.
For an arbitrary wave signal generator, when the frequency period of a signal is not in integral multiple relation with the sampling rate of a DAC, in the process of generating a digital waveform, a sampling error is generated if the sampling time is not matched with the period of the waveform, taking a pulse signal as an example, a pulse signal with the frequency of 98MHz is sampled by using the sampling rate of 1GSa/s, because the 98MHz cannot completely divide the 1GSa/s, a sampling error is generated at the edge of the pulse, so that the phenomenon of sampling point mismatch exists at both the high level and the low level of the pulse, signal jitter is generated from the time domain, the typical jitter under the sampling rate of 1GSa/s is 1000ps (═ 1ns), and the jitter index is more deteriorated when the sampling rate is lower. The waveform jitter limits the application of an arbitrary wave signal generator in high-purity signal simulation, the jitter is required to be lower than 100ps in the fields of radar signal simulation, pulse signal simulation and the like, and the individual high-end application is required to reach 1ps level.
In time domain, the fundamental reason for signal jitter is that 1ps level jitter is realized by using 1000GSa/s sampling rate and DAC theoretically because the DAC sampling rate is too low, but it is obviously unrealistic to use 1000GHz DAC to generate arbitrary wave signal due to the principle of arbitrary wave signal generator and DAC performance, so how to realize 1ps jitter at low sampling rate is still the technical problem to be solved.
Disclosure of Invention
In order to overcome the defects of the prior art, the method for reducing the jitter of the arbitrary wave signal under various sampling rates is provided by the present disclosure, and the jitter reduction of the arbitrary wave signal with a low sampling rate can be realized by using the high sampling, filtering, interpolation or decimation method of the arbitrary wave digital wave.
The technical scheme adopted by the disclosure is as follows:
a method of reducing jitter in an arbitrary wave signal output, the method comprising the steps of:
sampling a target waveform signal by adopting a high sampling rate to obtain a digital waveform signal sample point with the high sampling rate;
carrying out low-pass filtering processing on the data waveform signal sample points;
and judging whether the high sampling rate of the data waveform signal sample points is an integral multiple of the corresponding DAC sampling rate, and performing integral multiple extraction or fractional multiple interpolation processing on the filtered data waveform signal sample points to obtain the target jitter data waveform signal of the corresponding DAC sampling rate.
Further, the high sampling rate is the inverse of the target jitter indicator.
Furthermore, a low-pass filtering method is adopted to carry out low-pass filtering processing on the digital waveform signal sample points, so that the bandwidth of the signal is limited, and the rising edge or the falling edge of the pulse signal and the broadband signal is smoothed.
Further, when the high sampling rate is an integer multiple of the DAC sampling rate, the integer multiple extraction processing is performed on the digital waveform signal sample points after the low-pass filtering processing.
Further, the step of the integer-multiple decimation processing includes:
and calculating the corresponding position of each sampling point in the digital waveform signal sample point with the high sampling rate according to the sampling interval time of the DAC, and selecting the digital waveform signal sample point at the position to directly output to obtain the target jitter digital waveform signal with the corresponding DAC sampling rate.
Further, when the high sampling rate is not an integral multiple of the DAC sampling rate, fractional interpolation processing is performed on the digital waveform signal sample points after the low-pass filtering processing.
Further, the step of fractional interpolation processing includes:
calculating the position of each sampling point in a digital waveform signal sample point with a high sampling rate according to the sampling interval time of the DAC;
and selecting effective sample points near the sample points of the digital waveform signal to perform low-pass filtering operation by adopting a sample point selective operation method according to the length of the digital interpolation filter, thereby obtaining a target jitter digital waveform signal of a corresponding DAC sampling rate.
An apparatus for reducing output jitter of an arbitrary wave signal, which is used for implementing the method for reducing output jitter of an arbitrary wave signal as described above, the apparatus comprising:
the data waveform signal sampling unit is used for sampling a target waveform signal by adopting a high sampling rate to obtain a digital waveform signal sample point with the high sampling rate;
the low-pass filtering unit is used for carrying out low-pass filtering processing on the data waveform signal sample points;
the integral multiple extraction unit is used for carrying out integral multiple extraction processing on the digital waveform signal sample points after the low-pass filtering processing when the DAC sampling rate corresponding to the arbitrary wave signal generator can divide the high sampling rate completely to obtain a target jitter digital waveform signal of the corresponding DAC sampling rate;
and the fractional-multiple interpolation unit is used for performing fractional-multiple interpolation processing on the digital waveform signal sample points after the low-pass filtering processing when the DAC sampling rate corresponding to the arbitrary wave signal generator cannot divide the high sampling rate completely to obtain the target jitter digital waveform signal of the corresponding DAC sampling rate.
Further, the method also comprises the following steps:
the selection unit is used for judging whether the high sampling rate of the data waveform signal sample points is the integral multiple of the corresponding DAC sampling rate or not, and when the high sampling rate is the integral multiple of the DAC sampling rate, the integral multiple extraction unit is selected to carry out integral multiple extraction processing on the digital waveform signal sample points after the low-pass filtering processing; and when the high sampling rate is not the integral multiple of the DAC sampling rate, selecting a fractional-multiple interpolation unit to select to carry out fractional-multiple interpolation processing on the digital waveform signal sample points after the low-pass filtering processing.
Through the technical scheme, the beneficial effects of the disclosure are that:
(1) the method reduces the jitter of the waveform signal by high sampling, low-pass filtering, fractional interpolation or integral multiple extraction of the digital waveform of the arbitrary wave, can realize the jitter reduction of the arbitrary wave signal with low sampling rate, and can reduce the jitter to the target jitter of 1 ps;
(2) the method is suitable for reducing the jitter of any wave signal with various sampling rates below 1000GSa/s, has obvious reducing effect, does not need to change hardware, does not occupy any extra hardware resource, adopts a digital waveform processing method, and can effectively solve the technical problem of low jitter signal generation in the technology of generating any wave signal;
(3) the digital waveform processing technology is adopted, the jitter is reduced before the DAC, the jitter is reduced under the condition of not changing the sampling rate of the DAC, the jitter index of an output signal can be obviously reduced, the digital waveform processing method is suitable for realizing the jitter reduction of any wave signal of all sampling rates, and the application range is wide.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure and are not to limit the disclosure.
FIG. 1 is a diagram illustrating the cause of jitter generation in an arbitrary wave signal;
FIG. 2 is a flow chart of a method of reducing arbitrary wave signal output jitter;
FIG. 3 is a schematic diagram of a digital waveform signal processing flow;
FIG. 4 is a schematic diagram of sample point selection operation.
Detailed Description
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
The existing method for reducing the jitter of any wave signal is mainly realized by improving the sampling rate of a DAC (digital-to-analog converter), the two indexes of the sampling rate and the digit of the DAC are mutually restricted, the digit of the DAC with high sampling rate is relatively low, the DAC with the highest sampling rate can reach more than 10GSa/s at present, but the corresponding digit is only 10, and the DAC with low digit sacrifices an important index of any wave signal: the vertical resolution, when low, will bring signal spurious, level resolution, weak signal analog ability, dynamic range and so on key index's deterioration. Moreover, the jitter index corresponding to the sampling rate of 10GSa/s is 100ps, as shown in FIG. 1, which does not meet the requirement of 1 ps. Therefore, the conventional jitter reduction method by increasing the sampling rate of the DAC cannot effectively reduce the jitter of the signal.
In order to reduce the jitter of the arbitrary wave signal with the low sampling rate to 1ps, the present embodiment provides a method for reducing the output jitter of the arbitrary wave signal, which adopts a digital waveform processing technology to reduce the jitter before the DAC, reduces the jitter without changing the sampling rate of the DAC, can significantly reduce the jitter index of the output signal, is suitable for the jitter reduction of the arbitrary wave signal with all sampling rates, and has a wide application range.
As shown in fig. 2 and 3, the method for reducing the output jitter of the arbitrary wave signal includes the following steps:
and S101, sampling the target waveform signal by adopting a high sampling rate to obtain a digital waveform signal sample point with the high sampling rate.
When the conventional arbitrary wave signal generator generates the sample points of the digital waveform signal, the sampling rate adopted is the DAC sampling rate, and the DAC sampling rate is limited, so that the waveform jitter index is deteriorated. The present embodiment generates the digital waveform signal sample points with a high sampling rate much higher than the DAC sampling rate, which depends on the designed jitter index and is the inverse of the jitter index, for example, when the designed jitter index is 1ps, the sampling rate used is 1/1 ps-1000 GHz-1000 GSa/s, which ensures that the time resolution of 1ps is maintained in the whole waveform signal processing of the present embodiment.
The present embodiment generates a digital waveform with an ultra-high sampling rate related to a target jitter index, and the lower the design jitter index is, the higher the sampling rate is, for example, the sampling rate corresponding to the design jitter index 1ps is 1000 GSa/s.
In the present embodiment, the sampling calculation is performed on the target waveform signal with an ultra-high sampling rate of 1000GSa/s instead of the conventional DAC sampling rate, and a digital waveform signal with a sampling rate of 1000GSa/s is generated, which is much higher than the conventional DAC sampling rate.
And S102, carrying out low-pass filtering processing on the data waveform signal sample points.
The conventional arbitrary wave signal generator mainly limits the bandwidth of a signal through an analog low-pass filter behind a DAC (digital-to-analog converter), and suppresses unnecessary spurs, at the moment, extra spurs and jitter signals can be generated due to waveform distortion caused by sampling errors of the DAC, and the external analog filter cannot reduce the jitter. In the embodiment, a low-pass filtering technology is adopted on the digital waveform signal, namely, the bandwidth of the signal is limited before the DAC, so that the severe level change of the sample point of the rising and falling edges of the high-frequency signal such as a pulse signal is effectively eliminated, the range from the sample point to the designed bandwidth is gentle, and the bandwidth of the system design is not exceeded before the DAC. Meanwhile, the input bandwidth of the digital filter for subsequent fractional-multiple interpolation operation cannot exceed the designed bandwidth, otherwise, interpolation operation mismatch can be caused to generate distortion, and the low-pass filter can effectively limit the input bandwidth of the fractional-multiple interpolation operation and ensure that the waveform processing of the embodiment reduces jitter in the designed bandwidth range.
For the sample point of the digital waveform signal with the sampling rate of 1000GSa/S obtained in step S101, the low-pass filtering unit performs low-pass filtering processing on the sample point of the digital waveform signal, and the low-pass filtering processing has the function of limiting the bandwidth of the signal and smoothing the rising or falling edge of the pulse signal and the broadband signal.
And S103, extracting or interpolating the filtered data waveform signal sample points to obtain a low-jitter data waveform signal with a corresponding DAC sampling rate.
After the digital waveform signal with the sampling rate of 1000GSa/s is processed by low-pass filtering, the digital waveform signal corresponding to the sampling rate of the DAC needs to be recovered. If the sampling rate of the DAC can be divided by 1000GSa/s, taking the sampling rate of the DAC as 1GSa/s as an example, the sampling points of the sampling rate of 1000GSa/s are extracted by integral multiple, namely one sampling point is extracted and output from the sampling points of the digital waveform signal every 1000 sampling points, and then the digital waveform signal of the sampling rate of 1GSa/s can be recovered; however, if the DAC sampling rate cannot be divided by 1000GSa/s, taking the DAC sampling rate 1.2GSa/s as an example, the sampling time corresponding to the 1.2GSa/s sampling rate will appear in the middle of the sampling times corresponding to two adjacent sample points of 1000GSa/s, which cannot be achieved by integer-multiple extraction, and the sample points of 1000GSa/s sampling rate need to be interpolated by fractional times to recover the digital waveform of 1.2GSa/s sampling rate, the fractional-multiple interpolation technique is implemented by adopting a digital filtering method, the passband of the filtering factor is designed to be 0.4 times of the sampling rate, and thus, sufficient interpolation output bandwidth can be ensured.
And for the digital waveform signal sample points subjected to the low-pass filtering processing in the step S102, selecting integral multiple extraction or fractional multiple interpolation processing according to the DAC sampling rate corresponding to the arbitrary wave signal generator, and realizing the conversion of the data waveform signal from the 1000GSa/S sampling rate to the DAC sampling rate.
And when the DAC sampling rate corresponding to the arbitrary wave signal generator can be divided by 1000GSa/s, selecting an integral multiple extraction unit to perform integral multiple extraction processing on the digital waveform signal sample points after the low-pass filtering processing.
The integral multiple extraction processing process specifically comprises the following steps:
and the integral multiple extraction unit calculates the corresponding position of each sampling point in the digital waveform signal sample point with the sampling rate of 1000GSa/s according to the sampling interval time of the DAC, and selects the digital waveform signal sample point at the position to directly output so as to obtain the low-jitter digital waveform signal suitable for the sampling rate of the DAC.
For the sample points generated at the sampling rate of 1000GSa/s, if such a high sampling rate is applied to all waveforms to generate sampling points and low-pass operation is performed, the operation amount is very large, which will cause the problems of slow operation rate, low operation efficiency, and the like. Taking the DAC sampling rate 1GSa/s as an example, after a low-pass filtered signal with the sampling rate of 1000GSa/s is generated, sample points with the sampling rate of 1GSa/s need to be extracted 1000 times, because the stage number of the low-pass filter has a certain range, only the sample points near each extracted point participate in the low-pass operation, and the rest sample points are not actually used, therefore, the present embodiment adopts a sample point selective operation method, only effective sample points near the time point corresponding to the DAC sampling rate are selected to participate in the low-pass filtering operation, and finally, a 1GSa/s sampling point is generated, which can significantly reduce the operation amount, and a sample point selective operation schematic diagram is shown in fig. 4.
And when the DAC sampling rate corresponding to the arbitrary wave signal generator cannot be divided by 1000GSa/s, selecting a fractional multiple interpolation unit to perform fractional multiple interpolation processing on the digital waveform signal sample points subjected to the low-pass filtering processing. The fractional interpolation processing process specifically comprises the following steps:
the fractional multiple interpolation unit firstly calculates the position of each sampling point in a digital waveform signal sample point with the sampling rate of 1000GSa/s according to the sampling interval time of the DAC, then selects an effective sample point near the digital waveform signal sample point to perform low-pass filtering operation according to the length of the digital interpolation filter to obtain a low-jitter digital waveform signal suitable for the sampling rate of the DAC, and discards other sample points which do not participate in the operation without operation processing.
The digital waveform signal output after interpolation or extraction processing in this embodiment is a low-jitter digital waveform signal suitable for the DAC sampling rate, and can be downloaded to hardware of an arbitrary wave signal generator to play instead of a normal digital waveform signal.
The method for reducing the output jitter of the arbitrary wave signal provided by the embodiment adopts a sampling rate far higher than a DAC sampling rate to generate a digital waveform, and then is realized by digital waveform processing methods such as digital waveform low-pass filtering, fractional interpolation or integer-multiple extraction; performing low-pass filtering processing on the digital waveform with a new sampling rate (for example, 1000GSa/s) by a low-pass filtering method to limit the bandwidth of the signal; recovering and generating a digital waveform corresponding to the DAC sampling rate by a fractional waveform interpolation technology under the condition that the DAC sampling rate cannot divide the new sampling rate; and for the condition that the DAC sampling rate can be divided into new sampling rates, the digital waveform corresponding to the DAC sampling rate is generated by recovering through an integral multiple extraction technology, invalid sample points are abandoned through a selective operation technology, only relevant sample data near the DAC sampling point is used for participating in operation, the waveform operation amount is greatly reduced, and the waveform operation speed is improved.
The present embodiment also provides an apparatus for reducing output jitter of an arbitrary wave signal, which is used to implement the method for reducing output jitter of an arbitrary wave signal as described above. As shown in fig. 3, the apparatus includes a processor including a data waveform signal sampling unit, a low-pass filtering unit, a selecting unit, an integer-times decimation unit, and a fractional-times interpolation unit, wherein:
and the data waveform signal sampling unit is used for sampling the target waveform signal by adopting a high sampling rate to obtain a digital waveform signal sample point with the high sampling rate.
In order to avoid the limitation of the DAC sampling rate and the resulting deterioration of the waveform jitter index, in this embodiment, the data waveform signal sampling unit generates the digital waveform by using an ultra-high sampling rate related to the target jitter index, and the sampling rate is higher when the design jitter index is lower, for example, the sampling rate corresponding to the design jitter index of 1ps is 1000 GSa/s.
In the embodiment, the data waveform signal sampling unit adopts an ultra-high sampling rate of 1000GSa/s to replace the conventional DAC sampling rate, performs sampling calculation on the target waveform signal, and generates a digital waveform signal with the sampling rate of 1000GSa/s, wherein the sampling rate of the digital waveform signal is far higher than the conventional DAC sampling rate.
And the low-pass filtering unit is used for carrying out low-pass filtering processing on the data waveform signal sample points.
In this example, before performing integer-multiple decimation or fractional-multiple interpolation, the digital waveform signal sample points are low-pass filtered by a low-pass filtering unit, which has the effect of limiting the bandwidth of the signal, smoothing the rising or falling edges of the pulse signal, the broadband signal.
The selection unit is used for judging whether the high sampling rate of the data waveform signal sample points is the integral multiple of the corresponding DAC sampling rate or not, and when the high sampling rate is the integral multiple of the DAC sampling rate, the integral multiple extraction unit is selected to carry out integral multiple extraction processing on the digital waveform signal sample points after the low-pass filtering processing; and when the high sampling rate is not the integral multiple of the DAC sampling rate, selecting a fractional-multiple interpolation unit to select to carry out fractional-multiple interpolation processing on the digital waveform signal sample points after the low-pass filtering processing.
And the integral multiple extraction unit calculates the corresponding position of each sampling point in the digital waveform signal sample point with the sampling rate of 1000GSa/s according to the sampling interval time of the DAC, and selects the digital waveform signal sample point at the position to directly output so as to obtain the low-jitter digital waveform signal suitable for the sampling rate of the DAC.
The integer-multiple decimation unit is specifically configured to:
and the integral multiple extraction unit calculates the corresponding position of each sampling point in the digital waveform signal sample point with the sampling rate of 1000GSa/s according to the sampling interval time of the DAC, and selects the digital waveform signal sample point at the position to directly output so as to obtain the low-jitter digital waveform signal suitable for the sampling rate of the DAC.
And the fractional multiple interpolation unit is used for selecting the fractional multiple interpolation unit to perform fractional multiple interpolation processing on the digital waveform signal sample points after the low-pass filtering processing when the DAC sampling rate corresponding to the arbitrary wave signal generator cannot be divided by 1000 GSa/s. The fractional interpolation unit is specifically configured to:
and the fractional-multiple interpolation unit is used for performing fractional-multiple interpolation processing on the digital waveform signal sample points after the low-pass filtering processing when the DAC sampling rate corresponding to the arbitrary wave signal generator cannot divide the high sampling rate completely to obtain the target jitter digital waveform signal of the corresponding DAC sampling rate.
The device for reducing the output jitter of the arbitrary wave signal provided by the embodiment has a good jitter reduction effect, can be reduced to 1ps, and can remarkably reduce the jitter of an arbitrary waveform at an arbitrary sampling rate; hardware resources are not occupied, and any processing flow of hardware is not changed; the method is suitable for jitter reduction processing of all arbitrary wave signal generators, and has a wide application range.
Although the embodiments of the present invention have been described with reference to the accompanying drawings, it is not intended to limit the scope of the present invention, and it should be understood by those skilled in the art that various modifications and variations can be made without inventive efforts by those skilled in the art based on the technical solution of the present invention.
Claims (5)
1. A method for reducing jitter in an arbitrary wave signal output, comprising the steps of:
sampling a target waveform signal by adopting a high sampling rate to obtain a digital waveform signal sample point with the high sampling rate;
carrying out low-pass filtering processing on the data waveform signal sample points;
judging whether the high sampling rate of the data waveform signal sample points is the integral multiple of the corresponding DAC sampling rate, and when the high sampling rate is the integral multiple of the DAC sampling rate, performing integral multiple extraction processing on the digital waveform signal sample points after the low-pass filtering processing; when the high sampling rate is not the integral multiple of the DAC sampling rate, fractional interpolation processing is carried out on the digital waveform signal sample points after low-pass filtering processing; finally, obtaining a target jitter data waveform signal of the corresponding DAC sampling rate;
the step of the integer-multiple decimation processing includes:
calculating the corresponding position of each sampling point in the digital waveform signal sample point with a high sampling rate according to the sampling interval time of the DAC, and selecting the digital waveform signal sample point at the position to directly output to obtain a target jitter digital waveform signal with a corresponding DAC sampling rate;
the step of fractional interpolation processing includes:
calculating the position of each sampling point in a digital waveform signal sample point with a high sampling rate according to the sampling interval time of the DAC; and selecting effective sample points near the sample points of the digital waveform signal to perform low-pass filtering operation by adopting a sample point selective operation method according to the length of the digital interpolation filter, thereby obtaining a target jitter digital waveform signal of a corresponding DAC sampling rate.
2. The method of reducing jitter in the output of an arbitrary-wave signal as set forth in claim 1, wherein said high sampling rate is the inverse of a target jitter indicator.
3. The method according to claim 1, wherein the low-pass filtering is performed on the digital waveform signal sample points to limit the bandwidth of the signal, to smooth the rising or falling edges of the pulse signal, or to smooth the falling edges of the wideband signal.
4. An apparatus for reducing output jitter of an arbitrary wave signal, which is used for implementing the method for reducing output jitter of an arbitrary wave signal according to any one of claims 1 to 3, comprising:
the data waveform signal sampling unit is used for sampling a target waveform signal by adopting a high sampling rate to obtain a digital waveform signal sample point with the high sampling rate;
the low-pass filtering unit is used for carrying out low-pass filtering processing on the data waveform signal sample points;
the integral multiple extraction unit is used for carrying out integral multiple extraction processing on the digital waveform signal sample points after the low-pass filtering processing when the DAC sampling rate corresponding to the arbitrary wave signal generator can divide the high sampling rate completely to obtain a target jitter digital waveform signal of the corresponding DAC sampling rate;
and the fractional-multiple interpolation unit is used for performing fractional-multiple interpolation processing on the digital waveform signal sample points after the low-pass filtering processing when the DAC sampling rate corresponding to the arbitrary wave signal generator cannot divide the high sampling rate completely to obtain the target jitter digital waveform signal of the corresponding DAC sampling rate.
5. The apparatus for reducing jitter of an arbitrary wave signal output according to claim 4, further comprising:
the selection unit is used for judging whether the high sampling rate of the data waveform signal sample points is the integral multiple of the corresponding DAC sampling rate or not, and when the high sampling rate is the integral multiple of the DAC sampling rate, the integral multiple extraction unit is selected to carry out integral multiple extraction processing on the digital waveform signal sample points after the low-pass filtering processing; and when the high sampling rate is not the integral multiple of the DAC sampling rate, selecting a fractional-multiple interpolation unit to select to carry out fractional-multiple interpolation processing on the digital waveform signal sample points after the low-pass filtering processing.
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Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101512908A (en) * | 2006-08-01 | 2009-08-19 | 惠瑞捷（新加坡）私人有限公司 | Asynchronous Sigma-Delta digital-to-analog converter |
| CN102857223A (en) * | 2011-07-01 | 2013-01-02 | 英飞凌科技股份有限公司 | Method and system for jitter reduction |
| CN103580656A (en) * | 2013-10-11 | 2014-02-12 | 中国电子科技集团公司第四十一研究所 | Triggering vibration real-time correction circuit and method in random sampling process |
| CN104055512A (en) * | 2014-07-01 | 2014-09-24 | 深圳市岩尚科技有限公司 | Method for fast resampling electrocardiogram data |
| CN104218919A (en) * | 2014-09-15 | 2014-12-17 | 中国电子科技集团公司第三十八研究所 | Fractional-multiple interpolation shaping filter and implementation method thereof |
| CN104796151A (en) * | 2014-01-21 | 2015-07-22 | 成都国恒空间技术工程有限公司 | Sampling rate conversion device and method with continuously variable bandwidth |
| CN105610416A (en) * | 2015-12-18 | 2016-05-25 | 中国电子科技集团公司第四十一研究所 | Low-distortion audio signal generation method |
| CN206208940U (en) * | 2016-08-24 | 2017-05-31 | 固纬电子(苏州)有限公司 | Any ripple output device |
| CN107025918A (en) * | 2016-02-01 | 2017-08-08 | 爱思开海力士有限公司 | Shaking detection circuit and use its semiconductor system |
| CN107613877A (en) * | 2015-04-01 | 2018-01-19 | 微拉声学公司 | The method and system for carrying out coded-excitation imaging systems for estimating and recalling collection by impulse response |
| CN107800409A (en) * | 2017-11-16 | 2018-03-13 | 湖南工业大学 | Accumulation formula disturbing pulse filter method |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10268015A (en) * | 1997-03-26 | 1998-10-09 | Kenwood Corp | Device for generating calibration signal for measuring jitter |
| CN101262240A (en) * | 2008-04-25 | 2008-09-10 | 浙江大学 | An easy-to-realize method and device for full digital frequency conversion |
| CN102904653A (en) * | 2012-10-24 | 2013-01-30 | 复旦大学 | Method for measuring signal EVM (Error Vector Magnitude) in numeric field and realizing device |
| JP2014134498A (en) * | 2013-01-11 | 2014-07-24 | Advantest Corp | Detection device, wafer and electronic device |
| US10480943B2 (en) * | 2016-02-04 | 2019-11-19 | Honeywell International Inc. | Systems and methods for noise and drift calibration using dithered calibration |
-
2018
- 2018-12-26 CN CN201811603205.3A patent/CN109655644B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101512908A (en) * | 2006-08-01 | 2009-08-19 | 惠瑞捷（新加坡）私人有限公司 | Asynchronous Sigma-Delta digital-to-analog converter |
| CN102857223A (en) * | 2011-07-01 | 2013-01-02 | 英飞凌科技股份有限公司 | Method and system for jitter reduction |
| CN103580656A (en) * | 2013-10-11 | 2014-02-12 | 中国电子科技集团公司第四十一研究所 | Triggering vibration real-time correction circuit and method in random sampling process |
| CN104796151A (en) * | 2014-01-21 | 2015-07-22 | 成都国恒空间技术工程有限公司 | Sampling rate conversion device and method with continuously variable bandwidth |
| CN104055512A (en) * | 2014-07-01 | 2014-09-24 | 深圳市岩尚科技有限公司 | Method for fast resampling electrocardiogram data |
| CN104218919A (en) * | 2014-09-15 | 2014-12-17 | 中国电子科技集团公司第三十八研究所 | Fractional-multiple interpolation shaping filter and implementation method thereof |
| CN107613877A (en) * | 2015-04-01 | 2018-01-19 | 微拉声学公司 | The method and system for carrying out coded-excitation imaging systems for estimating and recalling collection by impulse response |
| CN105610416A (en) * | 2015-12-18 | 2016-05-25 | 中国电子科技集团公司第四十一研究所 | Low-distortion audio signal generation method |
| CN107025918A (en) * | 2016-02-01 | 2017-08-08 | 爱思开海力士有限公司 | Shaking detection circuit and use its semiconductor system |
| CN206208940U (en) * | 2016-08-24 | 2017-05-31 | 固纬电子(苏州)有限公司 | Any ripple output device |
| CN107800409A (en) * | 2017-11-16 | 2018-03-13 | 湖南工业大学 | Accumulation formula disturbing pulse filter method |
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