CN106849966A - A kind of wideband Larger Dynamic four-way digital receiver - Google Patents
A kind of wideband Larger Dynamic four-way digital receiver Download PDFInfo
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- CN106849966A CN106849966A CN201710209115.5A CN201710209115A CN106849966A CN 106849966 A CN106849966 A CN 106849966A CN 201710209115 A CN201710209115 A CN 201710209115A CN 106849966 A CN106849966 A CN 106849966A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
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- Circuits Of Receivers In General (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
The invention belongs to technical field of radio, more particularly to a kind of wideband Larger Dynamic four-way digital receiver.The present invention includes the identical and separate each other intermediate-freuqncy signal receiving unit of four groups of structures, and clock distributor, programable downConverter, FPGA control chip, eprom memory, driver, the present invention can be exported all the way to four road I/Q data-signals according to actual needs, be integrated into four independent broad-band channels in a circuit by the present invention, the function of four railway digital down coversions is capable of achieving in an integrated chip, it is saved greatly resource, save hardware cost, and circuit structure is simple, integrated level is high, it is with low cost, small volume, the present invention has selected general component, simplify circuit design.
Description
Technical field
The invention belongs to technical field of radio, more particularly to a kind of wideband Larger Dynamic four-way digital receiver.
Background technology
Propose that to today have been developed 25 years, its core is can using Kai Fang ﹑ from software-defined radio concept in 1992
The hardware that Kuo Zhan ﹑ structures are simplified as general-purpose platform, radio function as much as possible with Ke Chong Gou ﹑ scalable component
Change software to realize.Digital receiver is one of software radio core technology, it is possible to use general platform mating component
Software realizes multi-field application.
The usual circuit structure of digital receiver of the prior art is complicated, and hardware cost is too high, and volume is big, therefore needs badly and carry
Go out a kind of circuit structure simple, integrated level is high, with low cost, the digital receiver of small volume.
The content of the invention
The present invention is in order to overcome the above-mentioned deficiencies of the prior art, there is provided a kind of wideband Larger Dynamic four-way digital received
Machine, the present invention has selected general component, simplifies circuit design, and circuit structure of the invention is simple, and integrated level is high,
It is with low cost, small volume.
To achieve the above object, present invention employs following technical measures：
A kind of wideband Larger Dynamic four-way digital receiver includes that four groups of structures are identical and separate each other
Intermediate-freuqncy signal receiving unit, the signal input part of intermediate-freuqncy signal receiving unit is all connected with the signal of clock distributor described in four groups
Output end, the signal input part connection clock signal of the clock distributor, the signal of intermediate-freuqncy signal receiving unit described in four groups
Output end is all connected with the signal input part of programable downConverter, double between the programable downConverter and FPGA control chip
To communication connection, two-way communication link between the FPGA control chip and eprom memory, the signal of FPGA control chip is defeated
Go out the signal input part of end connection driver, the signal output part of the driver is exported all the way to four road I/Q data-signals.
Preferably, the intermediate-freuqncy signal receiving unit includes radio-frequency transformer, analog-digital converter and d type flip flop, wherein,
Radio-frequency transformer, it is used to for intermediate-freuqncy signal to be converted into both-end differential signal, and the both-end differential signal is defeated
Deliver to the signal input part of analog-digital converter；
Analog-digital converter, its signal input part signal output part, signal of clock distributor respectively with radio-frequency transformer
Output end is connected, and the signal output part of the analog-digital converter is connected with the signal input part of d type flip flop；
D type flip flop, its signal output part connects the signal input part of programable downConverter.
Preferably, the radio-frequency transformer includes the DT4-1WT chips of Mini-Circuits companies of U.S. production, described
The connection intermediate-freuqncy signal of pin 1 of DT4-1WT chips, pin 3 is grounded, and pin 4 and pin 6 are all connected with analog-digital converter, and pin 5 connects
It is grounded after connecing electric capacity.
Preferably, the analog-digital converter includes the AD6645 chips of ADI companies of U.S. production, the AD6645 chips
Pin 5 and pin 6 are all connected with clock distributor, 52,14 data output pins of pin of AD6645 chips, 1 outrange position
Output pin is indicated to be all connected with d type flip flop.
Further, the d type flip flop selects the d type flip flop chip of the model 74LCX16374MEA of 16, described
The pin 52 of AD6645 chips connects the CP1 pins and CP2 pins of 74LCX16374MEA, and 14 data of AD6645 chips are defeated
Go out pin, 1 outrange position and indicate output pin to be connected respectively 15 input pins of 74LCX16374MEA,
The signal output pin connection programable downConverter of 74LCX16374MEA.
Further, the clock distributor includes the chip of model MC100EL14.
Further, the programable downConverter includes the chip of model ISL5416KI.
Further, the FPGA control chip includes the chip of model EP20K200EPC484.
Further, the eprom memory at least includes an EPC2LI20 chip.
Further, the driver includes the chip of model 74FCT163245, the 74FCT163245 chips
For exporting all the way to four road I/Q data-signals.
The beneficial effects of the present invention are：
1), the present invention includes the identical and separate each other intermediate-freuqncy signal receiving unit of four groups of structures, with
And clock distributor, programable downConverter, FPGA control chip, eprom memory, driver, the present invention can be according to reality
Border needs output all the way to four road I/Q data-signals, and be integrated into four independent broad-band channels in a circuit by the present invention,
The function of four railway digital down coversions is capable of achieving in one integrated chip, resource is saved greatly, hardware cost is saved, and
And circuit structure is simple, integrated level is high, with low cost, small volume, and the present invention has selected general component, simplifies circuit and sets
Meter.
2), the eprom memory at least includes an EPC2LI20 chip, for by the control journey of FPGA control chip
Sequence is preserved, if a piece of EPC2LI20 chip-storeds space not enough, will can be made using multi-disc EPC2LI20 chip parallel connections
With, therefore memory space of the invention is big, it is easy to use.
3), the radio-frequency transformer includes the DT4-1WT chips of Mini-Circuits companies of U.S. production, analog-to-digital conversion
Device includes the AD6645 chips of ADI companies of U.S. production, D of the d type flip flop from the model 74LCX16374MEA of 16
Trigger chip, the programable downConverter includes the chip of model ISL5416KI, and the eprom memory is at least wrapped
An EPC2LI20 chip is included, the FPGA control chip includes the chip of model EP20K200EPC484, the driver
Chip including model 74FCT163245, said chip is general component, and the part of above-mentioned multiple specific models is mutual
It is engaged, realizes optimal design of the invention.
Brief description of the drawings
Fig. 1 is structural principle block diagram of the invention；
Fig. 2 is the pin configuration figure of the AD6645 chips of analog-digital converter.
Reference implication in figure is as follows：
10-intermediate-freuqncy signal receiving unit 11-radio-frequency transformer, 12-analog-digital converter
13-d type flip flop, 20-clock distributor, 30-programable downConverter
40-FPGA control chip, 50-eprom memory, 60-driver
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
As shown in figure 1, a kind of wideband Larger Dynamic four-way digital receiver include four groups of structures it is identical and each other it
Between separate intermediate-freuqncy signal receiving unit 10, when the signal input part of intermediate-freuqncy signal receiving unit 10 is all connected with described in four groups
The signal output part of clock distributor 20, the signal input part connection clock signal of the clock distributor 20, intermediate frequency described in four groups
The signal output part of signal receiving unit 10 is all connected with the signal input part of programable downConverter 30, the programmable down coversion
Two-way communication link between device 30 and FPGA control chip 40, it is double between the FPGA control chip 40 and eprom memory 50
To communication connection, the signal output part of FPGA control chip 40 connects the signal input part of driver 60, the driver 60
Signal output part is exported all the way to four road I/Q data-signals.
The intermediate-freuqncy signal receiving unit 10 includes radio-frequency transformer 11, analog-digital converter 12 and d type flip flop 13, described
Radio-frequency transformer 11 is used to for intermediate-freuqncy signal to be converted into both-end differential signal, and the both-end differential signal is delivered into modulus turn
The signal input part of parallel operation 12；The signal input part of the analog-digital converter 12 respectively with the signal output of radio-frequency transformer 11
End, the signal output part of clock distributor 20 are connected, the signal output part of the analog-digital converter 12 and the signal of d type flip flop 13
Input is connected；The signal output part of the d type flip flop 13 connects the signal input part of programable downConverter 30.
Specifically, the clock signal is 80MHz and is single ended input.
The signal input part connection intermediate-freuqncy signal of the radio-frequency transformer 11, according to reality output needs, 4 radio frequency transformations
Intermediate-freuqncy signal is become differential output signal and is input into analog-digital converter 12 by the selection connection intermediate-freuqncy signal of device 11, radio-frequency transformer 11
Signal input part；
The radio-frequency transformer 11 includes the DT4-1WT chips of Mini-Circuits companies of U.S. production, the DT4-
The connection intermediate-freuqncy signal of pin 1 of 1WT chips, pin 3 is grounded, and pin 4 and pin 6 are all connected with analog-digital converter 12, and pin 5 is connected
It is grounded after electric capacity, the 2~755MHz of working frequency of the DT4-1WT chips.
As shown in Fig. 2 the analog-digital converter 12 includes the AD6645 chips of ADI companies of U.S. production, the AD6645
The pin 5 and pin 6 of chip are all connected with clock distributor 20,52,14 data output pins of pin of AD6645 chips, 1
Outranging position indicates output pin to be all connected with d type flip flop 13；
AD6645 chips are the analog-digital converters of a high speed, high-performance, 14 single-chips, and if sampling frequency highest can
To 200MHz, multitone SFDR reaches 100dBFS in the second Nyquist spy's frequency band, and signal to noise ratio is more than 72dB, two
Complement on n n digital output format.The differential clock signal that clock distributor 20 is sent AD6645 chips in rising edge start to turn
Change, the pin 36 of AD6645 chips is least significant bit output pin, and pin 51 is highest significant position output pin, the He of pin 37~41
Pin 44~50 is middle 12 significance bit output pins, and the pin 52 of AD6645 chips is data ready output pin, AD6645's
Pin 32 is to outrange position to indicate pin.
The d type flip flop 13 selects the d type flip flop chip of the model 74LCX16374MEA of 16, the AD6645 cores
The pin 52 of piece connects the CP1 pins and CP2 pins of 74LCX16374MEA, 14 data output pins, 1 of AD6645 chips
Position outranges position and indicates output pin to be connected respectively 15 input pins of 74LCX16374MEA, 74LCX16374MEA's
Signal output pin connects programable downConverter 30.
The programable downConverter 30 includes the chip of model ISL5416KI；The eprom memory 50 is at least wrapped
An EPC2LI20 chip is included, for the control program of FPGA control chip to be preserved, if a piece of EPC2LI20 chips
Insufficient memory, can be used in parallel using multi-disc EPC2LI20 chips, therefore memory space of the invention is greatly, user
Just.The FPGA control chip 40 includes the chip of model EP20K200EPC484；The driver 60 includes model
The chip of 74FCT163245, the 74FCT163245 chips are used to export all the way to four road I/Q data-signals.
Specifically, EP20K200EPC484 chips mainly complete the control to ISL5416KI chips, and ISL5416KI
16, four tunnel that chip is sent i/q signal rearranges output, and output signal after 74FCT163245 chip drives by stablizing defeated
Go out.
ISL5416KI chips are four-way wideband digital low-converters, and original wave filter design can be independent four
Broad-band channel is integrated into a circuit, and all of post-processing function is put together carries out at a complete channelizing
Reason；Then ISL5416KI chips are filtered and extract signal from AD6645 chip receiving wide-band signals to broadband signal,
Each passage of ISL5416KI chips include digital oscillator, digital mixer, multiple digital filters, one
Automatic compensation amplifier and a multilayer sampling filter, 14 signals that 4 road d type flip flops 13 are sent and 1 outrange position
Indication signal is respectively fed to AIN3~AIN16 pins, AIN0 pins, 4 in 4 groups of 16 input pins of ISL5416KI chips
The data ready output pin of road analog-digital converter AD6645 chips connects the clock input pin of ISL5416KI chips respectively
CLKA, CLKB, CLKC and CLKD.All of passage can be independently programmable and real-time update, and each passage can be selected
Four groups of any one group for the treatment of of numeral input bus, 16 i/q signals that can be parallel or after string shape output treatment.
The chip model of the clock distributor 20 is MC100EL14, has saved design cost, and 1 tunnel is sent in outside
The clock signal of 80MHz is transformed into differential output signal and is converted into 5 road clock differential output signals.
When the sine wave signal for being input into 10.1MHz all the way, 10MHz intermediate frequencies, 80MHz clock signals obtain 16 I/Q, use
MATLAB and LABVIEW software analysis I/Q signal to noise ratios are more than 70dB, and mirror phase degree of suppression is more than 90dB, therefore the present invention is constructed
The hardware general-purpose platform of the extremely wide four-way digital receiver of one purposes, ultra-wide if sampling frequency of the invention is up to
200MHz, big multitone SFDR reaches 100dBFS, and high s/n ratio is more than 72dB, realizes 16 I/Q data letters of multichannel
The output of number flexible combination.
Claims (10)
1. a kind of wideband Larger Dynamic four-way digital receiver, it is characterised in that：Including four groups of structures it is identical and each other it
Between separate intermediate-freuqncy signal receiving unit (10), the signal input part of intermediate-freuqncy signal receiving unit (10) connects described in four groups
Connect the signal output part of clock distributor (20), the signal input part connection clock signal of the clock distributor (20), four groups
The signal output part of the intermediate-freuqncy signal receiving unit (10) is all connected with the signal input part of programable downConverter (30), described
Two-way communication link between programable downConverter (30) and FPGA control chip (40), the FPGA control chip (40) with
Two-way communication link between eprom memory (50), signal output part connection driver (60) of FPGA control chip (40)
Signal input part, the signal output part of the driver (60) is exported all the way to four road I/Q data-signals.
2. a kind of wideband Larger Dynamic four-way digital receiver as claimed in claim 1, it is characterised in that：The intermediate-freuqncy signal
Receiving unit (10) includes radio-frequency transformer (11), analog-digital converter (12) and d type flip flop (13), wherein,
Radio-frequency transformer (11), it is used to for intermediate-freuqncy signal to be converted into both-end differential signal, and the both-end differential signal is defeated
Deliver to the signal input part of analog-digital converter (12)；
Analog-digital converter (12), its signal input part signal output part, clock distributor respectively with radio-frequency transformer (11)
(20) signal output part is connected, the signal output part of the analog-digital converter (12) and the signal input part of d type flip flop (13)
It is connected；
D type flip flop (13), the signal input part of its signal output part connection programable downConverter (30).
3. a kind of wideband Larger Dynamic four-way digital receiver as claimed in claim 2, it is characterised in that：The radio frequency transformation
The DT4-1WT chips that device (11) is produced including Mini-Circuits companies of the U.S., during the pin 1 of the DT4-1WT chips is connected
Frequency signal, pin 3 is grounded, and pin 4 and pin 6 are all connected with analog-digital converter (12), are grounded after the connection electric capacity of pin 5.
4. a kind of wideband Larger Dynamic four-way digital receiver as claimed in claim 3, it is characterised in that：The analog-to-digital conversion
The AD6645 chips that device (12) is produced including ADI companies of the U.S., the pin 5 and pin 6 of the AD6645 chips are all connected with clock
Distributor (20), 52,14 data output pins of pin of AD6645 chips, 1 outrange position indicate output pin be all connected with D
Trigger (13).
5. a kind of wideband Larger Dynamic four-way digital receiver as claimed in claim 4, it is characterised in that：The d type flip flop
(13) the d type flip flop chip of the model 74LCX16374MEA of 16, the pin 52 of the AD6645 chips is selected to connect
The CP1 pins and CP2 pins of 74LCX16374MEA, 14 data output pins of AD6645 chips, 1 outrange position instruction
Output pin is connected respectively 15 input pins of 74LCX16374MEA, and the signal output pin of 74LCX16374MEA connects
Connect programable downConverter (30).
6. a kind of wideband Larger Dynamic four-way digital receiver as claimed in claim 5, it is characterised in that：The clock distribution
The chip of device (20) including model MC100EL14.
7. a kind of wideband Larger Dynamic four-way digital receiver as claimed in claim 6, it is characterised in that：It is described it is programmable under
The chip of frequency converter (30) including model ISL5416KI.
8. a kind of wideband Larger Dynamic four-way digital receiver as claimed in claim 7, it is characterised in that：The FPGA controls
The chip of chip (40) including model EP20K200EPC484.
9. a kind of wideband Larger Dynamic four-way digital receiver as claimed in claim 8, it is characterised in that：The EPROM is deposited
Reservoir (50) at least includes an EPC2LI20 chip.
10. a kind of wideband Larger Dynamic four-way digital receiver as claimed in claim 9, it is characterised in that：The driver
(60) including the chip of model 74FCT163245, the 74FCT163245 chips are used to export all the way to four road I/Q data
Signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201710209115.5A CN106849966B (en) | 2017-03-31 | 2017-03-31 | Wide-band large dynamic four-channel digital receiver |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710209115.5A CN106849966B (en) | 2017-03-31 | 2017-03-31 | Wide-band large dynamic four-channel digital receiver |
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| Publication Number | Publication Date |
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| CN106849966A true CN106849966A (en) | 2017-06-13 |
| CN106849966B CN106849966B (en) | 2023-04-07 |
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