CN100411310C - Medium frequency signal processing method and circuit in receiver - Google Patents
Medium frequency signal processing method and circuit in receiver Download PDFInfo
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- CN100411310C CN100411310C CNB031139833A CN03113983A CN100411310C CN 100411310 C CN100411310 C CN 100411310C CN B031139833 A CNB031139833 A CN B031139833A CN 03113983 A CN03113983 A CN 03113983A CN 100411310 C CN100411310 C CN 100411310C
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Abstract
The present invention relates to an intermediate frequency signal processing method and a circuit in a basic unit of a receiver in a software definition radio system, which adopts a resampling method and implements a software definition radio thought. The circuit comprises an equalizer E, a plurality of single-channel processing circuits and a combiner. The method comprises a multichannel parallel processing process which is used for single-mode and multi-mode signal processing. Each of the single-channel processing circuits comprises an analog/digital converter ADC, a digital down conversion processing circuit DDC and a resampling interpolation circuit RS. The present invention has the resampling method that a resampling treatment is conducted for an output digital signal DB by first sampling, a signal DO by second sampling of an intermediate frequency analog signal is obtained, and the sampling frequency of the signal DO by the second sampling is higher than that of the signal DB by the first sampling. The method and the circuit can improve the velocity of a baseband of outputting a signal and expand the bandwidth of the baseband, the oversampling signal output of a broadband is realized when the requirement of general intermediate frequency signal processing is met, and simultaneously, the cost of equipment is reduced.
Description
Technical field
The present invention relates to radiotechnics, the communication technology and microelectronics and software engineering, specifically, the radio frequency and the intermediate-freuqncy signal process field that relate to radio communication more particularly, relate to intermediate-freuqncy signal processing method and circuit in a kind of software-defined radio system receiver elementary cell.
Background technology
Traditional radio is meant the radio of being realized its communication function by hardware.Radiotechnics develops and successively analog radio, digital radio and programmable digital radio have occurred, and digital radio and programmable digital radio mainly also are to realize its communication function by hardware.The development of DSP, FPGA and general processor hardware such as (GP) and the introducing of PC bus concept cause the major transformation of radio architecture, make radiotechnics combine the new stage that entered with computer technology; What formed system at present is that software-defined radio Software Defined Radio is called for short SDR, can enough software controls and configuration process unit.The elementary cell of SDR structure comprises dual-mode antenna and feeder line, radio frequency sender, radio frequency receiver, high-speed figure link, general baseband digital signal processing platform and various software bag.Software all will leave in the baseband digital signal processing platform, or load into by network, comprise Control Software Package: as the base station is configured, is provided with, the software of management etc.; Physical layer software bag: its physical layer software will be arranged to each standard and standard; High layer software: respectively to each standard and standard; System interface software: to the multiple interfaces requirement.
In the present wireless communication standard, the bandwidth of each carrier wave from 25kHz (TACS) to 5MHz (WCDMA); Working frequency range is from 800MHz to 3GHz; With the emission everyway different technical indicators is arranged in the radio frequency reception.This is the most challenging work to SDR multi-mode equipment.Broadband programmable, configurable radio frequency and intermediate frequency technology are major issues that must solve, the level of depending merely on present radio frequency components and parts also can't solve (also will further specify below), and the initial stage SDR equipment that proposes, not a complete SDR equipment, also may require to change radio-frequency module when supporting many standards, radio frequency and intermediate frequency technological core and flesh and blood relate to signal processing.Signal processing is the most basic technology of the communications field, the signal processing requirement of the communications field is in real time with accurate, tight with combination of hardware, signal processing in general sense is meant to be utilized device, combines the device of software or by the device of software control signal is handled in real time in frequency domain.
Intermediate-freuqncy signal in the radio frequency of radio communication and the intermediate-freuqncy signal process field is handled, the intermediate-freuqncy signal that is divided into sender and receiver is handled, main realize between baseband signal and the radiofrequency signal on/functions such as down-conversion, frequency tuning, frequency-tracking, intermediate frequency filtering, phase control, gain controlling, modulating/demodulating, the intermediate-freuqncy signal treatment system of receiver and circuit are to realize down-conversion and demodulation function.
Below, advance broadband programmable, configurable radio frequency and the present implementation method of intermediate frequency technology in the explanation receiver: the typical signal processing circuit of intermediate frequency that receiver includes, as shown in Figure 1, its input is intermediate frequency analog input signal IF, and its output is baseband digital signal DB; Comprise that Digital Down Convert signal processing circuit Digital Down Converter is called for short DDC and analog/digital converter Analog-to-Digital Converter is called for short ADC, the work clock of DDC and ADC is defined as DDC CLOCK respectively and is called for short DDCK and ADC CLOCK abbreviation ADCK.
The intermediate-freuqncy signal processing procedure of circuit shown in Figure 1 is: 1, ADC carries out the digitlization conversion to analog intermediate frequency input signal IF under the driving that given speed sampling clock is given work clock ADCK.When ADCK is greater than or less than 2 times of IF frequency band, ADC IF is carried out over-sampling or the digitlization of owing to sample conversion after obtain digital intermediate frequency signal DIF, ADC again with the digital intermediate frequency signal DIF that obtains by ADC sampling clock 1/N (N=1,2,, speed N) is input to DDC synchronously.2, DDC imports under the driving that gated clock is work clock ADCK in given numeral the digital intermediate frequency signal DIF that imports is carried out real-time signal processing, realize the down-conversion of digital intermediate frequency signal to baseband digital signal, functions such as frequency tuning, frequency-tracking, intermediate frequency filtering, phase control, gain controlling, demodulation are exported digital signal DB at last.In this circuit, the high and low output bandwidth that has determined the signal handling capacity of DDC and handled the back digital signal of the work clock DDCK of DDC, for maximum processing capability and the maximum output bandwidth that effectively utilizes DDC, adopted with ADCK mutually the clock of same rate as DDC numeral input gated clock and work clock.
Because semiconductor integrated circuit technology limitation, make work clock speed and the I/O speed of ADC and DDC limited, and DDC is also limited to the speed of depression of order processing of digital signal etc., it is limited causing single channel DDC maximum number signal output speed, the bandwidth of the baseband digital signal IF that is exported after DDC handles also is limited, thereby limited the bandwidth of the baseband digital signal IF after DDC handles, this bandwidth only can satisfy the requirement of common baseband digital signal output; And dependence has the speed of the analog/digital converter (ADC) that is used for designing the radio communication receiver and the processing speed and the ability of digital down converter (DDC) now, also can not satisfy the requirement of the high intermediate frequency signal processing in the broadband of receiver in the Wireless Telecom Equipment far away, particularly in the application of the wideband digital signal output that needs the high magnification sampling.Thereby the present implementation method of receiver is in-problem in SDR broadband programmable, configurable radio frequency and the intermediate frequency technology, only can satisfy the requirement that common analog intermediate frequency input signal is handled and common baseband signal is exported.On the other hand, the signal processing circuit of intermediate frequency of the receiver in the traditional wireless communication equipment and system, it normally is specific wireless communication system design, have fixing frequency source and clock source, and can not change, thereby they can only be used in the system of AD HOC, particular frequency carrier and specific bandwidth.
Simultaneously, the patent application " a kind of intermediate-freuqncy signal processing method and circuit " that proposes in advance the applicant has solved the corresponding problem that exists that has problems with the present invention in sender in receiver, it provides a kind of intermediate-freuqncy signal processing method and circuit to sender, can be under the requirement of satisfying common intermediate-freuqncy signal processing, can also export the Wideband Intermediate Frequency analog signal, further in order to the needs that satisfy different mode, carrier frequency or bandwidth and the requirement of different wireless communication system, round Realization SDR.
Summary of the invention
The technical problem to be solved in the present invention is, how to implement SDR thought, providing a kind of intermediate-freuqncy signal processing method and circuit to receiver under the technical conditions at present, can be under the requirement of satisfying common analog intermediate frequency signal processing, can also realize the output of broadband high magnification over-sampling baseband digital signal or Wideband Intermediate Frequency digital signal, further in order to the needs that satisfy different mode, carrier frequency or bandwidth and the requirement of different wireless communication system, round Realization SDR.
The technical problem of a corresponding method of the present invention solves like this, utilize software and General Porcess Unit, use digital if technology, structure is applied in the intermediate-freuqncy signal processing method in the receiver, adopt method for resampling, comprised the general multi-channel parallel handling process that is used for input analog intermediate frequency signal IF is converted into baseband digital signal, broadband high magnification over-sampling baseband digital signal or Wideband Intermediate Frequency digital signal DO output; Described method for resampling is that the digital signal DB to once sampling output resamples and handles the sub-sampled signal DO that obtains described analog intermediate frequency signal, and the sample frequency of described sub-sampled signal DO is higher than the sample frequency of a described sampled signal DB; The analog intermediate frequency signal that described analog intermediate frequency signal IF is any monotype, single carrier frequency, any monotype, overloading synthetic analog intermediate frequency signal or the synthetic analog intermediate frequency signal of any multi-mode frequently.
According to processing method provided by the invention, it is characterized in that described multi-channel parallel handling process adopts the synthetic method for resampling of ALTERNATE SAMPLING, may further comprise the steps:
2.1) parallel ALTERNATE SAMPLING: described analog intermediate frequency signal IF is carried out ALTERNATE SAMPLING simultaneously, and the concrete sampled point of described sampling is interlaced, export a plurality of digital intermediate frequency signal DIF1, DIF2 ..., DIFN;
2.2) with parallel ALTERNATE SAMPLING Digital Down Convert signal processing one to one: the described digital intermediate frequency signal in each road is carried out the Digital Down Convert signal processing by certain rule, export a plurality of narrowband baseband digital signal DB1, DB2 ..., DBN;
2.3) synthetic output: stack described narrowband baseband digital signal broadband, N road output broadband high magnification over-sampling baseband digital signal or Wideband Intermediate Frequency digital signal DO.
Described once sampling is corresponding be DB1, DB2 ... or DBN, described double sampling correspondence be Wideband Intermediate Frequency digital signal DO.
According to processing method provided by the invention, it is characterized in that the step 2.1 of described multi-channel parallel handling process) can simplify, adopt the digital down-conversion signal of intersection to handle the method for resampling of synthetic output, comprising:
3.1) mould/number conversion high power sampling processing: described analog intermediate frequency signal IF is carried out high sampling, be converted to digital intermediate frequency signal DIF output;
3.2) intersect digital down-conversion signal and handle: described digital intermediate frequency signal is intersected by certain rule carries out the Digital Down Convert signal processing, export a plurality of narrowband baseband digital signal DB1, DB2 ..., DBN;
3.3) synthetic output: stack described narrowband baseband digital signal broadband, N road output broadband high magnification over-sampling baseband digital signal or Wideband Intermediate Frequency digital signal DO.
Described once sampling is corresponding be DB1, DB2 ... or DBN, described double sampling correspondence be Wideband Intermediate Frequency digital signal DO.
According to processing method provided by the invention, it is characterized in that described multi-channel parallel handling process is in step 2.2) and step 2.3) between also comprise resampling interpolation processing process; The method for resampling of the resampling interpolation processing that described resampling interpolation processing process adopts, described baseband digital signal DB is carried out R rank interpolation processing, and described interpolation is the numerical value that the median that described analog intermediate frequency signal IF does not carry out sampling processing is drawn by certain resampling interpolation algorithm estimation; Described resampling interpolation algorithm is any.At this moment be synthetic output.
According to processing method provided by the invention, it is characterized in that step 2.3 in the described multi-channel parallel handling process) can replace with resampling interpolation processing and shunt output procedure; The method for resampling of the resampling interpolation processing that described resampling interpolation processing process adopts, described baseband digital signal DB is carried out R rank interpolation processing, and described interpolation is the numerical value that the median that described analog intermediate frequency signal IF does not carry out sampling processing is drawn by certain resampling interpolation algorithm estimation; Described resampling interpolation algorithm is any; Described shunt output is without synthetic directly output.At this moment can export every roadbed band signal along separate routes.
According to processing method provided by the invention, it is characterized in that when the analog intermediate frequency signal that described analog intermediate frequency signal IF is any monotype, single carrier frequency, described general multi-channel parallel handling process can be reduced to general purpose single passage handling process; Described general purpose single passage handling process may further comprise the steps:
6.1) Universal Die/number conversion sampling processing: described analog intermediate frequency signal IF is converted to digital intermediate frequency signal DIF output;
6.2) processing of general digital down-conversion signal: digital intermediate frequency signal DIF is converted to narrowband baseband digital signal DB by certain rule;
6.3) the resampling interpolation processing: described resampling processing method is the resampling interpolation processing, described baseband digital signal DB is carried out R rank interpolation processing narrowband baseband digital signal DB is transformed broadband high magnification over-sampling baseband digital signal DO output; Described interpolation is the numerical value that the median that described analog intermediate frequency signal IF does not carry out sampling processing is drawn by certain resampling interpolation algorithm estimation;
Described resampling interpolation algorithm is any.
According to processing method provided by the invention, it is characterized in that, the sample frequency of described parallel ALTERNATE SAMPLING and sampling zero hour be corresponding to the pattern and the carrier frequency of described analog intermediate frequency signal, and the work clock of described Digital Down Convert signal processing one to one is corresponding to described sample frequency and sampling zero hour.
According to processing method provided by the invention, it is characterized in that the work clock that the digital down-conversion signal of described intersection is handled is corresponding to the pattern and the carrier frequency of described analog intermediate frequency signal.
The technical problem of another corresponding circuits of the present invention solves like this, utilize software and General Porcess Unit, use digital if technology, signal processing circuit of intermediate frequency in the structure receiver, comprise able to programme and configurable clock-signal generator and software kit, it is characterized in that, also comprise the single-pass process circuit of a plurality of parallel connections and be connected the equalizer E of described single-pass process circuit input end and the mixer PS of output; Described single-pass process circuit comprises that order is electrically connected is used to change A/D converter ADC that the input analog intermediate frequency signal is a digital intermediate frequency signal, be used for described digital intermediate frequency signal is carried out the Digital Down Convert treatment circuit DDC of down-converted and the resampling interpolation circuit RS of the interpolation that is used to resample, described D/A ADC is an input, and described resampling interpolation circuit RS is an output; The analog intermediate frequency signal that described analog intermediate frequency signal IF is any monotype, single carrier frequency, any monotype, overloading synthetic analog intermediate frequency signal or the synthetic analog intermediate frequency signal IF of any multi-mode frequently.The sort circuit organization definition is many ADC Wideband Intermediate Frequency signal processing circuit.
According to treatment circuit provided by the invention, it is characterized in that described equalizer E and the A/D converter ADC that is included in a plurality of digital intermediate frequency signals in the described single-pass process circuit can replace with the A/D converter ADC of a digital intermediate frequency signal.The sort circuit organization definition is many DDC Wideband Intermediate Frequency signal processing circuit.
According to treatment circuit provided by the invention, it is characterized in that, in many ADC or DDC Wideband Intermediate Frequency signal processing circuit structure, described single-pass process circuit can use the typical signal processing circuit of intermediate frequency of being made up of the A/D converter ADC of order electrical connection and Digital Down Convert treatment circuit DDC to replace;
According to treatment circuit provided by the invention, it is characterized in that when described analog intermediate frequency signal IF was the analog intermediate frequency signal of any monotype, single carrier frequency, described signal processing circuit of intermediate frequency can replace with described single-pass process circuit of the present invention.
Intermediate-freuqncy signal processing method provided by the invention and circuit, under the requirement of satisfying common analog intermediate frequency signal processing, still can satisfy the requirement of baseband digital signal output, also can realize the output of broadband high magnification over-sampling baseband digital signal or Wideband Intermediate Frequency digital signal, thereby improve the processing accuracy and the processing speed of the if system of radio communication receiver, for the antijamming capability of promoting Wireless Telecom Equipment and the capacity that improves wireless communication system provide the foundation, also reduced the cost of equipment simultaneously.By the ADC of clock and varying number and DCC being made up and programming, can realize that also multi-mode, overloading are frequently and the application of smart antenna.This method adds that indispensable radio-frequency front-end, antenna and Base-Band Processing part can realize that for the intermediate-freuqncy signal treatment system of Digital Programmable, reconfigurable radio communication receiver SDR has provided a comprehensive solution; On such hardware platform, use software programming, configuration, definition, control and management, can support 1) over-sampling of baseband signal, 2) narrowband intermediate frequency analog signal output, 3) Wideband Intermediate Frequency analog signal output, 4) arrowband over-sampling analog intermediate frequency signal output, 5) broadband over-sampling analog intermediate frequency signal output, 6) arrowband overloading frequency channel, 7) broadband overloading frequency channel, 8) space diversity, 9) smart antenna, 10) FDD of radio communication, 11) TDD of radio communication, 12) frequency hopping of radio communication, 13) a plurality of wireless communication frequency bands, 14) various wireless communication pattern, 15) various wireless communication standard, this general-purpose platform can be supported various prior aries and the realization of the new technology that may expand from now on.
Description of drawings
Fig. 1 is the schematic diagram of the signal processing circuit of intermediate frequency of classics in the general receiver.
Fig. 2 is the schematic diagram of the single channel Wideband Intermediate Frequency signal processing circuit of band resampling interpolation circuit provided by the invention
Fig. 3 is the clock and the digital stream sequential schematic diagram of the Digital Signal Processing of circuit shown in Figure 2.
Fig. 4 is the schematic diagram of many DDC Wideband Intermediate Frequency signal processing circuit provided by the invention.
Fig. 5 is the clock and the digital stream sequential schematic diagram of the Digital Signal Processing of circuit shown in Figure 4.
Fig. 6 is the schematic diagram of many ADC Wideband Intermediate Frequency signal processing circuit provided by the invention.
Fig. 7 is the clock and the digital stream sequential schematic diagram of the Digital Signal Processing of circuit shown in Figure 6.
Embodiment
In conjunction with following the inventive method is further launched, is illustrated that the main basic point of inventive method is as follows:
The present invention adopts comprehensive SDR thought and the digital signal that treatment circuit will be exported is simulated the interpolation method of resampling, set up the hardware platform of a general wireless digital intermediate frequency sender, comprise: 1, can realize the single channel Wideband Intermediate Frequency signal processing circuit of monotype list carrier frequency Wideband Intermediate Frequency analog, its circuit structure as shown in Figure 2; 2, can realize many DDC Wideband Intermediate Frequency signal processing circuit of various Wideband Intermediate Frequency analog, be divided into and be not with and be with two kinds of forms of resampling interpolation circuit, wherein not distinguish as shown in Figure 4 with a kind of its circuit structure of resampling interpolation circuit; 3, can realize many ADC Wideband Intermediate Frequency signal processing circuit of various Wideband Intermediate Frequency analog, be divided into and be not with and be with two kinds of forms of resampling interpolation circuit, wherein not distinguish as shown in Figure 6 with a kind of its circuit structure of resampling interpolation circuit.Realize can selecting the 2nd kind or the 3rd kind of circuit under overloading frequency or the multi-mode wideband analog intermediate frequency signal disposition at needs, the 3rd kind of ratio accelerated conversion speed for the 2nd kind, improved signal processing quality.
Below in conjunction with this general hardware platform the present invention is done further expansion again, one, at first instruction book passage broadband signal processing circuit of intermediate frequency and processing method.
This single channel Wideband Intermediate Frequency signal processing circuit is on the signal processing circuit of intermediate frequency basis of classics, increase the output that resampling interpolation circuit (RS-Re-Sampling) is realized monotype, single carrier frequency over-sampling baseband signal or Wideband Intermediate Frequency digital signal at its DDC delivery outlet, its circuit structure as shown in Figure 2, comprise an ADC, a DDC and a RS, its input IF is that analog intermediate frequency signal, the output DO of single carrier frequency (monotype list carrier frequency) is baseband digital signal, broadband over-sampling baseband digital signal or Wideband Intermediate Frequency digital signal; RSCKO is the output gated clock of resampling interpolation circuit RS, and RSCKI is the input gated clock of resampling interpolation circuit RS input signal DB.This single channel Wideband Intermediate Frequency signal processing circuit is handled the resampling interpolation processing process that increased (the 3rd of workflow the step promptly) than classical intermediate-freuqncy signal, and its processing method also comprises the resampling interpolation algorithm that is built in the resampling interpolation processing process.
The workflow of foregoing circuit is as follows: 1, the analog intermediate frequency signal IF of single carrier frequency channel is from the input input of ADC, and under the driving of ADCK, ADC samples to IF and digitlization conversion and output digital intermediate frequency signal DIF; 2, under the gating of the DDCK clock identical with ADCK, DIF is input to DDC synchronously to carry out the Digital Down Convert signal processing and exports digital signal DB; 3, DB signal input resampling interpolation circuit RS under the RSCKI clock drives carries out the resampling interpolated signal processing on R rank, widen the bandwidth of DB signal and synchronously the RSCKO clock with its phase same rate output digital signal sequences DO, the RSCKO clock is a R times of synchronised clock of RSCKI clock.Because the step 3 that increases makes that the output spectrum of Do is the frequency spectrum of output clock RScko, when speed increased, the also corresponding increase of bandwidth on the basis of output baseband digital signal, had realized the output of single carrier frequency over-sampling baseband signal or Wideband Intermediate Frequency digital signal.
In the 2nd step, the Digital Signal Processing of DDC is under the situation on M rank at maximum depression of order in the above, and the digital signal DB speed of DDC output is DDCK/M, is defined as DDCM.
In the above in the 3rd step, RS can adopt any resampling interpolation algorithm in R rank, and this algorithm is that the occurrence that need that the value between the digital signal value draws according to described value estimation by the way of resampling interpolation algorithm regulation insert particular location is faced in ADC sampling output in the step 1 mutually.As detailed clock and the digital stream sequential of having shown this circuit of Fig. 3, further described the relation between above-mentioned signal and reflected this circuit working flow process.This circuit is simple, cost hangs down and satisfies certain application scenario.
Two, many DDC Wideband Intermediate Frequency signal processing circuit and processing method.
Many DDC Wideband Intermediate Frequency signal processing circuit of the present invention has increased a DDC number and a parallel/serial transducer PS (PS-Parallel/Serial) who participates in the Digital Down Convert processing on the signal processing circuit of intermediate frequency basis of classics, the structure of its circuit has two kinds of forms, first kind of form structure as shown in Figure 4, adopt same ADC to realize analog intermediate frequency signal IF mould/number conversion and DIF output, use a plurality of (N) DDC in parallel parallel Digital Down Convert of realization under their clocks separately drive to handle again, export wideband digital signal DO after parallel/serial transducer PS conversion merges.By the parameter of clock signal and DDC being programmed and making up, this circuit structure can be realized owing sampling or over-sampling to the intermediate frequency analog input signal IF of different frequencies, different bandwidth, realizes the application of baseband digital signal, over-sampling baseband digital signal or the Wideband Intermediate Frequency digital signal DB output of different mode, different carrier frequency and different bandwidth.When second kind of form increased the resampling interpolation circuit behind each DDC output, the bandwidth of further widening the wideband digital signal of its output was the wider circuit structure of adaptability.Adopt the Wideband Intermediate Frequency signal processing circuit of this DDC structure more than two kinds to carry out: (one), monotype, single carrier frequency Wideband Intermediate Frequency analog; (2), monotype, overloading frequency range band analog intermediate frequency signal are handled; (3), multi-mode, overloading frequency range band analog intermediate frequency signal are handled.
(1), monotype, single carrier frequency Wideband Intermediate Frequency analog: (than single-pass process circuit increased disposal ability and restructural be overloading frequently or the multi-mode Signal Processing, but cost is higher)
When IF was monotype, single carrier frequency Wideband Intermediate Frequency analog input signal, this circuit carried out monotype, single carrier frequency Wideband Intermediate Frequency Digital Signal Processing.
With first kind of form circuit structure is example, DDC1, DDC2 ..., DDCN has the identical parameters setting, its workflow is: 1, under the driving of sampling clock ADCK, ADC carries out over-sampling or owes the sampled digital conversion the analog intermediate frequency signal IF of input, output digital medium-frequency signal DIF; 2, when DDC1, DDC2 ..., during the DDCN concurrent working, DDC1, DDC2 ..., DDCN input gated clock DDCK1, DDCK2 ..., DDCKN (DDCK1, DDCK2 ..., DDCKN and ADCK have same clock rate, their phase place postpone respectively ADCK phase place 0/N, 1/N ... (N-1)/N) under the driving, same DIF be input to respectively DDC1, DDC2 ..., DDCN, be provided with down in identical parameters, DDC1, DDC2 ..., DDCN carries out signal processing to same DIF, and output have identical characteristics digital signal DB1, DB2 ..., DBN.3, DB1, DB2 ..., the DBN digital signal, via the 0/N that postpones the DDCM phase place respectively, 1/N, 2/N, (N-1)/PSCK1, the PSCK2 of N, PSCK3 ..., the PSCKN clock, the parallel/serial transducer PS that gating is made of latch D, with DB11, DB21, DB31 ..., DBN1, DB12 ... form mix output serial digital signal sequence D O to baseband processing equipment, thereby realize the output of wideband digital signal.As detailed clock and the digital stream sequential of having shown this processing procedure of Fig. 5, further described the relation between above-mentioned signal and reflected this processing procedure workflow.
In the above the 2nd the step in, DDC1, DDC2 ..., DDCN Digital Signal Processing be under the situation on M rank all at maximum depression of order, described DB1, DB2 ..., DBN maximum rate all are DDCM, promptly the 3rd the step in the DDCM indication, speed is ADCK/M.
In addition, in the above in the 2nd step, when DDC1, DDC2 ..., DDCN input gated clock DDCK1, DDCK2 ..., DDCKN speed when being all ADCK/N, step 2 is: postpone respectively DDCK1 phase place 0/N, 1/N, 2/N ... (N-1)/DDCK1, the DDCK2 of N ..., the DDCKN clock driving under, corresponding to different DIF1, the DIF2 of same DIF ..., DIFN subsequence signal be input to respectively DDC1, DDC2 ..., DDCN.DDC1, DDC2 ..., DDCN is provided with in identical parameters and down different separately supplied with digital signal handled.When DDC1, DDC2 ..., DDCN Digital Signal Processing all maximum depression of order be under the situation on M rank and output have different qualities digital signal DB1, DB2 ..., DBN.DDC1, DDC2 ..., DDCN Digital Signal Processing be under the situation on M rank all at maximum depression of order, described DB1, DB2 ..., DBN maximum rate all are DDCM, at this moment DDCM is not both ADCK/N/M.
(2), monotype, overloading frequency range band analog intermediate frequency signal are handled:
When IF was monotype, broadband overloading frequency intermediate frequency analog input signal, this circuit carried out monotype, overloading frequency range band digital intermediate frequency signal is handled, and can two kinds of different way of outputs be arranged at different demands.First kind of way of output without the PS circuit directly export each carrier frequency channel digital signal DB1, DB2 ..., DBN; Second kind of way of output through the PS circuit with DB11, DB21, DB31 ..., DBN1, DB12 ... form mix to merge output digital signal sequences DO.
With first kind of form circuit structure is example, DDC1, DDC2 ..., DDCN be programmed be tuned to different carrier frequency channels, its workflow is: 1, the intermediate frequency input signal IF of monotype broadband overloading frequency channel is from the input input of ADC, under the driving of sampling clock ADCK, ADC carries out over-sampling or owes the sampled digital conversion IF, output digital signal DIF.2, digital signal DIF with synchronous DDCK1, the DDCK2 of ADCK ..., import respectively under the DDCKN gated clock DDC1, DDC2 ..., DDCN, be programmed be tuned to different carrier frequency channel DDC1, DDC2 ..., DDCN to different be selected into signal carry out the intermediate frequency digital processing obtain each carrier frequency channel digital signal DB1, DB2 ..., DBN is with the output of first kind of way of output or output to PS and be for further processing.If 3 DB1, DB2 ..., DBN outputs to PS, then by the 0/N that postpones the DDCM phase place respectively, 1/N, 2/N, (N-1)/PSCK1, the PSCK2 of N ..., PSCKN clock gating PS, with DB11, DB21, DB31 ..., DBN1, DB12 ... form mix to merge output digital signal sequences DO, the digital signal of each carrier frequency channel is outputed to baseband processing equipment.
In the above the 2nd the step in, DDC1, DDC2 ..., DDCN Digital Signal Processing be under the situation on maximum M rank at depression of order, described DB1, DB2 ..., DBN maximum rate all are DDCM, i.e. the 3rd step DDCM indication.At this moment, if DB1, the DB2 of this moment output ..., DBN speed satisfies the requirement of baseband digital signal speed, DB1, DB2 ..., DBN is exactly the baseband digital signal of each carrier frequency channel.
In the above the 3rd the step in, go back Reprogrammable PSCK1, PSCK2 ..., the PSCKN clock, realize the digital signal output in broadband more.
(3), multi-mode, overloading frequency range band analog intermediate frequency signal are handled.
IF is multi-mode, overloading frequency range band digital intermediate frequency signal, and this circuit carries out multi-mode, overloading frequency range band digital intermediate frequency signal is handled, and can two kinds of different way of outputs be arranged at different demands.First kind of way of output without the PS circuit directly export each carrier frequency channel digital signal DB1, DB2 ..., DBN; Second kind of way of output through the PS circuit with DB11, DB21, DB31 ..., DBN1, DB12 ... form mix to merge output digital signal sequences DO.
With first kind of form circuit structure is example, DDC1, DDC2, DDC3 ..., DDCN is by its tuning, filtering that is programmed, the isoparametric difference of demodulation, respectively DIF being carried out digital intermediate frequency signal by different patterns handles, its workflow is: 1, multi-mode, overloading frequency range band intermediate frequency digital input signals IF import from the input of ADC, under the driving of ADCK, ADC carries out over-sampling or owes the sampled digital conversion IF, output DIF.2, DDC1, DDC2 ..., DDCN works in different mode respectively, satisfy different mode clock DDCK1, DDCK2 ..., DDCKN respectively gating input DIF to DDC1, DDC2 ..., DDCN handle the digital signal DB1, the DB2 that obtain different mode ..., DBN is with the output of first kind of way of output or output to PS and be for further processing.If the digital signal DB1 of 3 each carrier frequency channel, DB2 ..., DBN imports PS, then via postpone respectively DDCM1, DDCM2 ..., the DDCMN phase place 0/N, 1/N, 2/N, (N-1)/PSCK1, the PSCK2 of N ..., PSCKN clock gating PS, with DB11, DB21, DB31 ..., DBN1, DB12 ... form mixes output digital signal sequences DO baseband processing equipment.
In the above in the 2nd step, DDC1, DDC2 ..., DDCN Digital Signal Processing be under the situation on M rank all at maximum depression of order, the maximum number output speed of each DDC be DDCK1/M, DDCK2/M ..., DDCKN/M, be defined as respectively DDCM1, DDCM2 ..., DDCMN, promptly the 3rd the step in DDCM1, DDCM2 ..., the DDCMN indication.When the speed of output digital signal satisfies the requiring of baseband digital signal speed of each pattern, DDC1, DDC2 ..., DDCN output be the baseband digital signal of carrier frequency channel under each pattern.
In the above the 3rd the step in, also Reprogrammable PSCK1, PSCK2 ..., the PSCKN clock, realize the wideband digital signal output of different mode.
Three, many ADC Wideband Intermediate Frequency signal processing circuit and processing method.
Many ADC Wideband Intermediate Frequency signal processing circuit of the present invention has increased the ADC number of processing mould/number conversion and has been positioned at the equalizer E of input on many DDC Wideband Intermediate Frequency signal processing circuit basis, the structure of its circuit also has two kinds of forms, first kind of form structure as shown in Figure 6, employing a plurality of (N) classical signal processing circuit of intermediate frequency in parallel behind equalizer E output carries out signal processing, merges output wideband digital signal DO after parallel/serial transducer PS mixes.Second kind of form structure, include the resampling interpolation circuit, employing a plurality of (N) single channel Wideband Intermediate Frequency signal processing circuit of the present invention in parallel behind equalizer E output is carried out signal processing, merges output wideband digital signal DO after parallel/serial transducer PS mixes.By the parameter of clock signal and DDC being programmed and making up, this circuit structure can be realized owing sampling or over-sampling to different IF input signals, realizes the application of baseband digital signal, over-sampling baseband digital signal or the output of Wideband Intermediate Frequency digital signal of different mode, different bandwidth.With the difference of many DDC Wideband Intermediate Frequency signal processing circuit, increased the quantity of ADC, thereby accelerated the speed of ADC the sampling of intermediate-freuqncy signal IF, improved the quality of Digital Signal Processing.Adopt the Wideband Intermediate Frequency signal processing circuit of this DDC structure more than two kinds to be mainly used in the oversampled signals processing, can carry out: (one), monotype, single carrier frequency Wideband Intermediate Frequency analog; (2), monotype, overloading frequency range band analog intermediate frequency signal are handled; (3), multi-mode, overloading frequency range band analog intermediate frequency signal are handled.
(1), monotype, single carrier frequency Wideband Intermediate Frequency analog:
When IF was monotype, single carrier frequency Wideband Intermediate Frequency analog input signal, this circuit carried out monotype, single carrier frequency Wideband Intermediate Frequency Digital Signal Processing.
With first kind of form circuit structure is example, DDC1, DDC2 ..., DDCN has the identical parameters setting, its workflow is: 1, the IF signal of single carrier frequency channel is from the input of the input of equalizer (E), identical IF1, the IF2 of E output ... the IFN signal to ADC1, ADC2 ..., ADCN input.2, ADC1, ADC2 ..., ADCN respectively by postpone ADCK1 phase place 0/N, 1/N ..., (N-1)/N ADCK1, ADCK2 ..., ADCKN clock drive the digitlization conversion that input signal is sampled, and respectively with ADCK1, ADCK2 ..., DDCK1, DDCK2 that ADCKN is identical ..., the DDCKN clock driving down output DIF1, DIF2 ..., DIFN to corresponding DDC1, DDC2 ..., DDCN.3, the DDC1, the DDC2 that are provided with of identical parameters ..., DDCN respectively to separately supplied with digital signal DIF1, DIF2 ..., DIFN handles and export same band digital signal DB1, DB2 ..., DBN.4, output digital signal DB1, DB2 ..., DBN by respectively with DDCM1, DDCM2 ..., PSCK1, PSCK2 that the DDCMN phase place is identical ..., PSCKN clock gating PS, with DB11, DB21, DB31 ..., DBN1, DB12 ... form mixes and merges output digital signal sequences DBO to baseband processing equipment, realizes the output of wideband digital signal.As detailed clock and the digital stream sequential of having shown this processing procedure of Fig. 7, further described the relation between above-mentioned signal and reflected this processing procedure workflow.
In the above in the 2nd step, when N＞2, and the frequency bandwidth of IF is during less than N * ADCK1/2, ADC1, ADC2, ADC3 ..., ADCN carries out the digitlization conversion of over-sampling to IF.
In the above in the 3rd step, DDC1, DDC2 ..., DDCN Digital Signal Processing be under the situation on maximum M rank at identical depression of order respectively, DDC1, DDC2 ..., DDCN the digital signal output speed be respectively DDCK1/M, DDCK2/M ..., DDCKN/M, be defined as DDCM1, DDCM2 ..., DDCMN, promptly the 4th the step in DDCM1, DDCM2 ..., the DDCMN indication.
(2), monotype, overloading frequency range band analog intermediate frequency signal are handled:
When IF was monotype, broadband overloading frequency intermediate frequency analog input signal, this circuit carried out monotype, overloading frequency range band digital intermediate frequency signal is handled, and can two kinds of different way of outputs be arranged at different demands.First kind of way of output without the PS circuit directly export each carrier frequency channel digital signal DB1, DB2 ..., DBN; Second kind of way of output through the PS circuit with DB11, DB21, DB31 ..., DBN1, DB12 ... form mix to merge output digital signal sequences DO.
With first kind of form circuit structure is example, DDC1, DDC2 ..., DDCN be programmed be tuned to different carrier frequency channels, its workflow is: 1, the monotype overloading frequently the analog intermediate frequency signal IF of channel from the input input of E, identical IF1, the IF2 of E output ... the IFN signal to ADC1, ADC2 ..., ADCN input.2, ADC1, ADC2 ..., ADCN identical clock ADCK1, ADCK2 ..., ADCKN drives down, according to different situations IF is carried out over-sampling or owe sampled digitalization be converted to DIF1, DIF2 ..., DIFN, and with ADCK1, ADCK2 ..., DDCK1, DDCK2 that ADCKN is identical ..., the DDCKN clock driving under with gained DIF1, DIF2 ..., DIFN is input to DDC1 respectively, DDC2,, DDCN.3, the DDC1 that programmes by different tuner parameters, DDC2, DDCN, select different carrier frequency channels, respectively to different carrier frequency digital signal DIF1, DIF2 ..., the DIFN processing of carrying out intermediate-freuqncy signal obtain each carrier frequency channel of same band digital signal DB1, DB2 ..., DBN is with the output of first kind of way of output or output to PS and be for further processing.If 4 DB1, DB2 ..., DBN outputs to PS, then by the 0/N that postpones the DDCM1 phase place respectively, 1/N, (N-1)/PSCK1, the PSCK2 of N ..., PSCKN clock gating PS, with DB11, DB21, DB31 ..., DBN1, DB12 ... form mixes and merges output digital signal sequences DO to baseband processing equipment.
In the above in the 3rd step, DDC1, DDC2 ..., the Digital Signal Processing of DDCN is under the situation on maximum M rank at identical depression of order all, each DDC1, DDC2 ..., the digital signal output speed of DDCN be respectively DDCK1/M, DDCK2/M ..., DDCKN/M, be defined as DDCM1, DDCM2 ..., DDCMN, promptly the 4th the step in the DDCM1 indication.At this moment, at DDC1, DDC2 ... the output of DDCN, digital signal DB1, the DB2 of each carrier frequency channel of output same band ..., DBN, if when output speed satisfies requiring of baseband digital signal speed, DDC1, DDC2 ..., what DDCN exported is exactly the baseband digital signal of each carrier frequency channel.
In the above the 4th the step in, go back Reprogrammable PSCK1, PSCK2 ..., the PSCKN clock, realize the digital signal output in broadband more.
(3), multi-mode, overloading frequency range band analog intermediate frequency signal are handled:
IF is multi-mode, overloading frequency range band digital intermediate frequency signal, and this circuit carries out multi-mode, overloading frequency range band digital intermediate frequency signal is handled, and can two kinds of different way of outputs be arranged at different demands.First kind of way of output without the PS circuit directly export each carrier frequency channel digital signal DB1, DB2 ..., DBN; Second kind of way of output through the PS circuit with DB11, DB21, DB31 ..., DBN1, DB12 ... form mix to merge output digital signal sequences DO.
With first kind of form circuit structure is example, DDC1, DDC2 ..., DDCN is by its tuning, filtering that is programmed, the isoparametric difference of demodulation, respectively DIF being carried out digital intermediate frequency signal by different patterns handles, its workflow is: 1, multi-mode, overloading frequency range band digital intermediate frequency signal IF be from the input input of E, identical IF1, the IF2 of E output ... the IFN signal to ADC1, ADC2 ..., ADCN input.2, ADC1, ADC2, ADC3 ..., ADCN respectively clock ADCK1, the ADCK2 of different mode, ADCK3 ..., ADCKN drives down, according to different situations IF is carried out over-sampling or owe sampled digitalization be converted to DIF1, DIF2 ..., DIFN, and respectively with ADCK1, ADCK2 ..., DDCK1, DDCK2 that ADCKN is identical ..., the DDCKN gated clock driving under with gained DIF1, DIF2 ..., DIFN be input to respectively DDC1, DDC2 ..., DDCN.3, be operated in different mode DDC1, DDC2 ..., DDCN, to separately the input DIF1, DIF2 ..., DIFN respectively by different patterns carry out digital intermediate frequency signal handle digital signal DB1, the DB2 obtain each carrier frequency channel under the different mode ..., DBN, with the output of first kind of way of output or output to PS and be for further processing.If 4 DB1, DB2 ..., DBN outputs to PS, then by the 0/N that postpones the DDCM1 phase place respectively, 1/N, 2/N, (N-1)/PSCK1, the PSCK2 of N, PSCK3 ..., PSCKN clock gating PS, with DB11, DB21, DB31 ..., DBN1, DB12 ... form mix to merge output digital signal sequences DO to baseband processing equipment.
In the above in the 3rd step, DDC1, DDC2 ..., the Digital Signal Processing of DDCN is under the situation on maximum M rank at identical depression of order all, each DDC1, DDC2 ..., the digital signal output speed of DDCN be respectively DDCK1/M, DDCK2/M ..., DDCKN/M, be defined as DDCM1, DDCM2 ..., DDCMN, promptly the 4th the step in the DDCM1 indication.At this moment, if the speed of output digital signal satisfies the requirement of the baseband digital signal speed of each pattern, DDC1, DDC2 ..., DDCN output be exactly the baseband digital signal of carrier frequency channel under each pattern.
In the above the 4th the step in, go back Reprogrammable PSCK1, PSCK2 ..., the PSCKN clock, realize the digital signal output in broadband more.
Above-mentioned three kinds of circuit can satisfy needs to different mode and carrier frequency by able to programme, configurable clock-signal generator being carried out software definition, can support the requirement of multiple communication standard to physical layer, top management and system interface by downloading, use with the different software kit of its cooperation.
Claims (10)
1. the intermediate-freuqncy signal processing method in the receiver, utilize software and General Porcess Unit, use digital if technology, it is characterized in that, adopt method for resampling, comprised the multi-channel parallel handling process that is used for input analog intermediate frequency signal IF is converted into baseband digital signal DB, broadband high magnification over-sampling baseband digital signal DB or output Wideband Intermediate Frequency digital signal DO; Described method for resampling is that the baseband digital signal DB to once sampling output resamples and handles the sub-sampled signal Wideband Intermediate Frequency digital signal DO that obtains described analog intermediate frequency signal IF, and the sample frequency of described Wideband Intermediate Frequency digital signal DO is higher than the sample frequency of described baseband digital signal DB; Described analog intermediate frequency signal IF is the analog intermediate frequency signal of any monotype, single carrier frequency, any monotype, overloading synthetic analog intermediate frequency signal or the synthetic analog intermediate frequency signal of any multi-mode frequently.
2. according to the described processing method of claim 1, it is characterized in that described multi-channel parallel handling process adopts the synthetic method for resampling of ALTERNATE SAMPLING, may further comprise the steps:
2.1) parallel ALTERNATE SAMPLING: described analog intermediate frequency signal IF is carried out ALTERNATE SAMPLING simultaneously, and the concrete sampled point of described sampling is interlaced, export a plurality of digital intermediate frequency signal DIF1, DIF2 ..., DIFN;
2.2) with parallel ALTERNATE SAMPLING Digital Down Convert signal processing one to one: to the described digital intermediate frequency signal DIF1 in each road, DIF2 ..., DIFN carries out the Digital Down Convert signal processing by certain rule, export a plurality of baseband digital signal DB1, DB2 ..., DBN;
2.3) synthetic output: the stack N described baseband digital signal DB1 in road, DB2 ..., DBN, broadband output broadband high magnification over-sampling baseband digital signal or Wideband Intermediate Frequency digital signal DO.
3. according to the described processing method of claim 2, it is characterized in that the step 2.1 of described multi-channel parallel handling process) can simplify, adopt the digital down-conversion signal of intersection to handle the method for resampling of synthetic output, comprising:
3.1) mould/number conversion high power sampling processing: described analog intermediate frequency signal IF is carried out high sampling, be converted to digital intermediate frequency signal DIF output;
3.2) intersect digital down-conversion signal and handle: described digital intermediate frequency signal is intersected by certain rule carries out the Digital Down Convert signal processing, export a plurality of baseband digital signal DB1, DB2 ..., DBN;
3.3) synthetic output: stack described baseband digital signal broadband, N road output broadband high magnification over-sampling baseband digital signal or Wideband Intermediate Frequency digital signal DO.
4. according to claim 2 or 3 described processing methods, it is characterized in that described multi-channel parallel handling process is in step 2.2) and step 2.3) between also comprise resampling interpolation processing process; The method for resampling of the resampling interpolation processing that described resampling interpolation processing process adopts, described baseband digital signal DB is carried out R rank interpolation processing, and described interpolation is the numerical value that the median that described analog intermediate frequency signal IF does not carry out sampling processing is drawn by certain resampling interpolation method estimation.
5. according to claim 2 or 3 described processing methods, it is characterized in that step 2.3 in the described multi-channel parallel handling process) can replace with resampling interpolation processing and shunt output procedure; The method for resampling of the resampling interpolation processing that described resampling interpolation processing process adopts, described baseband digital signal DB is carried out R rank interpolation processing, and described interpolation is the numerical value that the median that described analog intermediate frequency signal IF does not carry out sampling processing is drawn by certain resampling interpolation algorithm estimation; Described shunt output is without synthetic directly output.
6. according to the described processing method of claim 1, it is characterized in that when the analog intermediate frequency signal that described analog intermediate frequency signal IF is any monotype, single carrier frequency, described multi-channel parallel handling process is a general purpose single passage handling process, may further comprise the steps:
6.1) Universal Die/number conversion sampling processing: described analog intermediate frequency signal IF is converted to digital intermediate frequency signal DIF output;
6.2) processing of general digital down-conversion signal: digital intermediate frequency signal DIF is converted to baseband digital signal DB by certain rule;
6.3) the resampling interpolation processing: described resampling processing method is the resampling interpolation processing, described baseband digital signal DB is carried out R rank interpolation processing baseband digital signal DB is transformed broadband high magnification over-sampling baseband digital signal DB output; Described interpolation is the numerical value that the median that described analog intermediate frequency signal IF does not carry out sampling processing is drawn by certain resampling interpolation algorithm estimation.
The numerical value that the median of not carrying out sampling processing draws by certain resampling interpolation algorithm estimation.
7. according to the described processing method of claim 2, it is characterized in that, the sample frequency of described parallel ALTERNATE SAMPLING and sampling zero hour be corresponding to the pattern and the carrier frequency of described analog intermediate frequency signal, and the work clock of described Digital Down Convert signal processing one to one is corresponding to described sample frequency and sampling zero hour.
8. according to the described processing method of claim 3, it is characterized in that the work clock of described intersection Digital Down Convert Digital Signal Processing is corresponding to the pattern and the carrier frequency of described analog intermediate frequency signal.
9. the signal processing circuit of intermediate frequency in the receiver, comprise able to programme and configurable clock-signal generator and software kit, it is characterized in that, also comprise the single-pass process circuit of a plurality of parallel connections and be connected the equalizer E of described single-pass process circuit input end and the mixer PS of output, described single-pass process circuit comprises that order is electrically connected is used to change the input analog intermediate frequency signal is the A/D converter ADC of digital intermediate frequency signal, be used for described digital intermediate frequency signal is carried out the Digital Down Convert treatment circuit DDC of down-converted and the resampling interpolation circuit RS of the interpolation that is used to resample, described D/A ADC is an input, and described resampling interpolation circuit RS is an output; Described analog intermediate frequency signal IF is the analog intermediate frequency signal of any monotype, single carrier frequency, any monotype, overloading synthetic analog intermediate frequency signal or the synthetic analog intermediate frequency signal IF of any multi-mode frequently; Described equalizer E and the A/D converter ADC that is included in a plurality of digital intermediate frequency signals in the described single-pass process circuit replace with the A/D converter ADC of a digital intermediate frequency signal and the typical circuit of digital frequency conversion treatment circuit DDC composition.
10. according to the described treatment circuit of claim 9, it is characterized in that, when described analog intermediate frequency signal IF was the analog intermediate frequency signal of any monotype, single carrier frequency, described signal processing circuit of intermediate frequency replaced with the described single-pass process circuit that comprises A/D converter ADC, Digital Down Convert treatment circuit DDC and resampling interpolation circuit RS.
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| US8049505B2 (en) * | 2006-12-19 | 2011-11-01 | Koninlijke Philips Electronics N.V. | MRI system with direct digital receiver using resampling |
| CN101184297B (en) * | 2007-11-19 | 2010-06-02 | 华为技术有限公司 | Dual-mode transceiver and dual-mode signal processing method |
| CN101227266B (en) * | 2008-01-30 | 2010-07-28 | 华为技术有限公司 | Method and apparatus for clock recovery |
| CN102104391B (en) * | 2009-12-18 | 2014-08-13 | 中兴通讯股份有限公司 | Intermediate-frequency filtering device and method |
| CN103346756A (en) * | 2013-07-03 | 2013-10-09 | 北京北斗星通导航技术股份有限公司 | Space-time self-adaptive filtering method and device |
| CN105984346B (en) * | 2015-02-12 | 2018-06-29 | 株洲南车时代电气股份有限公司 | EMU power module overtemperature records system and method |
| CN107809248A (en) * | 2016-09-08 | 2018-03-16 | 上海贝岭股份有限公司 | Multi-mode analog to digital conversion circuit |
| CN108923785B (en) * | 2018-07-06 | 2022-03-01 | 中国电子科技集团公司第十四研究所 | Method for improving signal-to-noise ratio of multi-channel synthesized signal after DDC |
| CN113765545B (en) * | 2021-09-02 | 2022-10-28 | 上海微波技术研究所（中国电子科技集团公司第五十研究所） | Bluetooth receiver demodulation system and method |
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