CN112737626B - Broadband parallel receiving and processing device based on VPX bus - Google Patents
Broadband parallel receiving and processing device based on VPX bus Download PDFInfo
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- CN112737626B CN112737626B CN202011506311.7A CN202011506311A CN112737626B CN 112737626 B CN112737626 B CN 112737626B CN 202011506311 A CN202011506311 A CN 202011506311A CN 112737626 B CN112737626 B CN 112737626B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/0003—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain
- H04B1/0007—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain wherein the AD/DA conversion occurs at radiofrequency or intermediate frequency stage
Abstract
The invention discloses a broadband parallel receiving and processing device based on a VPX bus, and belongs to the technical field of signal reconnaissance and direction finding. The device comprises a clock source unit, first to fifth channel units, a sampling unit, a first processing unit, a second processing unit, a monitoring unit, a first interface unit, a second interface unit and a VPX back plate unit; the first processing unit and the second processing unit are realized on the basis of FPGA, and the monitoring unit is realized on the basis of an embedded processor. The invention adopts the design of integrating broadband receiving and parallel processing, has high real-time performance and can realize quick perception in complex environment.
Description
Technical Field
The invention relates to a broadband parallel receiving and processing device based on a VPX bus, and belongs to the technical field of signal reconnaissance and direction finding.
Background
The traditional reconnaissance system can only perform reconnaissance aiming at a single frequency band and cannot meet the requirement of full-frequency-band broadband reconnaissance. At present, a receiving processing device mainly adopts a narrow-band fast scanning receiving system, the receiving sensitivity is high, equipment tends to be miniaturized, the requirement on the medium-frequency digital processing speed is relatively low, but the interception probability is low, the real-time performance is poor, and the device cannot sense in time in the face of a complex electromagnetic environment.
Based on the above conditions, the target reconnaissance system needs to be designed based on a multi-channel broadband parallel receiving system, and with the development of a broadband receiving technology, a modular open architecture and a multifunctional extensible radio frequency receiving module technology, a receiving processing system develops towards high levels such as integration and high integration.
Disclosure of Invention
The invention aims to avoid the defects in the prior art and provides a VPX bus-based broadband parallel receiving and processing device, which adopts an integrated design of broadband receiving and parallel processing, has high real-time performance and can realize quick sensing in a complex environment.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a broadband parallel receiving and processing device based on a VPX bus comprises a clock source unit 1, first to fifth channel units 2 to 6, a sampling unit 7, a first processing unit 8, a second processing unit 9, a monitoring unit 10, a first interface unit 11, a second interface unit 12 and a VPX back plate unit 13; the first processing unit 8 and the second processing unit 9 are realized based on FPGA, and the monitoring unit 10 is realized based on an embedded processor;
wherein, the clock source unit 1 outputs synchronous reference clock to the first to fifth channel units 2-6 and the sampling unit 7;
the first channel unit 2 to the fifth channel unit 6 respectively receive the radio frequency signal of the channel 1 for frequency conversion amplification, and output a broadband intermediate frequency analog signal to the sampling unit 7;
the sampling unit 7 converts the received 5 paths of broadband intermediate frequency analog signals into 5 paths of digital intermediate frequency signals, and then the signals are transmitted to the first processing unit 8 through the VPX back board unit 13; the sampling unit 7 also switches and outputs the network interface of the first processing unit 8 through the VPX backplane unit 13;
the first processing unit 8 carries out parallel direction-finding processing on the 5 paths of digital intermediate frequency signals, then sends the processing result to a network interface of the sampling unit 7 through the VPX back board unit 13 for outputting, and sends 1 path of digital intermediate frequency signals in the 5 paths of digital intermediate frequency signals to the second processing unit 9 through the VPX back board unit 13 for detecting and receiving processing; the processing result of the second processing unit 9 is sent to the interface unit 12 through the VPX backplane unit 13 for output;
the first processing unit 8 comprises an interferometer direction-finding processor realized based on an FPGA, 5 digital down converters and 5 FFT processors, wherein the 5 digital down converters receive 5 paths of digital intermediate frequency signals sent from the sampling unit 7, perform down conversion processing on the digital signals, and then send the digital signals to the FFT processor for FFT processing, and the 5 paths of FFT processing results enter the interferometer direction-finding processor in parallel to complete direction-finding processing;
the second processing unit 9 comprises a narrow-band digital down converter realized based on FPGA, N digital filters, N signal detectors and N signal detection and reception processors, wherein N is more than or equal to 8; the narrow-band digital down converter receives the 1-channel digital intermediate frequency signal sent by the first processing unit 8, performs narrow-band down conversion processing on the digital intermediate frequency signal, and then sends the processed signal to the N digital filters respectively; n digital filters filter the input signals, and the filtered signals enter a signal detector for signal detection; the N signal detectors send the detected signals to corresponding signal detection processors to complete detection processing;
the monitoring unit is used for executing the following programs:
1) receiving a working instruction, and switching to the step 2 after the self-checking state of the equipment is normal;
2) controlling the clock source unit 1 to output a reference clock, and then turning to step 3);
3) controlling the first to fifth channel units 2-6 to work in the designated frequency band, and then turning to the step 4);
4) setting working parameters of a first processing unit 8 and a second processing unit 9, and then turning to step 5);
5) the working states of the clock source unit 1, the first to fifth channel units 2 to 6, the first processing unit 8 and the second processing unit 9 are read back at regular time, and working state data are output through the first interface unit 11;
the first interface unit 11 outputs the data output by the monitoring unit 10 through the industry standard interface ethernet.
Compared with the background technology, the invention has the following advantages:
1. the broadband parallel receiving and processing device receives through analog frequency conversion, performs intermediate frequency digital sampling, and performs broadband parallel processing on intermediate frequency digital signals. The system adopts a unified platform design, and solves the problems of non-unified system, rule and interface, large quantity and difficult information exchange of the traditional receiving and processing equipment.
2. The invention has the capacity of multi-channel analog receiving and can carry out the parallel processing of multi-channel broadband digital intermediate frequency signals.
3. The device has the advantages of high integration of modules, independent functions and high reliability, and is suitable for fixed or movable loading platforms.
Drawings
Fig. 1 is a schematic block diagram of a broadband parallel reception processing apparatus according to an embodiment of the present invention.
Detailed Description
The invention is further described with reference to the following figures and detailed description.
Referring to fig. 1, a VPX bus-based broadband parallel receiving and processing device includes a clock source unit 1, channel units 2 to 6, a sampling unit 7, a processing unit 8, a processing unit 9, a monitoring unit 10, an interface unit 11, an interface unit 12, and a VPX backplane unit 13, which are installed in a chassis, and all the units are connected through a cable.
The clock source unit 1 is used for providing a homologous reference clock for the channel units 2-6 and the sampling unit 7, the channel units 2-6 are used for performing frequency conversion amplification on radio frequency signals, the sampling unit 7 is used for sampling 5 paths of broadband intermediate frequency analog signals, the processing unit 8 is used for direction finding, the processing unit 9 is used for broadband interception, the interface unit 11 is used for receiving result data of the monitoring unit 10, the interface unit 12 is used for receiving interception result data of the processing unit 9, the monitoring unit 10 is used for controlling the clock source unit 1, the channel units 2-6, the processing unit 8 and the processing unit 9, and the VPX backboard unit 13 is used for realizing data transmission by adopting a VPX bus interface standard.
The clock source unit 1, the channel units 2-6, the sampling unit 7, the processing unit 8, the processing unit 9, the monitoring unit 10, the interface unit 11, the interface unit 12 and the VPX backplane unit 13 are all manufactured by using related integrated circuits sold in the market. Specifically, the processing units 8 and 9 are fabricated using FPGA chips XC7VX690T from XILINX, the monitoring unit 10 is fabricated using TMS320C6678 from TI, and the sampling unit 7 performs AD signal conversion using a commercially available AD9680 sampling chip.
Specifically, the clock source unit 1 outputs a synchronous reference clock to the channel units 2-6 and the sampling unit 7; the channel units 2-6 respectively receive the radio frequency signals of the channel 1 for frequency conversion amplification, and output broadband intermediate frequency analog signals to the sampling unit 7; the sampling unit 7 converts the received 5 paths of broadband intermediate frequency analog signals into 5 paths of digital intermediate frequency signals, and then the signals are transmitted to the first processing unit 8 through the VPX back board unit 13; the sampling unit 7 also switches and outputs the network interface of the first processing unit 8 through a VPX backplane unit 13;
the first processing unit 8 carries out parallel direction-finding processing on the 5 paths of digital intermediate frequency signals, then sends the processing result to a network interface of the sampling unit 7 through the VPX back board unit 13 for outputting, and sends 1 path of digital intermediate frequency signals in the 5 paths of digital intermediate frequency signals to the second processing unit 9 through the VPX back board unit 13 for detecting and receiving processing; the processing result of the second processing unit 9 is sent to the interface unit 12 through the VPX backplane unit 13 for output;
the first processing unit 8 comprises an interferometer direction-finding processor realized based on an FPGA, 5 digital down converters and 5 FFT processors, wherein the 5 digital down converters receive 5 paths of digital intermediate frequency signals sent from the sampling unit 7, perform down conversion processing on the digital signals, and then send the digital signals to the FFT processor for FFT processing, and the 5 paths of FFT processing results enter the interferometer direction-finding processor in parallel to complete direction-finding processing;
the second processing unit 9 comprises a narrow-band digital down converter realized based on FPGA, N digital filters, N signal detectors and N signal detection and reception processors, wherein N is more than or equal to 8; the narrow-band digital down converter receives the 1-channel digital intermediate frequency signal sent by the first processing unit 8, performs narrow-band down conversion processing on the digital intermediate frequency signal, and then sends the processed signal to the N digital filters respectively; n digital filters filter the input signals, and the filtered signals enter a signal detector for signal detection; the N signal detectors send the detected signals to corresponding signal detection processors to complete detection processing;
the monitoring unit is used for executing the following programs:
1) receiving a working instruction, and switching to the step 2 after the self-checking state of the equipment is normal;
2) controlling the clock source unit 1 to output a reference clock, and then turning to step 3);
3) controlling the first to fifth channel units 2-6 to work in the designated frequency band, and then turning to the step 4);
4) setting working parameters of a first processing unit 8 and a second processing unit 9, and then turning to the step 5);
5) the working states of the clock source unit 1, the first to fifth channel units 2 to 6, the first processing unit 8 and the second processing unit 9 are read back at regular time, and working state data are output through the first interface unit 11;
the first interface unit 11 outputs the data output by the monitoring unit 10 through the industry standard interface ethernet.
The invention adopts a unified platform design, and solves the problems of non-unified system, rule and interface, large quantity and difficult information exchange of the traditional receiving and processing equipment. The multi-channel analog receiving device has multi-channel analog receiving capability, can perform multi-channel broadband digital intermediate frequency signal parallel processing, and is suitable for fixed or mobile loading platforms.
Claims (1)
1. A broadband parallel receiving and processing device based on a VPX bus is characterized by comprising a clock source unit (1), first to fifth channel units (2-6), a sampling unit (7), a first processing unit (8), a second processing unit (9), a monitoring unit (10), a first interface unit (11), a second interface unit (12) and a VPX back panel unit (13); the first processing unit (8) and the second processing unit (9) are realized on the basis of FPGA, and the monitoring unit (10) is realized on the basis of an embedded processor;
wherein, the clock source unit (1) outputs synchronous reference clock to the first to fifth channel units (2-6) and the sampling unit (7);
the first channel unit, the second channel unit, the third channel unit, the fourth channel unit, the fifth channel unit, the sixth channel unit, the fifth channel unit and the fourth channel unit, wherein the first channel unit, the fifth channel unit, the fourth channel unit and the fourth channel unit, the fifth channel unit, the fourth channel unit, the fifth channel unit, the fourth channel, the fifth channel unit, the fifth channel, the fourth channel unit, the fifth channel, the fourth channel unit, the fourth channel, the fifth channel unit, the fourth channel unit, the fifth channel unit, the fourth channel unit, the fifth channel unit, the fourth channel unit, the fifth channel, the fourth channel unit, the fourth channel, the fifth channel, the fourth channel, the;
the sampling unit (7) converts the received 5 paths of broadband intermediate frequency analog signals into 5 paths of digital intermediate frequency signals, and then the signals are transmitted to the first processing unit (8) through the VPX back board unit (13);
the first processing unit (8) carries out parallel direction-finding processing on the 5 paths of digital intermediate frequency signals, then the processing result is sent to a network interface of the sampling unit (7) through a VPX back panel unit (13) to be output, and 1 path of digital intermediate frequency signals in the 5 paths of digital intermediate frequency signals are sent to the second processing unit (9) through the VPX back panel unit (13) to be subjected to detecting and receiving processing; the processing result of the second processing unit (9) is sent to a second interface unit (12) through a VPX back board unit (13) for output;
the first processing unit (8) comprises an interferometer direction-finding processor, 5 digital down converters and 5 FFT processors which are realized based on FPGA, wherein the 5 digital down converters receive 5 paths of digital intermediate frequency signals sent from the sampling unit (7), carry out down conversion processing on the digital intermediate frequency signals, then send the digital intermediate frequency signals to the FFT processors for FFT processing, and the 5 paths of FFT processing results enter the interferometer direction-finding processor in parallel to finish direction-finding processing;
the second processing unit (9) comprises a narrow-band digital down converter realized based on FPGA, N digital filters, N signal detectors and N signal detecting and receiving processors, wherein N is more than or equal to 8; the narrow-band digital down converter receives the 1-path digital intermediate frequency signal sent by the first processing unit (8), performs narrow-band down conversion processing on the digital intermediate frequency signal, and then respectively sends the signal to the N digital filters; n digital filters filter the input signals, and the filtered signals enter a signal detector for signal detection; the N signal detectors send the detected signals to corresponding signal detection processors to complete detection processing;
the monitoring unit is used for executing the following programs:
1) receiving a working instruction, and switching to the step 2 after the self-checking state of the equipment is normal;
2) controlling the clock source unit (1) to output a reference clock, and then turning to the step 3);
3) controlling the first to fifth channel units (2-6) to work in a specified frequency band, and then turning to the step 4);
4) setting working parameters of a first processing unit (8) and a second processing unit (9), and then turning to the step 5);
5) the working states of the clock source unit (1), the first to fifth channel units (2-6), the first processing unit (8) and the second processing unit (9) are read back at regular time, and working state data are output through the first interface unit (11);
the first interface unit (11) outputs the data output by the monitoring unit (10) through an industrial standard interface Ethernet.
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| CN113452395A (en) * | 2021-05-26 | 2021-09-28 | 中国电子科技集团公司第五十四研究所 | L frequency channel broadband signal processing device |
| CN113438012B (en) * | 2021-06-25 | 2022-09-09 | 中国电子科技集团公司第五十四研究所 | Multi-channel satellite communication device based on VPX framework |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106383338A (en) * | 2016-11-17 | 2017-02-08 | 中国电子科技集团公司第四十研究所 | Multichannel radar signal acquisition device based on digital channelization |
| CN106932753A (en) * | 2017-03-14 | 2017-07-07 | 湖南雷神电子科技有限公司 | Anti- unmanned plane passive detection and direction detecting positioning system |
| CN111044971A (en) * | 2019-12-23 | 2020-04-21 | 南京长峰航天电子科技有限公司 | Two-dimensional interferometer direction finding system |
| CN112003803A (en) * | 2020-08-10 | 2020-11-27 | 四川九洲电器集团有限责任公司 | Detection and reception equipment for VHF and UHF band aviation radio station signals |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1063267C (en) * | 1997-10-15 | 2001-03-14 | 电子工业部第五十四研究所 | Common-frequency multi-signal direction-finding and intercept receiving method and device thereof |
| US6898235B1 (en) * | 1999-12-10 | 2005-05-24 | Argon St Incorporated | Wideband communication intercept and direction finding device using hyperchannelization |
| FR2929057B1 (en) * | 2008-03-18 | 2010-04-23 | Eads Secure Networks | RADIO FREQUENCY RECEIVER LARGE MULTICHANNEL BAND |
| CN101408608B (en) * | 2008-11-21 | 2011-01-26 | 哈尔滨工程大学 | P waveband radio frequency wide opening digital receive and direction-finding integrated machine and direction-finding method |
| CN102075266B (en) * | 2010-12-27 | 2014-03-26 | 南京新兴电子系统有限公司 | Nine-channel spatial spectrum estimation super-resolution monitoring direction-finding fixed station system |
| CN203643597U (en) * | 2013-12-27 | 2014-06-11 | 中国电子科技集团公司第五十四研究所 | Mobile shortwave scouting and direction finding device |
| CN111581153A (en) * | 2020-06-09 | 2020-08-25 | 中国空气动力研究与发展中心计算空气动力研究所 | Radar signal processing device based on Open VPX |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106383338A (en) * | 2016-11-17 | 2017-02-08 | 中国电子科技集团公司第四十研究所 | Multichannel radar signal acquisition device based on digital channelization |
| CN106932753A (en) * | 2017-03-14 | 2017-07-07 | 湖南雷神电子科技有限公司 | Anti- unmanned plane passive detection and direction detecting positioning system |
| CN111044971A (en) * | 2019-12-23 | 2020-04-21 | 南京长峰航天电子科技有限公司 | Two-dimensional interferometer direction finding system |
| CN112003803A (en) * | 2020-08-10 | 2020-11-27 | 四川九洲电器集团有限责任公司 | Detection and reception equipment for VHF and UHF band aviation radio station signals |
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