CN102394808B - Method and apparatus for phase adaption and frame alignment of serial media independent interface of ethernet network - Google Patents
Method and apparatus for phase adaption and frame alignment of serial media independent interface of ethernet network Download PDFInfo
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- CN102394808B CN102394808B CN201110284476.9A CN201110284476A CN102394808B CN 102394808 B CN102394808 B CN 102394808B CN 201110284476 A CN201110284476 A CN 201110284476A CN 102394808 B CN102394808 B CN 102394808B
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Abstract
The invention discloses a method and an apparatus for phase adaption and frame alignment of a serial media independent interface (SMII) of an ethernet network. The method comprises the following steps that: when an input synchronous pulse signal comes, clearing is carried out on a counter and the counter starts to count again; when a system synchronous pulse signal comes, a trigger with clock enablement latches a counting value of the counter to obtain a phase difference delay between the input synchronous pulse signal and the system synchronous pulse signal; with regard to input data, a shift register works out data of ten kinds of different phase time delays , wherein the data contains the input data itself; and according to the phase difference delay value, a synchronization selector selects data for output from the data with ten kinds of different phase time delays, wherein the selected data are corresponded to the phase time delay and are used as output data after phase alignment is carried out again according to the system synchronous pulse signal. According to the invention, multipath source synchronous SMII (SS-SMII) data can be synchronized to a same system clock and a same frame pulse, wherein the SS-SMII data has a same source, so that a timing combination mode of a target chip or a target module can be satisfied.
Description
Technical field
The present invention relates to the communications field, particularly relate to method and the device of a kind of Ethernet serial media independent interfaces phase adaptation and frame alignment.
Background technology
SMII (Serial Media Independent Interface, serial media independent interfaces) interface is that Cisco company is at MII (Media Independent Interface, Media Independent Interface) a kind of Ethernet media interface that basis puts forward, be characterized in the serialization of MII interface framing, clock frequency is 125MHz, every frame 10 bit, adopts SYNC (lock-out pulse, every frame 10 bit) framing.Current SMII interface has become the universal serial bus standard of exchange chip ethernet mac (Medium/MediaAccess Control, medium access control) interface.
The provider that SMII interface presses timing source is different, is divided into again system synchronization SMII interface and SS-SMII (Source Synchronous SMII, the synchronous SMII in source) two kinds, interface, shown in Fig. 1 and Fig. 2.Wherein, SS-SMII (source synchronous serial Media Independent Interface) refers to reception/tranmitting data register, SYNC pulse together with data with line transmission, simultaneity factor clock Clock is the reference clock as source and place, not directly as data-interface timing, reception/tranmitting data register that data-interface timing adopts reference clock to derive from.This timing mode is more conducive to modularized design and the later stage change of circuit than timing mode.System synchronization SMII interface is then directly adopt system clock Clock as data-interface timing, and no matter frame alignment receives or send is dominated also completely by MAC side, is therefore all to export SYNC signal by mac controller.
In order to save pin number, SS-SMII interface always one group of 125MHz clock and the SYNC pulse timing multichannel data of exchange chip, shown in Figure 2, the exchange chip MAC on synchronous Zhong 16 tunnel, source, often group timing pipe 8 circuit-switched data, 2 groups altogether, this timing integrated mode is called 2x8 pattern.Obviously, when exchange chip and PHY (Physical Layer, physical chip) combination of interfaces, the timing integrated mode of PHY also must be corresponding with it.But, if the Data Source on 8 Zhong Mou road, roads is different, even the Data Source on 8 tunnels is all not identical, and different Data Sources is with different timing sources, namely clock is all different with SYNC pulse, and they are merged in same timing combination must need to retime and frame alignment.
Summary of the invention
The object of the invention is the deficiency in order to overcome above-mentioned background technology, method and the device of a kind of Ethernet serial media independent interfaces phase adaptation and frame alignment are provided, by the multichannel SS-SMII data syn-chronization of homology on same system clock and frame pulse, the timing integrated mode of objective chip or module can be met.
The method of Ethernet serial media independent interfaces phase adaptation provided by the invention and frame alignment, comprises the following steps: A, when incoming sync pulse signal arrives, and counter O reset also restarts to count; When system synchronization pulse signal arrives, the count value of the flip/flops latch counter that band clock is enable, obtains the phase difference delay of incoming sync pulse signal and systems synchronization pulse; B, shift register make the data of ten kinds of out of phase time delays to input data, comprise input data originally in interior; C, sync selector select the data of corresponding phase time delay to export according to described phase difference delay value in the data of ten kinds of out of phase time delays, as according to the output data after system synchronization pulse signal again alignment phase.
In technique scheme, comprise the following steps before steps A: adopt asynchronous First Input First Output FIFO, by derived from by system clock homology, from the serial media independent interfaces SMII bus of different clock-domains, be all fitted to system clock domain.
In technique scheme, described data fifo is formed by SMII data and lock-out pulse SYNC merging, and write clock is accompanying clock, and readout clock is system clock.
In technique scheme, shift register described in step B is made up of 9 registers.
The device of Ethernet serial media independent interfaces phase adaptation provided by the invention and frame alignment, the trigger, shift register and the sync selector that comprise counter, be with clock enable, wherein, counter is used for: when incoming sync pulse signal arrives, and resets and restarts counting; With the enable trigger of clock for: when system synchronization pulse signal arrives, the count value of latching accumulator, obtains the phase difference delay of incoming sync pulse signal and systems synchronization pulse; Shift register is used for: data input data being made to ten kinds of out of phase time delays, comprises described input data originally in interior; Sync selector is used for: in the data of ten kinds of out of phase time delays, select the data of corresponding phase time delay to export according to described phase difference delay value, as according to the output data after system synchronization pulse signal again alignment phase.
In technique scheme, also comprise adaptation module, for adopting asynchronous First Input First Output FIFO, by derived from by system clock homology, from the serial media independent interfaces SMII bus of different clock-domains, be all fitted to system clock domain.
In technique scheme, described data fifo is formed by SMII data and lock-out pulse SYNC merging, and write clock is accompanying clock, and readout clock is system clock.
In technique scheme, described shift register is made up of 9 registers.
Compared with prior art, advantage of the present invention is as follows:
The present invention adopts asynchronous FIFO to realize retiming, and data and SYNC are fitted to same clock zone; Adopt the mode of counter to measure the phase difference inputted between SYNC and system SYNC, the phase difference utilizing this to measure is selected in the data of 10 grades of time delays, thus realizes snapping in the system SYNC pulse of arbitrary phase.Regardless of SMII Data Source, the present invention can both by the multichannel SS-SMII data syn-chronization of homology on same system clock and frame pulse, the SS-SMII interface data of exchange chip is originated can be diversified, different Data Sources can align when combination in any same timing, thus meets the different SS-SMII group timing mode of exchange chip 2x4,3x8 etc.
Accompanying drawing explanation
Fig. 1 is the structural representation of system synchronization SMII interface;
The structural representation of the synchronous SMII interface of Fig. 2 and source;
Fig. 3 is the signal terminal schematic diagram of device in the embodiment of the present invention;
Fig. 4 be in the embodiment of the present invention device realize schematic diagram;
Fig. 5 is the function sequential chart of device in the embodiment of the present invention.
Embodiment
Below in conjunction with drawings and Examples, the present invention is described in further detail.
For all being derived from by system clock homology, from the SMII bus of different clock-domains, asynchronous FIFO (First Input First Output, First Input First Output) can be adopted all to be fitted to system clock domain.Attention: data fifo is formed by SMII data and SYNC merging, and write clock is accompanying clock, and readout clock is system clock.Due to clock homology, read-write enable signal all can be in enabled state always, and FIFO also can not be caused to overflow.After all adjusting to system clock domain, just can adopt method described below by alignment of data in the system SYNC pulse of arbitrary phase.
The method of the Ethernet serial media independent interfaces phase adaptation that the embodiment of the present invention provides and frame alignment, comprises the following steps:
A, when incoming sync pulse signal arrives, counter O reset also restarts counting; When system synchronization pulse signal arrives, the count value of the flip/flops latch counter that band clock is enable, obtains the phase difference delay of incoming sync pulse signal and systems synchronization pulse;
The data of ten kinds of out of phase time delays made by B, the shift register be made up of 9 registers to input data, comprise input data originally in interior;
C, sync selector select the data of corresponding phase time delay to export according to delay value in the data of ten kinds of out of phase time delays, as according to the output data after system synchronization pulse signal again alignment phase.
The device of the Ethernet serial media independent interfaces phase adaptation that the embodiment of the present invention provides and frame alignment, the trigger, shift register and the sync selector that comprise counter, be with clock enable, wherein,
Counter is used for: when incoming sync pulse signal arrives, and resets and restarts counting;
With the enable trigger of clock for: when system synchronization pulse signal arrives, the count value of latching accumulator, obtains the phase difference delay of incoming sync pulse signal and systems synchronization pulse;
Shift register is made up of 9 registers, for making the data of ten kinds of out of phase time delays to input data, comprises described input data originally in interior;
Sync selector is used for: in the data of ten kinds of out of phase time delays, select the data of corresponding phase time delay to export according to described phase difference delay value, as according to the output data after system synchronization pulse signal again alignment phase.
The device of the embodiment of the present invention also comprises adaptation module, for adopting asynchronous First Input First Output FIFO, by derived from by system clock homology, from the serial media independent interfaces SMII bus of different clock-domains, be all fitted to system clock domain.Data fifo is formed by SMII data and lock-out pulse SYNC merging, and write clock is accompanying clock, and readout clock is system clock.
Shown in Figure 3, in the embodiment of the present invention, the signal terminal of device illustrates see table 1.
Table 1, signal terminal explanation
| Sequence number | Port name | Semiotic function explanation | Attribute (I/O) |
| 1 | clk | System clock | I |
| 2 | sync_i | Input sync signal | I |
| 3 | d_i | Input data | I |
| 4 | sync_t | System sync signal | I |
| 5 | d_o | According to the output data after sync_t signal again alignment phase | O |
Shown in Figure 4, in the embodiment of the present invention, the specific implementation principle of device is described below:
Counter adopts incoming sync pulse signal sync_i to carry out synchronous reset clearing, with the enable trigger (FDCE) of the clock only value of the count value cnt of latching accumulator when system synchronization pulse signal sync_t is effective, both combines the phase difference just determining incoming sync pulse signal sync_i and system synchronization pulse signal sync_t, the time delay delay namely in Fig. 4.
For input data d_i, the shift register be made up of 9 FD registers is adopted to make the data (comprising input data d_i itself) of ten kinds of out of phase time delays.
Sync selector, according to delay signal, selects the data of corresponding phase to export, the data of sync_t of having alignd exactly in the data of ten kinds of out of phase time delays.
In the embodiment of the present invention, device corresponding function sequential is shown in Figure 5, illustrate when the phase difference of incoming sync pulse signal sync_i and system synchronization pulse signal sync_t is 4 in Fig. 5, the working condition of device in the embodiment of the present invention, is described as follows:
The count value cnt of counter Counter resets when incoming sync pulse signal sync_i arrives, and restarts counting.When system synchronization pulse signal sync_t arrives, the value meter of cnt, to 3, so just determines the phase difference of incoming sync pulse signal sync_i and system synchronization pulse signal sync_t, namely the value of delay in Fig. 5.According to the delay value 3 obtained, select the data d_d [2] of respective phase time delay as the output data d_o after alignment phase again.The situation of other nine kinds of phase difference values in like manner processes.
Obviously, when system synchronization pulse signal sync_t and incoming sync pulse signal sync_i phase difference fix, although the value of delay overturns when sync_t is effective, the value size of delay is constant.
The Verilog code that in the embodiment of the present invention, device realizes is as follows:
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong to
Within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
The content be not described in detail in this specification belongs to the known prior art of professional and technical personnel in the field.
Claims (4)
1. a method for Ethernet serial media independent interfaces phase adaptation and frame alignment, is characterized in that comprising the following steps:
Adopt asynchronous First Input First Output FIFO, by derived from by system clock homology, from the serial media independent interfaces SMII bus of different clock-domains, be all fitted to system clock domain;
A, when incoming sync pulse signal arrives, counter O reset also restarts counting; When system synchronization pulse signal arrives, the count value of the flip/flops latch counter that band clock is enable, obtains the phase difference delay of incoming sync pulse signal and systems synchronization pulse;
B, shift register make the data of ten kinds of out of phase time delays to input data, and comprise described input data originally in interior, described shift register is made up of 9 registers;
C, sync selector select the data of corresponding phase time delay to export according to described phase difference delay value in the data of ten kinds of out of phase time delays, as according to the output data after system synchronization pulse signal again alignment phase.
2. the method for Ethernet serial media independent interfaces phase adaptation as claimed in claim 1 and frame alignment, it is characterized in that: described data fifo is formed by SMII data and lock-out pulse SYNC merging, write clock is accompanying clock, and readout clock is system clock.
3. a device for Ethernet serial media independent interfaces phase adaptation and frame alignment, is characterized in that: comprise trigger, shift register and sync selector that adaptation module, counter, band clock are enable, wherein,
Adaptation module is used for: adopt asynchronous First Input First Output FIFO, by derived from by system clock homology, from the serial media independent interfaces SMII bus of different clock-domains, be all fitted to system clock domain;
Counter is used for: when incoming sync pulse signal arrives, and resets and restarts counting;
With the enable trigger of clock for: when system synchronization pulse signal arrives, the count value of latching accumulator, obtains the phase difference delay of incoming sync pulse signal and systems synchronization pulse;
Shift register is used for: data input data being made to ten kinds of out of phase time delays, and comprise described input data originally in interior, described shift register is made up of 9 registers;
Sync selector is used for: in the data of ten kinds of out of phase time delays, select the data of corresponding phase time delay to export according to described phase difference delay value, as according to the output data after system synchronization pulse signal again alignment phase.
4. the device of Ethernet serial media independent interfaces phase adaptation as claimed in claim 3 and frame alignment, it is characterized in that: described data fifo is formed by SMII data and lock-out pulse SYNC merging, write clock is accompanying clock, and readout clock is system clock.
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| CN105208467B (en) * | 2015-08-20 | 2018-05-29 | 电子科技大学 | The frame alignment means of broadband access network system |
| CN108363675B (en) * | 2018-02-05 | 2021-03-05 | 成都天诚慧芯科技有限公司 | Accompanying clock synchronization method and digital image gamma correction hardware implementation method |
| CN112188203B (en) * | 2020-09-11 | 2022-11-04 | 烽火通信科技股份有限公司 | Rapid framing method and system for high-speed data stream |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1722654A (en) * | 2004-12-31 | 2006-01-18 | 杭州华为三康技术有限公司 | Ethernet equipment time clock adjustment device |
| CN101001199A (en) * | 2006-01-11 | 2007-07-18 | 中兴通讯股份有限公司 | Data processing method of high speed multidigit parallel data bus |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1722654A (en) * | 2004-12-31 | 2006-01-18 | 杭州华为三康技术有限公司 | Ethernet equipment time clock adjustment device |
| CN101001199A (en) * | 2006-01-11 | 2007-07-18 | 中兴通讯股份有限公司 | Data processing method of high speed multidigit parallel data bus |
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