CN102394808A - Method and apparatus for phase adaption and frame alignment of serial media independent interface of ethernet network - Google Patents
Method and apparatus for phase adaption and frame alignment of serial media independent interface of ethernet network Download PDFInfo
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- CN102394808A CN102394808A CN2011102844769A CN201110284476A CN102394808A CN 102394808 A CN102394808 A CN 102394808A CN 2011102844769 A CN2011102844769 A CN 2011102844769A CN 201110284476 A CN201110284476 A CN 201110284476A CN 102394808 A CN102394808 A CN 102394808A
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Abstract
The invention discloses a method and an apparatus for phase adaption and frame alignment of a serial media independent interface (SMII) of an ethernet network. The method comprises the following steps that: when an input synchronous pulse signal comes, clearing is carried out on a counter and the counter starts to count again; when a system synchronous pulse signal comes, a trigger with clock enablement latches a counting value of the counter to obtain a phase difference delay between the input synchronous pulse signal and the system synchronous pulse signal; with regard to input data, a shift register works out data of ten kinds of different phase time delays , wherein the data contains the input data itself; and according to the phase difference delay value, a synchronization selector selects data for output from the data with ten kinds of different phase time delays, wherein the selected data are corresponded to the phase time delay and are used as output data after phase alignment is carried out again according to the system synchronous pulse signal. According to the invention, multipath source synchronous SMII (SS-SMII) data can be synchronized to a same system clock and a same frame pulse, wherein the SS-SMII data has a same source, so that a timing combination mode of a target chip or a target module can be satisfied.
Description
Technical field
The present invention relates to the communications field, particularly relate to the method and the device of a kind of Ethernet serial Media Independent Interface phase adaptation and frame alignment.
Background technology
SMII (Serial Media Independent Interface; The serial Media Independent Interface) interface is a kind of Ethernet media interface that Cisco company puts forward on MII (Media Independent Interface, Media Independent Interface) basis, is characterized in the serialization of MII interface framing; Clock frequency is 125MHz; Every frame 10 bits adopt SYNC (lock-out pulse, every frame 10 bits) to decide frame.The SMII interface has become the universal serial bus standard of exchange chip ethernet mac (Medium/MediaAccess Control, medium access control) interface at present.
The provider that the SMII interface is pressed timing source is different, is divided into two kinds system synchronization SMII interface and SS-SMII (Source Synchronous SMII, the synchronous SMII in source) interfaces again, referring to illustrated in figures 1 and 2.Wherein, SS-SMII (source synchronous serial Media Independent Interface) refers to reception/tranmitting data register, SYNC pulse and data and transmits with circuit together; Simultaneity factor clock Clock is the reference clock as source and place; Not directly not regularly, reception/tranmitting data register that data-interface regularly adopts reference clock to derive from as data-interface.This timing mode more helps the modularized design and the later stage change of circuit than system timing mode.System synchronization SMII interface then is directly to adopt system clock Clock as data-interface regularly, and no matter frame alignment receives or send also leading by MAC side fully, therefore all is by mac controller output SYNC signal.
In order to save pin number, the SS-SMII interface of exchange chip is one group of 125MHz clock and SYNC pulse timing multichannel data always, referring to shown in Figure 2; The exchange chip MAC of during the source is synchronous 16 tunnel; Regularly manage 8 circuit-switched data for every group, 2 groups altogether, this timing integrated mode is called the 2x8 pattern.Obviously, during exchange chip and PHY (Physical Layer, physical chip) combination of interfaces, the timing integrated mode of PHY also must be corresponding with it.But; If the Data Source on certain road is different in 8 the tunnel, even 8 tunnel Data Source is all inequality, different Data Sources is followed different timing sources; Be that clock is all different with the SYNC pulse, they merge in the same timing combination and must retime and the frame alignment.
Summary of the invention
The objective of the invention is in order to overcome the deficiency of above-mentioned background technology; The method and the device of the alignment of a kind of Ethernet serial Media Independent Interface phase adaptation and frame are provided; Can with the multichannel SS-SMII data sync of homology on same system clock and frame pulse, satisfy the timing integrated mode of objective chip or module.
The method of Ethernet serial Media Independent Interface phase adaptation provided by the invention and frame alignment may further comprise the steps: A, when the incoming sync pulse signal arrives, and counter O reset also restarts to count; When the system synchronization pulse signal arrived, the count value of the flip/flops latch counter that enables of band clock obtained the phase difference delay of incoming sync pulse signal and system synchronization pulse signal; B, shift register are made the data that ten kinds of outs of phase are delayed time to the input data, comprise that the input data are originally in interior; C, sync selector select the data of corresponding phase time-delay to export in the data of ten kinds of out of phase time-delays according to said phase difference delay value, as the dateout after the phase place of aliging again according to the system synchronization pulse signal.
In technique scheme, may further comprise the steps before the steps A: adopt asynchronous First Input First Output FIFO, will derive from by the system clock homology, from the serial Media Independent Interface SMII bus of different clock-domains, all be fitted to the system clock territory.
In technique scheme, said data fifo is formed by SMII data and lock-out pulse SYNC merging, and writing clock is accompanying clock, and readout clock is a system clock.
In technique scheme, shift register described in the step B is made up of 9 registers.
The device of Ethernet serial Media Independent Interface phase adaptation provided by the invention and frame alignment; Comprise trigger, shift register and sync selector that counter, band clock enable; Wherein, counter is used for: when the incoming sync pulse signal arrived, zero clearing also restarted counting; The trigger that the band clock enables is used for: when the system synchronization pulse signal arrives, latch the count value of counter, obtain the phase difference delay of incoming sync pulse signal and system synchronization pulse signal; Shift register is used for: the input data are made the data that ten kinds of outs of phase are delayed time, comprise that said input data are originally in interior; Sync selector is used for: select the data of corresponding phase time-delay to export according to said phase difference delay value in the data of ten kinds of out of phase time-delays, as the dateout after the phase place of aliging again according to the system synchronization pulse signal.
In technique scheme, also comprise adaptation module, be used to adopt asynchronous First Input First Output FIFO, will derive from by the system clock homology, from the serial Media Independent Interface SMII bus of different clock-domains, all be fitted to the system clock territory.
In technique scheme, said data fifo is formed by SMII data and lock-out pulse SYNC merging, and writing clock is accompanying clock, and readout clock is a system clock.
In technique scheme, said shift register is made up of 9 registers.
Compared with prior art, advantage of the present invention is following:
The present invention adopts asynchronous FIFO to realize retiming, and data and SYNC are fitted to same clock zone; Adopt the mode of counter to measure the phase difference between input SYNC and the SYNC of system, utilize the phase difference of this mensuration in the data of 10 grades of time-delays, to select, thereby realize snapping in the system SYNC pulse of arbitrary phase.Regardless of the SMII Data Source; The present invention can both be with the multichannel SS-SMII data sync of homology on same system clock and frame pulse; Make that the SS-SMII interface data source of exchange chip can be diversified; The same timing of can under the situation of combination in any, aliging of different Data Sources, thus satisfy the different SS-SMII group timing mode of exchange chip 2x4,3x8 or the like.
Description of drawings
Fig. 1 is the structural representation of system synchronization SMII interface;
The structural representation of the synchronous SMII interface in Fig. 2 and source;
The signal terminal sketch map of Fig. 3 for installing in the embodiment of the invention;
The realization schematic diagram of Fig. 4 for installing in the embodiment of the invention;
The function sequential chart of Fig. 5 for installing in the embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is made further detailed description.
For all by the system clock homology derive from, from the SMII bus of different clock-domains, can adopt asynchronous FIFO (First Input First Output, First Input First Output) all to be fitted to the system clock territory.Attention: data fifo is formed by SMII data and SYNC merging, and writing clock is accompanying clock, and readout clock is a system clock.Because the clock homology, the read-write enable signal can all be in enabled always, also can not cause FIFO to overflow.After all adjusting to the system clock territory, just can adopt the method that describes below with alignment of data to the system SYNC pulse of any phase place.
The method of Ethernet serial Media Independent Interface phase adaptation that the embodiment of the invention provides and frame alignment may further comprise the steps:
A, when the incoming sync pulse signal arrives, counter O reset also restarts counting; When the system synchronization pulse signal arrived, the count value of the flip/flops latch counter that enables of band clock obtained the phase difference delay of incoming sync pulse signal and system synchronization pulse signal;
B, the shift register that is made up of 9 registers make the data of ten kinds of outs of phase time-delays to the input data, comprise the input data this in interior;
C, sync selector select the data of corresponding phase time-delay to export in the data of ten kinds of out of phase time-delays according to the delay value, as the dateout after the phase place of aliging again according to the system synchronization pulse signal.
The device of Ethernet serial Media Independent Interface phase adaptation that the embodiment of the invention provides and frame alignment comprises trigger, shift register and sync selector that counter, band clock enable, wherein,
Counter is used for: when the incoming sync pulse signal arrived, zero clearing also restarted counting;
The trigger that the band clock enables is used for: when the system synchronization pulse signal arrives, latch the count value of counter, obtain the phase difference delay of incoming sync pulse signal and system synchronization pulse signal;
Shift register is made up of 9 registers, is used for the input data are made the data of ten kinds of out of phase time-delays, comprises that said input data are originally in interior;
Sync selector is used for: select the data of corresponding phase time-delay to export according to said phase difference delay value in the data of ten kinds of out of phase time-delays, as the dateout after the phase place of aliging again according to the system synchronization pulse signal.
The device of the embodiment of the invention also comprises adaptation module, is used to adopt asynchronous First Input First Output FIFO, will derive from by the system clock homology, from the serial Media Independent Interface SMII bus of different clock-domains, all be fitted to the system clock territory.Data fifo is formed by SMII data and lock-out pulse SYNC merging, and writing clock is accompanying clock, and readout clock is a system clock.
Referring to shown in Figure 3, the signal terminal explanation of installing in the embodiment of the invention is referring to table 1.
Table 1, signal terminal explanation
| Sequence number | Port name | The semiotic function explanation | Attribute (I/O) |
| 1 | clk | System clock | I |
| 2 | sync_i | Input sync signal | I |
| 3 | d_i | The input data | I |
| 4 | sync_t | System sync signal | I |
| 5 | d_o | According to the sync_t signal dateout after the phase place of aliging again | O |
Referring to shown in Figure 4, the concrete realization principle of installing in the embodiment of the invention is set forth as follows:
Counter adopts incoming sync pulse signal sync_i to carry out the synchronous reset zero clearing; The trigger (FDCE) that the band clock enables only latchs the value of the count value cnt of counter when system synchronization pulse signal sync_t is effective; The two combines just to have measured the phase difference of incoming sync pulse signal sync_i and system synchronization pulse signal sync_t, i.e. time-delay delay among Fig. 4.
To input data d_i, adopt the shift register that constitutes by 9 FD registers to make the data of ten kinds of out of phase time-delays (comprising input data d_i itself).
Sync selector is selected the data output of corresponding phase according to the delay signal in the data of ten kinds of out of phase time-delays, alignd the data of sync_t exactly.
Device function corresponding sequential is referring to shown in Figure 5 in the embodiment of the invention; Among Fig. 5 example under the phase difference of incoming sync pulse signal sync_i and system synchronization pulse signal sync_t is 4 situation; The working condition of installing in the embodiment of the invention specifies as follows:
Zero clearing when the count value cnt of counter Counter arrives at incoming sync pulse signal sync_i, and restart counting.When system synchronization pulse signal sync_t arrived, the value meter to 3 of cnt had so just been measured the phase difference of incoming sync pulse signal sync_i and system synchronization pulse signal sync_t, just the value of delay among Fig. 5.According to the delay value 3 that obtains, the dateout d_o of the data d_d [2] that selects the respective phase time-delay after as the phase place of aliging again.The situation of other nine kinds of phase difference values is in like manner handled.
Obviously, under the fixing situation of system synchronization pulse signal sync_t and incoming sync pulse signal sync_i phase difference, though the value of delay is overturn when sync_t is effective, the value size of delay is constant.
The Verilog code that device is realized in the embodiment of the invention is following:
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these revise and modification belongs to
Within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also be intended to comprise these change and modification interior.
The content of not doing in this specification to describe in detail belongs to this area professional and technical personnel's known prior art.
Claims (8)
1. the method for Ethernet serial Media Independent Interface phase adaptation and frame alignment is characterized in that may further comprise the steps:
A, when the incoming sync pulse signal arrives, counter O reset also restarts counting; When the system synchronization pulse signal arrived, the count value of the flip/flops latch counter that enables of band clock obtained the phase difference delay of incoming sync pulse signal and system synchronization pulse signal;
B, shift register are made the data that ten kinds of outs of phase are delayed time to the input data, comprise that said input data are originally in interior;
C, sync selector select the data of corresponding phase time-delay to export in the data of ten kinds of out of phase time-delays according to said phase difference delay value, as the dateout after the phase place of aliging again according to the system synchronization pulse signal.
2. the method for Ethernet serial Media Independent Interface phase adaptation as claimed in claim 1 and frame alignment; It is characterized in that: may further comprise the steps before the steps A: adopt asynchronous First Input First Output FIFO; To derive from by the system clock homology, from the serial Media Independent Interface SMII bus of different clock-domains, all be fitted to the system clock territory.
3. the method for Ethernet serial Media Independent Interface phase adaptation as claimed in claim 2 and frame alignment; It is characterized in that: said data fifo is formed by SMII data and lock-out pulse SYNC merging; Writing clock is accompanying clock, and readout clock is a system clock.
4. like the method for each described Ethernet serial Media Independent Interface phase adaptation and frame alignment in the claim 1 to 3, it is characterized in that: shift register described in the step B is made up of 9 registers.
5. the device of Ethernet serial Media Independent Interface phase adaptation and frame alignment is characterized in that: comprise trigger, shift register and sync selector that counter, band clock enable, wherein,
Counter is used for: when the incoming sync pulse signal arrived, zero clearing also restarted counting;
The trigger that the band clock enables is used for: when the system synchronization pulse signal arrives, latch the count value of counter, obtain the phase difference delay of incoming sync pulse signal and system synchronization pulse signal;
Shift register is used for: the input data are made the data that ten kinds of outs of phase are delayed time, comprise that said input data are originally in interior;
Sync selector is used for: select the data of corresponding phase time-delay to export according to said phase difference delay value in the data of ten kinds of out of phase time-delays, as the dateout after the phase place of aliging again according to the system synchronization pulse signal.
6. the device of Ethernet serial Media Independent Interface phase adaptation as claimed in claim 5 and frame alignment; It is characterized in that: also comprise adaptation module; Be used to adopt asynchronous First Input First Output FIFO; To derive from by the system clock homology, from the serial Media Independent Interface SMII bus of different clock-domains, all be fitted to the system clock territory.
7. the device of Ethernet serial Media Independent Interface phase adaptation as claimed in claim 6 and frame alignment; It is characterized in that: said data fifo is formed by SMII data and lock-out pulse SYNC merging; Writing clock is accompanying clock, and readout clock is a system clock.
8. like the device of each described Ethernet serial Media Independent Interface phase adaptation and frame alignment in the claim 5 to 7, it is characterized in that: said shift register is made up of 9 registers.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105208467A (en) * | 2015-08-20 | 2015-12-30 | 电子科技大学 | Frame aligning apparatus of broadband access network system |
| CN108363675A (en) * | 2018-02-05 | 2018-08-03 | 成都天诚慧芯科技有限公司 | A kind of accompanying clock synchronous method and digital picture gamma correction hardware implementation method |
| CN112188203A (en) * | 2020-09-11 | 2021-01-05 | 烽火通信科技股份有限公司 | Rapid framing method and system for high-speed data stream |
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| CN1722654A (en) * | 2004-12-31 | 2006-01-18 | 杭州华为三康技术有限公司 | Ethernet equipment time clock adjustment device |
| CN101001199A (en) * | 2006-01-11 | 2007-07-18 | 中兴通讯股份有限公司 | Data processing method of high speed multidigit parallel data bus |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1722654A (en) * | 2004-12-31 | 2006-01-18 | 杭州华为三康技术有限公司 | Ethernet equipment time clock adjustment device |
| CN101001199A (en) * | 2006-01-11 | 2007-07-18 | 中兴通讯股份有限公司 | Data processing method of high speed multidigit parallel data bus |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105208467A (en) * | 2015-08-20 | 2015-12-30 | 电子科技大学 | Frame aligning apparatus of broadband access network system |
| CN105208467B (en) * | 2015-08-20 | 2018-05-29 | 电子科技大学 | The frame alignment means of broadband access network system |
| CN108363675A (en) * | 2018-02-05 | 2018-08-03 | 成都天诚慧芯科技有限公司 | A kind of accompanying clock synchronous method and digital picture gamma correction hardware implementation method |
| CN108363675B (en) * | 2018-02-05 | 2021-03-05 | 成都天诚慧芯科技有限公司 | Accompanying clock synchronization method and digital image gamma correction hardware implementation method |
| CN112188203A (en) * | 2020-09-11 | 2021-01-05 | 烽火通信科技股份有限公司 | Rapid framing method and system for high-speed data stream |
| CN112188203B (en) * | 2020-09-11 | 2022-11-04 | 烽火通信科技股份有限公司 | Rapid framing method and system for high-speed data stream |
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