CN110082745B

CN110082745B - FPGA-based small MIMO radar master control machine and design method thereof

Info

Publication number: CN110082745B
Application number: CN201910354247.6A
Authority: CN
Inventors: 全英汇; 冯伟; 隋尚兼; 刘智星; 程远; 安子建; 章振栋; 马宝洋
Original assignee: Xidian University
Current assignee: Xidian University
Priority date: 2019-04-29
Filing date: 2019-04-29
Publication date: 2022-11-18
Anticipated expiration: 2039-04-29
Also published as: CN110082745A

Abstract

The invention discloses a small MIMO radar master controller based on FPGA, which comprises a clock buffer distributor, two AD9516 clock chips, two ADC chips, two DAC chips, an FPGA chip and a clock generator CDCM6208, wherein the clock buffer distributor, the two AD9516 clock chips, the two ADC chips, the two DAC chips, the FPGA chip and the clock generator CDCM6208 are arranged on a master control board. The clock buffer distributor is respectively in one-way connection with two AD9516 and CDCM6208, one AD9516 is respectively in one-way connection with two DAC chips, and the other AD9516 is respectively in one-way connection with two ADC chips; the two AD9516 and the CDCM6208 are also respectively connected with the FPGA in a one-way mode, and the DAC/ADC chip is respectively connected with the FPGA in a two-way mode; the FPGA is also unidirectionally connected with an optical fiber transceiving module, a DDR3 storage module and an antenna control module and is externally connected with a radar console. Also discloses a design method of the small MIMO radar master controller based on the FPGA.

Description

FPGA-based small MIMO radar master control machine and design method thereof

Technical Field

The invention relates to the technical field of digital signal processing, in particular to a small MIMO radar master controller based on an FPGA and a design method thereof.

Background

In recent years, MIMO radar has become a research hotspot in the field of radar as a radar of a new system. The radar adopts a multi-transmitting multi-receiving technology, orthogonal or partially related waveform signals are transmitted at a transmitting end, and a plurality of beams are formed at a receiving end by using digital beam synthesis, so that the system radar can obtain obvious performance improvement compared with a phased array radar, such as reduction of signal interception distance, improvement of weak target detection capability, solution of performance reduction caused by RCS (radar cross section) flicker of a target and the like.

In practical design, as a typical digital array radar, the MIMO radar puts higher requirements on engineering implementation. The radar needs a plurality of transceiving channels, and each path of analog signals to be transmitted and received is required to realize high-precision synchronization; meanwhile, the quantity of processed data is greatly increased due to the fact that the number of channels is large, and higher requirements are put forward on data throughput rate and real-time performance in engineering implementation; the characteristics of multiple channels and large data volume inevitably increase the number of devices, so that the volume of the equipment is increased, which is contrary to the miniaturization requirements of missile-borne and airborne radars.

Disclosure of Invention

Aiming at the problems in the prior art, the invention aims to provide a small MIMO radar master control machine based on FPGA, which can save the number of pins, greatly reduce the volume of equipment and realize the miniaturization of the radar master control machine while realizing the master control function of the MIMO radar by integrating the FPGA and a plurality of high-speed ADC/DAC chips based on JESD204B protocol on a master control board.

The invention also aims to provide a design method of the small MIMO radar master control computer based on the FPGA, which directly generates radar signals through a DAC chip with high sampling rate, effectively simplifies the design process and realizes the accurate and controllable radar waveform and phase. In addition, the data processing capacity of the radar system can be improved, and resources are saved.

In order to achieve the purpose, the invention is realized by adopting the following technical scheme.

The first technical scheme is as follows:

the utility model provides a small-size MIMO radar master control machine based on FPGA, is including setting up on the main control board: the clock buffer distributor, two AD9516 clock chips, two ADC chips, two DAC chips, an FPGA chip and a clock generator CDCM6208;

the clock buffer distributor is respectively connected with the two AD9516 clock chips and the clock generator CDCM6208 in a unidirectional mode and is used for distributing an externally input reference clock signal to the two AD9516 clock chips and the clock generator CDCM6208;

one AD9516 clock chip is respectively connected with the two DAC chips in a unidirectional mode, and the other AD9516 clock chip is respectively connected with the two ADC chips in a unidirectional mode; the two AD9516 clock chips are respectively used for providing device clocks for the DAC chip and the ADC chip;

the two AD9516 clock chips are also in one-way connection with the FPGA chip and are used for providing a reference clock, a core clock and a SYSREF reference signal for inter-chip data synchronization for the FPGA chip;

the clock generator CDCM6208 is in one-way connection with the FPGA chip and is used for providing a global clock, a DDR3 read-write reference clock and a GTH reference clock for the FPGA chip;

the DAC chip and the ADC chip are also respectively connected with the FPGA chip in a bidirectional way; the DAC chip is used for sending a playback SYNC signal to the FPGA chip, and the FPGA chip sends waveform data to the DAC chip after receiving the playback SYNC signal; the FPGA chip is also used for sending a sampling SYNC signal to the ADC chip, and the ADC chip sends sampling data to the FPGA chip after receiving the sampling SYNC signal;

the FPGA chip is also unidirectionally connected with an optical fiber transceiver module, a DDR3 storage module and an antenna control module;

the FPGA chip is also externally connected with a radar console and used for receiving radar instructions sent by the radar console.

The first technical scheme of the invention has the characteristics and further improvements that:

(1) The clock buffer distributor is LMK00105.

(2) The FPGA chip is Xilinx Virtex-7.

(3) The ADC chip is AD9680.

(4) The DAC chip is AD9136.

(5) The DAC chip and the ADC chip are respectively connected with the FPGA chip in a bidirectional mode through a JESD204B interface.

(6) The FPGA chip is externally connected with a radar console through an RS-422 interface.

(7) The FPGA chip is connected with the optical fiber module through an Aurora protocol.

The second technical scheme is as follows:

a design method of a small MIMO radar master control machine based on FPGA comprises the following steps:

step 1, designing a hardware platform: according to claim 1, a clock buffer distributor, two AD9516 clock chips, two ADC chips, two DAC chips, an FPGA chip and a clock generator CDCM6208 are respectively arranged on a main control board;

step 2, configuring an AD9516 clock chip through the SPI;

step 3, configuring two DAC chips through the SPI;

step 4, configuring two ADC chips through the SPI;

and 5, configuring a clock generator CDCM6208 through the SPI.

The second technical scheme of the invention has the characteristics and further improvements that:

(1) In step 2, configuring the AD9516 clock chip, so that the frequency of the AD9516 clock chip providing the device clock for the ADC chip is 1GHz, and the frequency of the device clock providing the DAC chip is 2GHz.

(2) In step 3, two DAC chips are configured, the output mode of each DAC chip is a dual-channel 2GSPS, the maximum spurious-free dynamic range of the output frequency spectrums of the two DAC chips is larger than-75 db, and the synchronization error is smaller than 50ps;

(3) In step 4, two ADC chips are configured, the sampling mode of each ADC chip is a dual-channel 1GSPS, the maximum spurious-free dynamic range of the sampling frequency spectrum of the two ADC chips is larger than-60 db, and the synchronization error is smaller than 50ps.

(4) In step 5, configuring a clock generator CDCM6208, so that the clock generator CDCM6208 provides a 100MHz global clock, a 133.33MHz DDR3 read-write reference clock, and an 156.25MHz optical fiber interface communication reference clock for the FPGA chip respectively

Compared with the prior art, the invention has the beneficial effects that:

the FPGA-based small MIMO radar master control machine directly samples/generates radio frequency signals by adopting a JESD 204B-based high-speed ADC/DAC chip, so that multichannel high-precision synchronization is realized, and the radar performance is improved; and the chip packaging volume is small, and the pin number is saved, so that the equipment volume is greatly reduced, and the miniaturization of the MIMO radar master control machine is realized.

Meanwhile, compared with the traditional radar design, the radar signal generating method has the advantages that the waveform data generated by the radar parameters are set according to the upper computer, the radar signals are directly generated through the high-sampling-rate DAC, the design process is simplified, and the precise and controllable radar waveform and phase are realized.

In addition, the Xilinx Virtex-7FPGA is used as a main control chip, real-time signal preprocessing is carried out on multi-path echo data in the FPGA, data processing capacity of a radar system is improved, and resources are saved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic block diagram of the structure of an embodiment of a small MIMO radar master controller based on FPGA of the present invention;

fig. 2 is a radar working timing diagram of a small MIMO radar master controller based on an FPGA according to an embodiment of the present invention;

fig. 3 is a DAC output spectrum diagram of a small MIMO radar master controller based on an FPGA according to an embodiment of the present invention;

fig. 4 is an ADC sampling data frequency spectrum diagram of a small MIMO radar master controller based on an FPGA according to an embodiment of the present invention;

fig. 5 is a four-channel ADC synchronous sampling time domain diagram of the FPGA-based small MIMO radar master controller according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The embodiment of the invention provides a small-sized MIMO radar master control machine based on an FPGA, and referring to fig. 1, fig. 1 is a structural schematic block diagram of an embodiment of the small-sized MIMO radar master control machine based on the FPGA.

The small MIMO radar master control machine based on the FPGA comprises a main control board: the clock buffer distributor, two AD9516 clock chips, two ADC chips, two DAC chips, an FPGA chip and a clock generator CDCM6208.

The clock buffer distributor is unidirectionally connected to the two AD9516 clock chips and the clock generator CDCM6208, respectively, and is configured to distribute an externally input reference clock signal to the two AD9516 clock chips and the clock generator CDCM6208.

One AD9516 clock chip is respectively connected with the two DAC chips in a unidirectional mode, and the other AD9516 clock chip is respectively connected with the two ADC chips in a unidirectional mode; the two AD9516 clock chips are respectively used for providing device clocks for the DAC chip and the ADC chip.

The two AD9516 clock chips are also in one-way connection with the FPGA chip and used for providing a reference clock, a core clock and a SYSREF reference signal for inter-chip data synchronization for the FPGA chip.

The clock generator CDCM6208 is unidirectionally connected with the FPGA chip and is used for providing a global clock, a DDR3 read-write reference clock and a GTH reference clock for the FPGA chip.

The DAC chip and the ADC chip are also respectively connected with the FPGA chip in a bidirectional way through a JESD204B interface; the DAC chip is used for sending a playback SYNC signal to the FPGA chip, and the FPGA chip sends waveform data to the DAC chip after receiving the playback SYNC signal; the FPGA chip is further used for sending sampling SYNC signals to the ADC chip, and the ADC chip sends sampling data to the FPGA chip after receiving the sampling SYNC signals.

The FPGA chip is also unidirectionally connected with an optical fiber transceiving module through an Aurora protocol, and is also unidirectionally connected with a DDR3 storage module and an antenna control module; the FPGA chip is also externally connected with a radar console through an RS-422 interface and used for receiving radar instructions sent by the radar console.

The small-sized MIMO radar master control computer based on the FPGA provided by the embodiment directly processes the radio frequency signals by using the high-speed ADC/DAC chip, and integrates modules such as the optical fiber, the storage module, the VPX module and the like, so that the radar master control function is realized. The clock buffer distributor is LMK00105, and the FPGA chip is Xilinx Virtex-7; the ADC chip is a dual-channel ADC chip with the model number of AD9680, and the DAC chip is a dual-channel DAC chip with the model number of AD9136. The FPGA chip is unidirectionally connected with two 4x optical fiber transceiving modules and two groups of 2GB DDR3 storage modules. In addition, the FPGA chip also carries out data interaction between boards through a VPX standard interface. Where the analog-to-digital hybrid and digital circuits provide clock signals using chips of model numbers AD9516 and CDCM6208, respectively.

The embodiment of the invention also provides a design method of the small MIMO radar master control machine based on the FPGA, which comprises the following steps:

step 1, designing a hardware platform: referring to fig. 1, according to the FPGA-based small MIMO radar master controller provided in the above embodiment, a clock buffer distributor, two AD9516 clock chips, two ADC chips, two DAC chips, an FPGA chip, and a clock generator CDCM6208 are respectively laid out on a master control board.

In particular, the method comprises the following steps of,

(1) In the circuit design, one ultra-low jitter clock buffer LMK00105 is used for distributing a reference clock signal from an external input to one clock chip CDCM6208 and two clock chips AD9516, wherein the two clock chips AD9516 are used for respectively providing a device clock for an ADC/DAC, providing a JESD204B reference clock and a core clock for an FPGA, and providing an inter-chip data synchronization signal SYSREF.

(2) In order to realize high-performance synchronization of the JESD204B interface, equal length processing needs to be carried out on key signal routing during layout and wiring, as shown in FIG. 1, equal length processing is respectively carried out between DAC device clock (1) of each DAC chip and DAC SYSREF signal line (2), (3) and between JESD204B signal lines of DAC, and between signals (4), (5), (6) and (4) of FPGA and DAC chips, and similarly, equal length processing is carried out between signal lines of ADC sampling part

And

between the signal lines,

Between the signal lines of (1), (8) (9) (8)

Equal length processing is also respectively carried out between the signal lines.

(3) In order to enable the radar master controller provided in this embodiment to implement high-speed data interaction with the signal processing board card, a VPX connector module is introduced in the hardware design as a redundant design, and 12 high-speed differential signal lines of the FPGA are connected to the VPX, using the SRIO protocol, as shown in fig. 1, where the 12 SRIO signal lines should perform equal-length processing.

(4) In order to avoid introducing unnecessary clock jitter, the CDCM6208 is used in the digital circuit portion in this embodiment to provide digital clocks for the DDR3, the SRIO, the optical fiber module, and the like, respectively, so as to implement isolation from the clock portion spectrum of the analog-to-digital circuit.

And 2, configuring an AD9516 clock chip through the SPI.

Specifically, an AD9516 clock chip is configured to provide a device clock for the ADC/DAC chip, wherein the clock frequency of the generated ADC device is 1GHz, and the clock frequency of the generated DAC device is 2GHz. And simultaneously, a reference clock, a JESD204B core clock and a SYSREF reference signal for data synchronization are provided for the FPGA.

And 3, configuring two DAC chips through the SPI.

Specifically, two DAC chips AD9136 are configured, an output mode is set to be a dual-channel 2GSPS, and four-channel signal synchronous output is achieved. The test is carried out by using a frequency spectrograph and a multi-channel oscilloscope respectively, the frequency spectrograms of the test are shown in figure 3, the maximum spurious-free dynamic range is larger than-75 db, and the synchronization error is smaller than 50ps.

And 4, configuring two ADC chips through the SPI.

Specifically, two ADC chips AD9680 are configured, a sampling mode is set to be a dual-channel 1GSPS, and four-channel signal synchronous sampling is achieved. The standard signal source and the power divider are used for testing, the frequency spectrogram and the time domain chart of the sampling data are respectively shown as fig. 4 and fig. 5, the maximum spurious-free dynamic range is better than-60 db, and the synchronization error is less than 50ps.

And step 5, configuring a clock generator CDCM6208 through the SPI.

Specifically, configuring the CDCM6208, generating each digital clock by using the reference clock signal in step 1 (1), providing a 100MHz global clock for the FPGA, providing a 133.33MHz DDR3 read-write reference clock, providing a 125MHz SRIO interface communication reference clock, and providing an 156.25MHz optical fiber interface communication reference clock, implementing DDR3 control in the FPGA through these clock signals, storing and reading specified waveform data, and sending the read data to the optical fiber interface through the GTH. Wherein the fiber interface communication uses the Aurora protocol.

According to the steps, a small MIMO radar master control machine based on the FPGA can be designed, the small MIMO radar master control machine utilizes the 100MHz global clock generated in the step 5, the FPGA receives a console radar command through an RS422 serial port, and identifies basic parameters and multifunctional parameters in the command, wherein the basic parameters comprise a pulse repetition period, a transmitting gate width, a blocking pulse width and a receiving gate width, the multifunctional parameters comprise a repetition frequency working mode, a repetition frequency jitter rate, a repetition frequency staggered period, a sampling signal extraction proportion, a frequency agility range and other parameters, meanwhile, the small MIMO radar master control machine receives radar transmitted waveform data, and stores the waveform data into the DDR 3.

And then generating a required radar time sequence according to the radar parameters to complete the master control function of the radar.

Specifically, according to the above-mentioned basic parameters, the radar operation timing signal shown in fig. 2 is generated, and each pulse signal in the diagram is sent to the antenna control module except for the external power-on signal, so as to implement the receiving and transmitting switching of the antenna. The antenna control module performs power amplification on the 4 paths of transmitting signals generated by the DAC chip and transmits the signals through the antenna according to the pulse control signals, and performs power amplification on echo signals received by the 4 paths of antennas and transmits the signals to the ADC chip.

When the transmitting wave gate signal is high, waveform data in DDR3 is sent to an AD9136 chip through a DACJESD204B interface, and radar signal transmission is achieved;

when the received gate signal is high, the sampling data from the AD9680 chip is received through an ADC JESD204B interface and cached in DDR3, the sampling data is extracted according to the obtained sampling signal extraction proportion parameters, matched filtering is carried out according to the filter coefficient to complete signal preprocessing, and the preprocessed data is sent to the optical fiber module through an Aurora interface.

Then, according to 4, the multi-function parameters mentioned above are completed to realize multiple radar functions and working modes.

In particular, the method comprises the following steps of,

according to the parameters of the repetition frequency working mode, the radar can work in a single repetition frequency mode (the pulse repetition period is kept unchanged), a repetition frequency staggered mode (the repetition period jumps among a plurality of given staggered periods) and a repetition frequency jittering mode (the repetition period jumps randomly according to the repetition frequency jittering rate).

According to the sampling signal extraction proportion, the sampling data can be extracted, and matched filtering is performed by using a filter in the FPGA, so that signal preprocessing is realized, and calculation and storage resources are saved for subsequent equipment.

According to the frequency agility range parameter, the received multi-frequency point waveform data is used to realize the frequency agility function between pulses in the appointed frequency band.

The effect of the small-sized MIMO radar master control machine based on the FPGA provided by the embodiment of the invention is further illustrated by the following tests:

the small MIMO radar master control machine designed by the design method provided by the embodiment of the invention can flexibly configure parameters according to the setting of the control console, transmit various radar signals such as linear frequency modulation, nonlinear frequency modulation, single carrier frequency, phase coding and the like and collect echoes, and can realize various radar functions such as repetition frequency jitter, repetition frequency spread, frequency agility, signal preprocessing and the like. Compared with the traditional MIMO radar implementation mode, all functions can be realized only by one 6U standard board card.

Through external field testing, the main control machine designed by the invention realizes the main control function of the MIMO radar and successfully searches offshore targets.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. The utility model provides a small-size MIMO radar master control machine based on FPGA which characterized in that, including setting up on the main control board: the clock buffer distributor, two AD9516 clock chips, two ADC chips, two DAC chips, an FPGA chip and a clock generator CDCM6208;

the two AD9516 clock chips are also in one-way connection with the FPGA chip and are used for providing a reference clock, a core clock and an SYSREF reference signal for data synchronization between chips for the FPGA chip;

the clock generator CDCM6208 is unidirectionally connected with the FPGA chip and is used for providing a global clock, a DDR3 read-write reference clock and a GTH reference clock for the FPGA chip;

2. The FPGA-based small MIMO radar master controller according to claim 1, wherein the clock buffer distributor is LMK00105.

3. The FPGA-based small MIMO radar master controller as claimed in claim 1, wherein the FPGA chip is Xilinx Virtex-7.

4. The FPGA-based small MIMO radar master controller according to claim 1, wherein the ADC chip is AD9680.

5. The FPGA-based small MIMO radar master controller according to claim 1, wherein the DAC chip is AD9136.

6. A design method of a small MIMO radar master control machine based on FPGA is characterized by comprising the following steps:

step 2, configuring an AD9516 clock chip through the SPI;

step 3, configuring two DAC chips through the SPI;

step 4, configuring two ADC chips through the SPI;

and step 5, configuring a clock generator CDCM6208 through the SPI.

7. The design method of small MIMO radar master controller based on FPGA according to claim 6, wherein in step 2, the AD9516 clock chip is configured, so that the frequency of the device clock provided by the AD9516 clock chip for the ADC chip is 1GHz, and the frequency of the device clock provided by the DAC chip is 2GHz.

8. The design method of FPGA-based small MIMO radar master controller, according to claim 6, wherein in step 3, two DAC chips are configured, the output mode of each DAC chip is dual-channel 2GSPS, the maximum spurious-free dynamic range of the output frequency spectrum of the two DAC chips is larger than-75 db, and the synchronization error is smaller than 50ps.

9. The design method of master controller of FPGA-based small MIMO radar as claimed in claim 6, wherein in step 4, two ADC chips are configured so that the sampling mode of each ADC chip is dual channel 1GSPS, and the maximum spurious-free dynamic range of the sampling frequency spectrum of the two ADC chips is greater than-60 db, and the synchronization error is less than 50ps.

10. The design method of small MIMO radar master controller based on FPGA of claim 6, wherein in step 5, a clock generator CDCM6208 is configured, so that said clock generator CDCM6208 provides a global clock of 100MHz, a DDR3 read-write reference clock of 133.33MHz, and a fiber interface communication reference clock of 156.25MHz for said FPGA chip, respectively.