CN110082745A - A kind of small-sized MIMO radar main controller and its design method based on FPGA - Google Patents
A kind of small-sized MIMO radar main controller and its design method based on FPGA Download PDFInfo
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- CN110082745A CN110082745A CN201910354247.6A CN201910354247A CN110082745A CN 110082745 A CN110082745 A CN 110082745A CN 201910354247 A CN201910354247 A CN 201910354247A CN 110082745 A CN110082745 A CN 110082745A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
- G01S13/02—Systems using reflection of radio waves, e.g. primary radar systems; Analogous systems
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
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Abstract
The invention discloses a kind of small-sized MIMO radar main controller based on FPGA, including clock buffer distributor, two AD9516 clock chips, two ADC chips, two DAC chips, fpga chip and the clock generator CDCM6208 being set on master control borad.Clock buffer distributor is unidirectionally connect with two AD9516 and CDCM6208 respectively, and an AD9516 is unidirectionally connect with two DAC chips respectively, another AD9516 is unidirectionally connect with two ADC chips respectively；Two AD9516 and CDCM6208 are also unidirectionally connect with FPGA respectively, and DAC/ADC chip is bi-directionally connected with FPGA respectively；FPGA is also unidirectionally connected with optical fiber receiver-transmitter module, DDR3 memory module and antenna control module, and external radar console.Also disclose a kind of design method of small-sized MIMO radar main controller based on FPGA.
Description
Technical field
The present invention relates to digital signal processing technique field more particularly to a kind of small-sized MIMO radar master controls based on FPGA
Machine and its design method.
Background technique
In recent years, MIMO radar is as a kind of new system radar, it has also become the research hotspot of field of radar.This kind of radar is adopted
Digital beam is used in receiving end by emitting the relevant waveform signal in orthogonal or part in transmitting terminal with multiple-input multiple-output technology
Multiple wave beams are synthetically formed, so that the radar be made to can get apparent performance boost compared to phased-array radar, are such as reduced
Signal interception distance is improved to dim target detection ability, is solved by target RCS flashing bring degradation problem etc..
In actual design, as a kind of typical Digital Array Radar, MIMO radar proposes Project Realization higher
Requirement.The radar needs multiple transceiver channels, and each road analog signal of transmitting-receiving is required to realize high-precise synchronization；Simultaneously because logical
Road number is more, leads to handle data volume being significantly increased, this in Project Realization data throughput and real-time propose it is higher
It is required that；And the characteristic of multichannel, big data quantity necessarily increases number of devices, increases equipment volume, this and missile-borne, airborne radar
Small form factor requirements run counter to.
Summary of the invention
Aiming at the problems existing in the prior art, the purpose of the present invention is to provide a kind of small-sized MIMO thunder based on FPGA
Up to main controller, by integrating the high-speed ADC/DAC chip of FPGA and multi-disc based on JESD204B agreement on master control borad, saving is drawn
Foot quantity can greatly reduce the volume of equipment, while realizing MIMO radar master control function, it can be achieved that radar main controller it is small
Type.
The design method of it is another object of the present invention to provide a kind of small-sized MIMO radar main controller based on FPGA,
Radar signal is directly generated by the DAC chip of high sampling rate, effectively simplifies design cycle, realizes that radar waveform and phase are accurate
Controllably.In addition, can also promote the data-handling capacity of radar system, resource is saved.
In order to achieve the above objectives, the present invention is achieved by the following scheme.
Technical solution one:
A kind of small-sized MIMO radar main controller based on FPGA, including being set on master control borad: clock buffer distributor,
Two AD9516 clock chips, two ADC chips, two DAC chips, fpga chip and clock generator CDCM6208；
The clock buffer distributor is mono- with two AD9516 clock chips and clock generator CDCM6208 respectively
To connection, for externally input reference clock signal to be distributed to two AD9516 clock chips and clock generation
Device CDCM6208；
Wherein, an AD9516 clock chip is unidirectionally connect with two DAC chips respectively, described in another
AD9516 clock chip is unidirectionally connect with two ADC chips respectively；Two AD9516 clock chips be respectively used to for
DAC chip and ADC chip provide device clock；
Two AD9516 clock chips are also unidirectionally connect with the fpga chip, for providing for the fpga chip
Reference clock, nuclear clock and the SYSREF reference signal synchronous for data between piece；
The clock generator CDCM6208 is unidirectionally connect with the fpga chip, complete for providing to the fpga chip
Office clock provides DDR3 read-write reference clock and provides GTH reference clock；
The DAC chip and ADC chip are also bi-directionally connected with the fpga chip respectively；The DAC chip is used for institute
It states fpga chip and sends playback SYNC signal, after the fpga chip receives the playback SYNC signal, Xiang Suoshu DAC chip
Send Wave data；The fpga chip is also used to send sampling SYNC signal to the ADC chip, and the ADC chip receives
To after the sampling SYNC signal, Xiang Suoshu fpga chip sends sampled data；
The fpga chip is also unidirectionally connected with optical fiber receiver-transmitter module, DDR3 memory module and antenna control module；
The also external radar console of the fpga chip, for receiving the radar command of radar console sending.
The characteristics of technical solution of the present invention one and further improvement is that
(1) the clock buffer distributor is LMK00105.
(2) fpga chip is Xilinx Virtex-7.
(3) the ADC chip is AD9680.
(4) DAC chip is AD9136.
(5) DAC chip and ADC chip pass through the two-way company of JESD204B interface between the fpga chip respectively
It connects.
(6) fpga chip passes through the external radar console of RS-422 interface.
(7) fpga chip connects optic module by Aurora agreement.
Technical solution two:
A kind of design method of the small-sized MIMO radar main controller based on FPGA, comprising the following steps:
Step 1, the design of hardware platform: according to claim 1, by clock buffer distributor, two AD9516 clock cores
Piece, two ADC chips, two DAC chips, fpga chip and clock generator CDCM6208 are laid out on master control borad respectively；
Step 2, AD9516 clock chip is configured by SPI；
Step 3, two DAC chips are configured by SPI；
Step 4, two ADC chips are configured by SPI；
Step 5, pass through SPI configurable clock generator generator CDCM6208.
The characteristics of technical solution of the present invention two and further improvement is that
(1) in step 2, AD9516 clock chip is configured, AD9516 clock chip ADC chip is made to provide device clock
Frequency is 1GHz, and the frequency for providing device clock for DAC chip is 2GHz.
(2) in step 3, two DAC chips are configured, make the output mode two-channel 2-4 GSPS of each DAC chip,
And the maximum spurious-free dynamic range of the output spectrum of two DAC chips is set to be greater than -75db, synchronous error is less than 50ps；
(3) in step 4, two ADC chips are configured, make the sampling configuration binary channels 1GSPS of each ADC chip,
And the maximum spurious-free dynamic range of the sampling frequency of two ADC chips is set to be greater than -60db, synchronous error is less than 50ps.
(4) in step 5, configurable clock generator generator CDCM6208, it is respectively described for making the clock generator CDCM6208
Fpga chip provides the global clock of 100MHz, provides the DDR3 read-write reference clock of 133.33MHz, and provide
156.25MHz optical fiber interface communication references clock
Compared with prior art, the invention has the benefit that
Small-sized MIMO radar main controller based on FPGA of the invention uses the high-speed ADC based on JESD204B/DAC core
Piece, direct sampling/generation radiofrequency signal realize that multi-channel high-accuracy is synchronous, improve radar performance；And chip package volume
It is small, pin number is saved, therefore greatly reduce equipment volume, realizes the miniaturization of MIMO radar main controller.
Meanwhile being designed compared to conventional radar, the Wave data that radar parameter generates is arranged according to host computer by the present invention, leads to
It crosses high sampling rate DAC and directly generates radar signal, simplify design cycle, realize radar waveform and phase controllable precise.
In addition, the present invention uses Xilinx Virtex-7FPGA as main control chip, to multi-path echo data in FPGA
Live signal pretreatment has been carried out, the data-handling capacity of radar system is improved, has saved resource.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is a kind of structural principle block diagram of embodiment of the small-sized MIMO radar main controller of the invention based on FPGA；
Fig. 2 is the radar working timing figure of the small-sized MIMO radar main controller provided in an embodiment of the present invention based on FPGA；
Fig. 3 is the DAC output spectrum figure of the small-sized MIMO radar main controller provided in an embodiment of the present invention based on FPGA；
Fig. 4 is the ADC sampled data frequency spectrum of the small-sized MIMO radar main controller provided in an embodiment of the present invention based on FPGA
Figure；
Fig. 5 is synchronized for the four-way ADC of the small-sized MIMO radar main controller provided in an embodiment of the present invention based on FPGA and is adopted
Sample time-domain diagram.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
The embodiment of the invention provides a kind of small-sized MIMO radar main controller based on FPGA is this hair with reference to Fig. 1, Fig. 1
A kind of structural principle block diagram of embodiment of the bright small-sized MIMO radar main controller based on FPGA.
Small-sized MIMO radar main controller based on FPGA includes being set on master control borad: clock buffer distributor, two
AD9516 clock chip, two ADC chips, two DAC chips, fpga chip and clock generator CDCM6208.
Clock buffer distributor unidirectionally connects with two AD9516 clock chips and clock generator CDCM6208 respectively
It connects, for externally input reference clock signal to be distributed to two AD9516 clock chips and the clock generator
CDCM6208。
Wherein, an AD9516 clock chip is unidirectionally connect with two DAC chips respectively, described in another
AD9516 clock chip is unidirectionally connect with two ADC chips respectively；Two AD9516 clock chips be respectively used to for
DAC chip and ADC chip provide device clock.
Two AD9516 clock chips are also unidirectionally connect with the fpga chip, for providing for the fpga chip
Reference clock, nuclear clock and the SYSREF reference signal synchronous for data between piece.
The clock generator CDCM6208 is unidirectionally connect with the fpga chip, complete for providing to the fpga chip
Office clock provides DDR3 read-write reference clock and provides GTH reference clock.
The DAC chip and ADC chip are also bi-directionally connected between the fpga chip by JESD204B interface respectively；
The DAC chip is used to send playback SYNC signal to the fpga chip, and the fpga chip receives the playback SYNC
After signal, Xiang Suoshu DAC chip sends Wave data；The fpga chip is also used to send sampling SYNC to the ADC chip
Signal, after the ADC chip receives the sampling SYNC signal, Xiang Suoshu fpga chip sends sampled data.
The fpga chip also passes through Aurora agreement and is unidirectionally connected with optical fiber receiver-transmitter module, is also unidirectionally connected with DDR3 and deposits
Store up module and antenna control module；The fpga chip also passes through the external radar console of RS-422 interface, for receiving thunder
The radar command issued up to console.
Small-sized MIMO radar main controller provided by the above embodiment based on FPGA is directly right using high-speed ADC/DAC chip
Radiofrequency signal is handled, while the modules such as integrated optical fiber, storage, VPX, to realize radar master control function.Wherein, clock is slow
Rushing distributor is LMK00105, and fpga chip is Xilinx Virtex-7；The binary channels of ADC chip selection model AD9680
ADC chip, DAC chip select the binary channels DAC chip of model AD9136.Fpga chip is unidirectionally connected with two-way 4x optical fiber receipts
Send out module and two groups of 2GB DDR3 memory modules.In addition, fpga chip, which also passes through VPX standard interface, carries out data interaction between plate.
Wherein Analog-digital circuit and digital circuit use the chip of model AD9516 and CDCM6208 to provide clock signal respectively.
The embodiment of the present invention also provides a kind of design method of small-sized MIMO radar main controller based on FPGA, including following
Step:
Step 1, the design of hardware platform: Fig. 1 is referred to, according to the small-sized MIMO thunder provided by the above embodiment based on FPGA
Up to main controller, by clock buffer distributor, two AD9516 clock chips, two ADC chips, two DAC chips, fpga chips
It is laid out on master control borad respectively with clock generator CDCM6208.
Specifically,
(1) in circuit design, using a piece of ultralow jitter clock buffer LMK00105, externally input benchmark will be come from
Clock signal is distributed to a piece of clock chip CDCM6208 and two panels clock chip AD9516, wherein using this two panels AD9516 points
Device clock is not provided for ADC/DAC, provides JESD204B reference clock and nuclear clock for FPGA, and data are same between providing piece
Walk signal SYSREF.
(2) it is the high performance synchronous for realizing JESD204B interface, is needed when being laid out wiring to key signal cabling
Carry out equal length treatment, as shown in Figure 1, between the 1. DAC device clock of each DAC chip and 2. DAC SYSREF signal wire, 3. DAC
Each road JESD204B signal wire between, between FPGA and each DAC chip 4. 5. 6. 4. all done between signal wire respectively it is isometric
Processing, similarly, ADC sampling sectionWithBetween signal wire,Each road signal wire between, 8. 9. 8.Signal wire
Between also all do equal length treatment respectively.
(3) in order to make radar main controller provided in this embodiment may be implemented and Signal transacting board analysis carry out high-speed data friendship
Mutually, therefore introduce VPX connector module in the hardware design as Redundancy Design, by the 12 road high-speed differential signal lines of FPGA with
VPX is connected, and using SRIO agreement, as shown in fig. 1, wherein this 12 road SRIO signal wire should carry out equal length treatment.
(4) to avoid introducing unnecessary clock jitter, the digital circuits section in the present embodiment uses CDCM6208 points
Not Wei DDR3, SRIO, optic module etc. digital dock is provided, realize and be isolated with the clock portion of modulus circuit spectrum point.
Step 2, AD9516 clock chip is configured by SPI.
Specifically, configuration AD9516 clock chip, provides device clock for ADC/DAC chip, wherein the ADC device generated
Clock frequency is 1GHz, and the DAC device clock frequency of generation is 2GHz.Reference clock and JESD204B core are provided simultaneously for FPGA
Clock, and the SYSREF reference signal synchronous for data.
Step 3, two DAC chips are configured by SPI.
Specifically, two DAC chip AD9136 of configuration, setting output mode is two-channel 2-4 GSPS, realizes four-way signal
Synchronism output.It is tested respectively using frequency spectrograph and multichannel oscillograph, spectrogram is as shown in figure 3, it is maximum without spuious
Dynamic range is greater than -75db, and synchronous error is less than 50ps.
Step 4, two ADC chips are configured by SPI.
Specifically, two ADC chip AD9680 of configuration, setting sampling configuration is binary channels 1GSPS, realizes four-way signal
Synchronized sampling.It is tested using standard signal source and power splitter, the spectrogram and time-domain diagram of sampled data are respectively such as Fig. 4, Fig. 5
Shown, maximum spurious-free dynamic range is better than -60db, and synchronous error is less than 50ps.
Step 5, pass through SPI configurable clock generator generator CDCM6208.
Specifically, configuration CDCM6208, generates each number word clock using the reference clock signal in step 1 (1), respectively
The global clock of 100MHz is provided for FPGA, the DDR3 read-write reference clock of 133.33MHz is provided, the SRIO for providing 125MHz connects
Port communications reference clock, and the optical fiber interface communication references clock of 156.25MHz is provided, by these clock signals in FPGA
Control of the middle realization to DDR3, is stored and is read to specified Wave data, and can be sent to the data of reading by GTH
Optical fiber interface.Wherein optical fiber interface communication uses Aurora agreement.
According to above step, a kind of small-sized MIMO radar main controller based on FPGA can be designed that, this is small-sized
In use, using 100MHz global clock caused by step 5, FPGA passes through RS422 serial ports to MIMO radar main controller
Console radar command is received, basic parameter and multi function parameter in identification instruction, wherein basic parameter includes that pulse repeats
Period, disabling pulse width, receives gatewidth at transmitting gatewidth, and multi function parameter includes that repetition operating mode, repetition are trembled
Dynamic rate, PRF staggering period, sampled signal extract the parameters such as ratio, frequency agility range, while receiving radar transmitting wave figurate number
According to by Wave data storage into DDR3.
Then the radar timing needed for being generated according to radar parameter, completes the master control function of radar.
Specifically, according to the above-mentioned basic parameter being previously mentioned, radar working sequence signal as described in Figure 2 is generated, in figure
Each pulse signal is sent to antenna control module in addition to external starting-up signal, to realize the transmitting-receiving switching of antenna.Wherein day line traffic control
Molding root tuber carries out power amplification to the 4 tunnels transmitting signal that DAC chip generates and is passed through day according to these pulse control signals
Line is emitted, while also being carried out power amplification to the echo-signal received on No. 4 antennas and being delivered to ADC chip.
When it is high for emitting gate signal, the Wave data in DDR3 is taken to be sent to by DACJESD204B interface
AD9136 chip realizes radar signal；
Hits when it is high for receiving gate signal, by ADC JESD204B interface from AD9680 chip
According to being buffered in DDR3, and extract scale parameter according to obtained sampled signal and extracted to sampled data, according to filter
Coefficient carries out matched filtering and completes Signal Pretreatment, then pretreated data are sent to optical fiber mode by Aurora interface
Block.
Then, it completes to realize many kinds of radar function and operating mode according to 4 multi function parameters mentioned above.
Specifically,
According to repetition operating mode parameter, can enable radar work substance frequency mode (pulse repetition period remains unchanged),
PRF staggering mode (repetition period jumps between given a variety of stagger cycles), repetition jitter mode (repetition period according to
Repetition jitter rate random jump).
Ratio is extracted according to sampled signal, sampled data can be extracted, is carried out using the filter inside FPGA
Matched filtering saves calculating and storage resource to realize Signal Pretreatment for subsequent equipment.
Arteries and veins can be realized in designated frequency band using the multifrequency point Wave data received according to frequency agility range parameter
Frequency agility function between punching.
The effect of small-sized MIMO radar main controller provided in an embodiment of the present invention based on FPGA is tested by following into one
Step explanation:
The small-sized MIMO radar main controller designed using design method provided in an embodiment of the present invention, can be according to console
Setting flexibly carries out parameter configuration, and many kinds of radar signals such as transmitting linear frequency modulation, nonlinear frequency modulation, single carrier frequency, phase code are simultaneously
The many kinds of radar function such as it is acquired, while can also realize repetition shake, PRF staggering, frequency agility, Signal Pretreatment to echo
Energy.And compared to traditional MIMO radar implementation, it is only necessary to which it is functional that institute can be realized in one piece of 6U standard board.
By field testing, MIMO radar master control function is realized using the main controller that the present invention designs, to naval target
Successfully scan for.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain
Lid is within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.
Claims (10)
1. a kind of small-sized MIMO radar main controller based on FPGA, which is characterized in that including being set on master control borad: clock is slow
Rush distributor, two AD9516 clock chips, two ADC chips, two DAC chips, fpga chip and clock generator
CDCM6208；
The clock buffer distributor unidirectionally connects with two AD9516 clock chips and clock generator CDCM6208 respectively
It connects, for externally input reference clock signal to be distributed to two AD9516 clock chips and the clock generator
CDCM6208；
Wherein, an AD9516 clock chip is unidirectionally connect with two DAC chips respectively, another described AD9516
Clock chip is unidirectionally connect with two ADC chips respectively；Two AD9516 clock chips are respectively used to as DAC chip
Device clock is provided with ADC chip；
Two AD9516 clock chips are also unidirectionally connect with the fpga chip, for providing reference for the fpga chip
Clock, nuclear clock and the SYSREF reference signal synchronous for data between piece；
The clock generator CDCM6208 is unidirectionally connect with the fpga chip, when for providing global to the fpga chip
Clock provides DDR3 read-write reference clock and provides GTH reference clock；
The DAC chip and ADC chip are also bi-directionally connected with the fpga chip respectively；The DAC chip is used for described
Fpga chip sends playback SYNC signal, after the fpga chip receives the playback SYNC signal, Xiang Suoshu DAC chip hair
Send Wave data；The fpga chip is also used to send sampling SYNC signal to the ADC chip, and the ADC chip receives
After the sampling SYNC signal, Xiang Suoshu fpga chip sends sampled data；
The fpga chip is also unidirectionally connected with optical fiber receiver-transmitter module, DDR3 memory module and antenna control module；
The also external radar console of the fpga chip, for receiving the radar command of radar console sending.
2. the small-sized MIMO radar main controller according to claim 1 based on FPGA, which is characterized in that the clock buffer
Distributor is LMK00105.
3. the small-sized MIMO radar main controller according to claim 1 based on FPGA, which is characterized in that the fpga chip
For Xilinx Virtex-7.
4. the small-sized MIMO radar main controller according to claim 1 based on FPGA, which is characterized in that the ADC chip
For AD9680.
5. the small-sized MIMO radar main controller according to claim 1 based on FPGA, which is characterized in that the DAC chip
For AD9136.
6. a kind of design method of the small-sized MIMO radar main controller based on FPGA, which comprises the following steps:
Step 1, the design of hardware platform: according to claim 1, by clock buffer distributor, two AD9516 clock chips, two
A ADC chip, two DAC chips, fpga chip and clock generator CDCM6208 are laid out on master control borad respectively；
Step 2, AD9516 clock chip is configured by SPI；
Step 3, two DAC chips are configured by SPI；
Step 4, two ADC chips are configured by SPI；
Step 5, pass through SPI configurable clock generator generator CDCM6208.
7. the design method of the small-sized MIMO radar main controller according to claim 6 based on FPGA, which is characterized in that step
In rapid 2, AD9516 clock chip is configured, so that AD9516 clock chip ADC chip is provided the frequency of device clock is 1GHz, is
The frequency that DAC chip provides device clock is 2GHz.
8. the design method of the small-sized MIMO radar main controller according to claim 6 based on FPGA, which is characterized in that step
In rapid 3, two DAC chips are configured, make the output mode two-channel 2-4 GSPS of each DAC chip, and make two DAC
The maximum spurious-free dynamic range of the output spectrum of chip is greater than -75db, and synchronous error is less than 50ps.
9. the design method of the small-sized MIMO radar main controller according to claim 6 based on FPGA, which is characterized in that step
In rapid 4, two ADC chips are configured, make the sampling configuration binary channels 1GSPS of each ADC chip, and make two ADC
The maximum spurious-free dynamic range of the sampling frequency of chip is greater than -60db, and synchronous error is less than 50ps.
10. the design method of the small-sized MIMO radar main controller according to claim 6 based on FPGA, which is characterized in that
In step 5, configurable clock generator generator CDCM6208, making the clock generator CDCM6208 is respectively that the fpga chip provides
The global clock of 100MHz provides the DDR3 read-write reference clock of 133.33MHz, and provides the optical fiber interface of 156.25MHz
Communication references clock.
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| CN115102549B (en) * | 2020-03-23 | 2023-03-10 | 成都华芯天微科技有限公司 | Data channel establishing method for ADC (analog to digital converter) acquisition system |
| CN111679250A (en) * | 2020-06-05 | 2020-09-18 | 西安电子科技大学 | Small frequency agility MIMO radar device based on radio frequency transceiver |
| US20230384978A1 (en) * | 2020-10-22 | 2023-11-30 | International Business Machines Corporation | Inferring the state of a write-only device |
| US12039204B2 (en) * | 2020-10-22 | 2024-07-16 | International Business Machines Corporation | Inferring the state of a write-only device by mapping control register values and feedback signal values |
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