CN115664628A - Multi-channel digital synchronous frequency conversion method and system - Google Patents
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Abstract
The invention provides a multichannel digital synchronous frequency conversion method and a system, wherein the method comprises the following steps: s1, ensuring that a synchronous mark is input into each channel of sampling data based on a plurality of channels of sampling data of a JESD204B protocol, respectively receiving the plurality of channels of sampling data through a plurality of FPGAs, and ensuring the same source of reference clock input of each FPGA; s2, updating the synchronous marks of the sampling data of a plurality of channels at regular time; s3, configuring the digital frequency conversion local oscillator of each FPGA, and keeping configuration parameters consistent; and S4, each FPGA analyzes the corresponding channel sampling data, finds out the position of the synchronous mark, triggers the enabled digital frequency conversion local oscillation working parameter by the synchronous mark, and performs synchronous digital frequency conversion processing on the data after the synchronous mark. The invention realizes the synchronous frequency conversion of digital signals among a plurality of FPGA, completely reserves the synchronous characteristic of multi-channel signals, and keeps the phase characteristic before frequency conversion among channels consistent with the phase characteristic after frequency conversion.
Description
Technical Field
The invention relates to the technical field of digital signal processing, in particular to a multi-channel digital synchronous frequency conversion method and a multi-channel digital synchronous frequency conversion system.
Background
The existing multi-channel synchronous frequency conversion technology generally processes an analog radio frequency signal before AD sampling, realizes synchronous analog frequency conversion on the signal through a homologous local oscillator signal and a multi-channel frequency converter, and performs sampling processing after frequency conversion; the more the number of the channels requiring synchronous frequency conversion, the larger the scale of the frequency converter is, which is not favorable for the miniaturization and integration of the system. The adoption of a digital frequency conversion mode can effectively reduce the use of an analog mixer, and is beneficial to system integration, the conventional AD data transmission data mostly adopts a JESD204B protocol, the JESD204B protocol can introduce uncertain delay in a transmission link, the direct utilization of data for digital frequency conversion can cause unstable change of phases among channels, the synchronism of sampling data of a plurality of channels is seriously hindered, and under the condition of high sampling rate, the processing of the sampling data of all the channels is difficult to complete due to the limited resources of one FPGA chip.
Disclosure of Invention
The invention aims to provide a multichannel digital synchronous frequency conversion method and a multichannel digital synchronous frequency conversion system, which are used for solving the problem of digital synchronous frequency conversion processing of multichannel sampling data with high sampling rate.
The invention provides a multichannel digital synchronous frequency conversion method, which comprises the following steps:
s1, ensuring that a synchronous mark is input into each channel sampling data based on a plurality of channels of sampling data of a JESD204B protocol, respectively receiving the plurality of channels of sampling data through a plurality of FPGAs, and ensuring the same source when the reference clock of each FPGA is input;
s2, updating the synchronous marks of the sampling data of a plurality of channels at regular time;
s3, configuring the digital frequency conversion local oscillator of each FPGA, and keeping configuration parameters consistent;
and S4, analyzing the corresponding channel sampling data by each FPGA, finding out the position of a synchronous mark, triggering the enabled digital frequency conversion local oscillation working parameters by the synchronous mark, and carrying out synchronous digital frequency conversion processing on the data after the synchronous mark.
Further, in step S2, the synchronization flag of the sampling data of the plurality of channels is updated once per second.
Further, in the configuration parameters in step S3, it is at least required to ensure that the initial phases of the digital frequency conversion local oscillation frequencies are kept consistent.
Furthermore, when configuring the digital frequency conversion local oscillator of each FPGA, it is necessary to complete configuration of the frequency conversion local oscillator parameter registers of all FPGAs that need to participate in digital frequency conversion processing before the synchronization mark arrives.
Further, the synchronization mark is a SYNC synchronization mark.
The invention also includes a multi-channel digital synchronous frequency conversion system, comprising:
multiple FPGAs; the multi-chip FPGA is used for receiving a plurality of channels of sampling data;
inputting a reference clock of each FPGA to be homologous, and keeping the configuration parameters of the digital frequency conversion local oscillator of each FPGA consistent;
the plurality of channel sampling data are based on a JESD204B protocol, synchronous marks are guaranteed to be punched in each channel sampling data, and the synchronous marks of the plurality of channel sampling data are updated at regular time.
In summary, due to the adoption of the technical scheme, the invention has the beneficial effects that:
the invention mainly aims at realizing the digital synchronous frequency conversion processing of real-time multi-channel signals under the condition that the multi-channel digital signals need to be processed. The invention can be used for frequency conversion processing of high sampling rate digital signals in the communication and radar fields, realizes synchronous frequency conversion of the digital signals among a plurality of FPGA, completely reserves the synchronous characteristic of multi-channel signals, and keeps the phase characteristic before frequency conversion among channels consistent with the phase characteristic after frequency conversion.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a schematic diagram of a multi-channel digital synchronous frequency conversion method and system in the embodiment of the invention.
Fig. 2 is a schematic diagram of an uncertain delay of data transmission according to an embodiment of the present invention.
FIG. 3 is a diagram illustrating data verification according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Examples
The embodiment provides a multichannel digital synchronous frequency conversion method and a multichannel digital synchronous frequency conversion system, which mainly solve the problem of digital synchronous frequency conversion processing of multichannel sampling data with high sampling rate, and have the main difficulty that single-chip FPGA (field programmable gate array) processing resources are limited, the multichannel sampling data need to be grouped into an FPGA (field programmable gate array) for digital signal processing, and when the digital frequency conversion of the multichannel sampling data is performed between different FPGAs, the multichannel digital frequency conversion method is provided to realize synchronous frequency conversion between multiple channels on the digital, and simultaneously ensure the phase difference between the channels to be stable, and finally, when the multichannel sampling data are converged and processed, each channel keeps the synchronism of signals after digital frequency conversion.
As shown in fig. 1, a multi-channel digital synchronous frequency conversion system includes:
multiple FPGAs; the multi-chip FPGA is used for receiving a plurality of channels of sampling data;
inputting a reference clock of each FPGA to be homologous, and keeping the configuration parameters of the digital frequency conversion local oscillator of each FPGA consistent;
the plurality of channel sampling data are based on a JESD204B protocol, synchronous marks are guaranteed to be punched in each channel sampling data, and the synchronous marks of the plurality of channel sampling data are updated at regular time.
Therefore, the multichannel digital synchronous frequency conversion method comprises the following steps:
s1, on the basis of a plurality of channel sampling data of a JESD204B protocol, a synchronous mark is ensured to be input into each channel sampling data, the plurality of channel sampling data are respectively received through a plurality of FPGAs, and the reference clock input of each FPGA needs to ensure the same source, so that phase drift is avoided, and the requirements of the FPGA on clock stability and clock amplitude are met;
s2, updating the synchronous marks of the sampling data of a plurality of channels at regular time; generally, the sync marks configuring the sampled data of multiple channels are updated once per second.
S3, configuring the digital frequency conversion local oscillator of each FPGA, and keeping configuration parameters consistent; at least the initial phase of the digital frequency conversion local oscillator frequency is required to be kept consistent in the configuration parameters.
And S4, each FPGA analyzes the corresponding channel sampling data, finds out the position of a synchronous mark, triggers an enabled digital frequency conversion local oscillator working parameter by a synchronous mark (SYNC), and performs synchronous digital frequency conversion processing on the data after the synchronous mark.
Furthermore, when configuring the digital frequency conversion local oscillator of each FPGA, it is necessary to complete the configuration of the frequency conversion local oscillator parameter registers of all FPGAs that need to participate in the digital frequency conversion processing before the synchronization mark arrives, so that it can be ensured that when all digital local oscillators are started, the frequency parameters are ready and the initial phases are consistent, the phase difference between the output signal after the digital frequency conversion processing and the reference channel is kept unchanged, and further, the digital synchronous frequency conversion of the multi-channel sampling data among the FPGAs is realized.
Example (a):
in system design, a clock frequency suitable for FPGA work is selected as a reference clock, and a 100Mhz reference clock is taken as an example, so that the reference clocks reaching different FPGAs are ensured to be homologous clocks.
The FPGA selects an IP core of the DDS module to generate a local oscillation clock frequency signal, the phase offset is in a locking state, and the SYNC synchronous mark is programmed and set to serve as a trigger enabling signal for switching the frequency of the DDS module, so that the frequency of the generated local oscillation signal is consistent with the initial phase.
And filtering the signal after digital frequency conversion to finally obtain a target frequency signal after frequency conversion, and simultaneously keeping the output data with SYNC synchronous marks, so that the multichannel signal synchronization can be realized by conveniently performing synchronous alignment on the subsequent data according to the SYNC synchronous marks.
Data verification:
two paths of signals are divided through a radio frequency input end, the signals are respectively input into two paths of AD acquisition, SYNC synchronous marks are marked on the synchronously acquired data, as shown in figure 2, the synchronously acquired data are respectively transmitted into 2 pieces of FPGA, and the AD data before frequency conversion and the AD data after frequency conversion are stored according to the SYNC synchronous marks, as shown in figure 3.
The sampling data of the first two channels of the frequency conversion are analyzed off line, and the phase of the signal A of the first channel is calculated to be phi through Fourier transformation 1 Calculating the phase of the second channel signal B as phi 2 Calculating the phase difference phi between the second channel sampling data and the first channel 2 -φ 1 。
Similarly, the sampling data of the two channels after frequency conversion are subjected to off-line analysis, and the phase of the signal A' of the first channel is calculated to be phi through Fourier transform 3 Calculating the second channel signal B' as the phase phi 4 Calculating the phase difference phi between the second channel sample data and the first channel 4 -φ 3 。
Comparison found that phi 2 -φ 1 Phi and phi 4 -φ 3 The equality proves that the relative phase between the channels is not influenced by the digital frequency conversion processing mode between different FPGAs, the signal synchronization characteristic is kept, and the effectiveness of the method is proved.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (6)
1. A multi-channel digital synchronous frequency conversion method is characterized by comprising the following steps:
s1, ensuring that a synchronous mark is input into each channel sampling data based on a plurality of channels of sampling data of a JESD204B protocol, respectively receiving the plurality of channels of sampling data through a plurality of FPGAs, and ensuring the same source when the reference clock of each FPGA is input;
s2, updating the synchronous marks of the sampling data of a plurality of channels at regular time;
s3, configuring the digital frequency conversion local oscillator of each FPGA, and keeping configuration parameters consistent;
and S4, each FPGA analyzes the corresponding channel sampling data, finds out the position of the synchronous mark, triggers the enabled digital frequency conversion local oscillation working parameter by the synchronous mark, and performs synchronous digital frequency conversion processing on the data after the synchronous mark.
2. The multi-channel digital synchronous frequency conversion method according to claim 1, wherein in step S2, the synchronous flag of the sampled data of the plurality of channels is updated once per second.
3. The multi-channel digital synchronous frequency conversion method according to claim 1, characterized in that in the configuration parameters in step S3, at least the initial phases of the digital frequency conversion local oscillation frequencies are required to be kept consistent.
4. The multi-channel digital synchronous frequency conversion method according to claim 1, wherein when configuring the digital frequency conversion local oscillator of each FPGA, it is necessary to complete the configuration of the frequency conversion local oscillator parameter registers of all FPGAs that need to participate in digital frequency conversion processing before the arrival of the synchronization mark.
5. The method of claim 1, wherein the synchronization mark is a SYNC synchronization mark.
6. A multi-channel digital synchronous frequency conversion system, comprising:
multiple FPGAs; the multi-chip FPGA is used for receiving a plurality of channels of sampling data;
inputting a reference clock of each FPGA to a same source, and keeping the configuration parameters of the digital frequency conversion local oscillator of each FPGA consistent;
the plurality of channel sampling data are based on a JESD204B protocol, synchronous marks are guaranteed to be punched in each channel sampling data, and the synchronous marks of the plurality of channel sampling data are updated at regular time.
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