CN103560805A - System and method for synchronously processing multiple paths of signals - Google Patents
System and method for synchronously processing multiple paths of signals Download PDFInfo
- Publication number
- CN103560805A CN103560805A CN201310577430.5A CN201310577430A CN103560805A CN 103560805 A CN103560805 A CN 103560805A CN 201310577430 A CN201310577430 A CN 201310577430A CN 103560805 A CN103560805 A CN 103560805A
- Authority
- CN
- China
- Prior art keywords
- module
- data
- multichannel
- signal
- signals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention discloses a system and method for synchronously processing multiple paths of signals. The system is applied to a mobile phone phase position difference positioning system, multiple paths of synchronous clock signals output by a synchronous clock module serve as same-source signals and are distributed to an AD module and an FPGA module, and therefore the AD module conducts synchronous sampling on multiple paths of intermediate frequency signals which are formed by converting multiple paths of carrier signals received through an external receiver, and the FPGA module conducts synchronous digital down conversion processing on the multiple paths of intermediate frequency signals, a DSP processing module encodes data undergoing synchronous digital down conversion processing and adding synchronization timestamps to the data, then, a CPCI interface transmits the multiple paths of synchronization data to an upper computer outside the system, and the upper computer extracts required data through the synchronization timestamps of the multiple paths of data and conducts phase different analysis to obtain the position coordinate of a mobile phone. According to the system, synchronous sampling of the multiple paths of carrier signals is ensured, synchronous digital down conversion processing of the multiple paths of carrier signals is achieved, and therefore phase difference positioning of the mobile phone is achieved.
Description
Technical field
The present invention relates to digital signal and direction-finding station technical field, in particular, relate to a kind of multiple signals System of Synchronous Processing and method.
Background technology
At the beginning of the origin of radio position finding radio directional bearing technology can be traced back to last century, the digital cellular mobile communication systems that start at the military requirement of World War II and the end of the eighties to promote have promoted respectively the development of this technology in military and civilian field.Mobile phone phase difference navigation system is a kind of amplitude and phase characteristic that adopts the AD HOC multipath carrier signal of receiver antenna array detection mobile phone terminal generation, extract multipath interference characteristic phase place difference, then the method for utilizing the phase difference of multipath carrier signal to position mobile phone, in system, owing to needing the phase place of multichannel multipath carrier signal, analyze, therefore must guarantee the temporal correlation of multichannel carrier signal, at this, need to apply FPGA(Field Programmable Gate Array, field programmable gate array) array processing board is realized the processing to signal.
In prior art, FPGA array processing board comprises that a power module, four FPGA process submodule, a FPGA transceiver module, an interconnect chip set module and a FPGA load-on module, FPGA processes submodule and adopts full mutual contact mode to be connected with FPGA transceiver module, the interconnected bandwidth of every two intermodules is up to 1.6B/s, this disposable plates realizes external multiple high-speed interface by pci bus, RapidIO bus, and the capacity that the carried DDRSDRAM that is 4GB, memory bandwidth is up to 10688MB/s.Although can meet the problem of embedded system to disposal ability, memory capacity and interface bandwidth high request simultaneously, but it can not guarantee the synchronous acquisition of multichannel carrier signal source, can not guarantee the synchronous frequency conversion under numeral by multichannel carrier signal, can not realize mobile phone is carried out to phase difference location.
The shortcoming existing based on above-mentioned prior art, how a kind of multiple signals synchronization processing method and device are provided, guarantee the synchronous acquisition of multichannel carrier signal source, multichannel carrier signal is realized to synchronous frequency conversion under numeral, thereby can realize, mobile phone being carried out to phase difference location, is those skilled in the art's urgent problems.
Summary of the invention
In view of this, the invention provides a kind of multiple signals System of Synchronous Processing and method, solve FPGA array processing board of the prior art and can not guarantee the synchronous acquisition of multichannel carrier signal source and can not realize multichannel carrier signal these technical problems of synchronous frequency conversion under numeral, thereby realized the object of mobile phone being carried out to phase difference location.
For achieving the above object, the invention provides following technical scheme:
A System of Synchronous Processing, this system applies, in mobile phone phase difference navigation system, comprising: synchronised clock module, FPGA module, DSP processing module, AD module, external digital receiver and CPCI interface;
Described synchronised clock module is used for the clock signal of output multi-channel homology, and the clock signal of described multichannel homology is distributed to respectively to described FPGA module and AD module;
Described external digital receiver is sent to described AD module for the multichannel carrier signal receiving is converted to multichannel intermediate-freuqncy signal;
Described FPGA module is used for according to the clock signal of homology, control described AD module described multichannel intermediate-freuqncy signal is carried out to synchronized sampling, data after synchronized sampling are done to the lower synchronous frequency conversion processing of numeral and obtain I/Q data, and described I/Q data are sent to described DSP processing module;
Described DSP processing module receives the I/Q data that FPGA module sends, and the I/Q data that receive are encoded and added synchronized timestamp;
Described CPCI interface, for multipath synchronous data being transferred to the host computer of system outside, utilizes the synchronized timestamp of multichannel data to extract the data that need by host computer, carries out the position coordinates that phase difference analysis obtains mobile phone.
Preferably, the clock signal of the multichannel homology of described synchronised clock module output is specially the clock signal of 6 tunnel homologies.
Preferably, described synchronised clock module specifically comprises crystal oscillator and clock distribution chip;
Described crystal oscillator is used for providing clock signal, and drives clock distribution chip operation;
Described clock distribution chip is used for according to the clock signal of the driver output multichannel homology of crystal oscillator, and the clock signal of described multichannel homology is distributed to respectively to described FPGA module and AD module.
Preferably, described FPGA module comprises 2 FPGA disposable plates;
Wherein, between described 2 FPGA disposable plates, specifically by synchronizing signal, undertaken synchronously.
Preferably, describedly the multichannel carrier signal receiving is converted to multichannel intermediate-freuqncy signal is specially the 8 tunnel carrier signals that receive are converted to 8 tunnel intermediate-freuqncy signals.
Preferably, described AD module specifically comprises 4 AD chips, and described each AD chip gathers 2 tunnel intermediate-freuqncy signals.
Preferably, describedly data after synchronized sampling are done to the lower synchronous frequency conversion of numeral process and be specially:
Data after sampling are sent to described FPGA module, and described FPGA module is utilized IP stone to realize synchronous frequency conversion under the numeral of multiple signals and is processed.
A synchronization processing method, the method is applied to, in mobile phone phase difference location, comprising:
Output multi-channel homology clock signal is also distributed described multichannel homology clock signal;
The multichannel carrier signal receiving is converted to multichannel intermediate-freuqncy signal;
According to homology clock signal, described multichannel intermediate-freuqncy signal is carried out to synchronized sampling and preliminary treatment, the data after synchronized sampling are done to the lower synchronous frequency conversion processing of numeral and obtain I/Q data;
Described I/Q data are encoded and added synchronized timestamp;
Utilize the synchronized timestamp of multichannel data to extract the data that need, carry out the position coordinates that phase difference analysis obtains mobile phone.
Preferably, described multichannel homology clock signal is specially the clock signal of 6 tunnel homologies.
Preferably, describedly the multichannel carrier signal receiving is converted to multichannel intermediate-freuqncy signal is specially the 8 tunnel carrier signals that receive are converted to 8 tunnel intermediate-freuqncy signals.
Known via above-mentioned technical scheme, compared with prior art, the invention discloses a kind of multiple signals System of Synchronous Processing and method, can be by the multi-path synchronous clock signal of synchronised clock module output be distributed to respectively to AD module and FPGA module as same source signal, thereby realized, multichannel intermediate-freuqncy signal that multichannel carrier signal that AD module receives external receiver converts to is carried out synchronized sampling and FPGA module is carried out synchronous frequency conversion processing under numeral to multichannel intermediate-freuqncy signal, data after DSP processing module is processed synchronous frequency conversion are encoded and add synchronized timestamp, by CPCI interface, multipath synchronous data is transferred to again to the host computer of system outside, by host computer, utilize the synchronized timestamp of multichannel data to extract the data that need, carry out phase difference analysis and obtain the position coordinates of mobile phone.The present invention compared with prior art, has guaranteed the synchronous acquisition to multichannel carrier signal, has realized the synchronous frequency conversion of multichannel carrier signal under numeral and has processed, thereby reached the object of mobile phone being carried out to phase difference location.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only embodiments of the invention, for those of ordinary skills, do not paying under the prerequisite of creative work, other accompanying drawing can also be provided according to the accompanying drawing providing.
Fig. 1 is the block diagram of the disclosed a kind of multiple signals System of Synchronous Processing of the embodiment of the present invention;
Fig. 2 is the schematic diagram of the disclosed synchronized sampling of the embodiment of the present invention;
Fig. 3 is the schematic diagram that the disclosed monolithic FPGA of embodiment of the present invention disposable plates realizes the lower synchronous frequency conversion of numeral;
Fig. 4 is the controller drawing of the disclosed synchronous processing of the embodiment of the present invention;
Fig. 5 is the flow chart of the disclosed a kind of multiple signals synchronization processing method of the embodiment of the present invention;
Embodiment
Embodiment mono-
In order to realize the synchronous acquisition to multichannel carrier signal, by multichannel carrier signal synchronous frequency conversion under numeral, thereby be able to mobile phone to carry out phase difference location, the present embodiment is following content openly, Fig. 1 is the block diagram of the disclosed a kind of multiple signals System of Synchronous Processing of the embodiment of the present invention, shown in Fig. 1, described in the multiple signals System of Synchronous Processing that is applied in mobile phone phase difference navigation system comprise: synchronised clock module 101, FPGA module 102, DSP processing module 103, AD module 104, external digital receiver 105 and CPCI interface 106;
Concrete, synchronised clock module 101 specifically comprises crystal oscillator and clock distribution chip two parts, and crystal oscillator is 52.1MHz crystal oscillator OSC, and clock distribution chip is specially precision clock and divides distribution chip AD9510, FPGA module specifically comprises two FPGA disposable plates, and AD module specifically comprises 4 AD chips.Synchronised clock module 101 is driven by the crystal oscillator OSC of 52.1MHz, and the clock signal of dividing distribution chip AD9510 to export 6 tunnel homologies by precision clock is sent to 4 AD chips and two FPGA disposable plates.
External digital receiver 105 is for introducing multichannel intermediate-freuqncy signal to AD module 104;
Concrete, external digital receiver 105 use RF cables are introduced ch1 to the carrier signal of 8 passages of ch8, and carrier signal is converted to high-frequency signal is sent to AD module 104, each AD chip in AD module 104 is responsible for respectively gathering 2 tunnel intermediate-freuqncy signals, simultaneously, external digital receiver 105 also has serial communication passage with AD module 104, for carrying out the transmission of signal.
Concrete, two FPGA disposable plates in FPGA module 102 are directly by synchronous protocol, notify the other side to sample and the operating state of Digital Down Convert, and what further guarantee to process is synchronous.Every FPGA disposable plates is responsible for respectively controlling the synchronized sampling that two AD chips carry out 4 tunnel intermediate-freuqncy signals, and the data after sampling are sent in FPGA module, utilize IP stone to realize synchronous frequency conversion under the numeral of multiple signals, the I/Q data that obtain after synchronous frequency conversion are sent to DSP processing module 103;
Between two FPGA disposable plates in the present invention, by synchronizing signal, undertaken synchronously, 8 tunnel carrier signals of external receiver are carried out to synchronized sampling and Digital Down Convert, the maximum sample rate of single channel is 80Mbps.
The I/Q data that DSP processing module 103 sends for receiving FPGA module 102, and the I/Q data that receive are encoded and added synchronized timestamp;
Dsp processor in the present invention is for coding and the synchronized timestamp sign of I/Q data, expand RS232 interface and control external receiver work, the IO of use 32bit controls the work of the aerial array of external receiver, put on display the startup NOR FLASH of 2MB and the storage Flash of 8MB simultaneously, and the DDR SDRM of 128M.
What the dsp processor using in the present invention adopted is high performance fixed-point DSP processor, its clock frequency can reach 1GHz, highest point reason ability is 4800MIPS, it has 2 extended menory interfaces (EMIF), one is 64bit(EMIFA), one is 16bit(EMIFA), can with asynchronous (SRAM, EPROM)/synchronous memories (SDRAM, SBSRAM, ZBTSRAM, FIFO) seamless link, maximum addressable scope is 1280MB; The direct memory access controller (EDMA) with expansion, can provide 64 independently DMA passages, also has the universal input/output interface (GPIO) of 16 pins in sheet.
AD sampling module in the present invention adopts 4 chip AD9251, supports 80Msps sampling, 14bit, supporting signal input amplitude 0-1.5V, AC coupled.
It is that a precision clock divides distribution chip that clock module in the present invention is used AD9510, and it has PLL core on differential clocks input, 8 road clocks outputs and the sheet of 2 road 1.6GHz.Wherein, comprise the independently 1.2GHz LVPECL clock output of 4 tunnels, LVDS or CMOS can be arranged in other 4 tunnels independently clock output: while being arranged to LVDS output, frequency can reach 800MHz; While being arranged to CMOS output, frequency can reach 250MHz.Meanwhile, this chip can also be controlled the phase delay between output clock by SPI serial programming, and shake and phase noise extremely low.
In the present invention, by 2 EMIF interface: EMIFA and the EMIFB of DSP module, the interface of expansion comprises memory interface, sdram interface, control interface.EMIFA interface clock frequency can reach 100MHz, and EMIFA interface chip selects 0 for controlling SDRAM, big or small 128MByte, data bit width 32bit; Sheet selects 1 read-write for FPGA1, big or small 16Byte, data bit width 32bit; Sheet selects 2 read-writes for FPGA2, big or small 16Byte, data bit width 32bit.The clock frequency of EMIFB interface can reach 133MHz, and sheet selects 0 for storing the read-write of NOR FLASH, big or small 8MByte, data bit width 16bit; Sheet selects 1 for starting the read-write of NOR FLASH, big or small 2MByte, data bit width 8bit; Sheet selects 2 read-writes for serial ports 0, big or small 16Byte, data bit width 8bit; Sheet selects 3 read-writes for serial ports 1, big or small 16Byte, data bit width 8bit.
Dsp processor in the present invention, for coding and the synchronized timestamp sign of I/Q data, expands RS232 interface and controls operation of receiver, and the IO of use 32bit controls the work of 8 road aerial arrays of external receiver.
The present invention uses two FPGA respectively 4 road signals to be gathered, and has overcome while carrying out multiple signals processing by monolithic FPGA, when port number too much causes that the isometric layout of system PCB signal is puzzled, the problem that antijamming capability is not strong.
Receiver of the present invention can collect the carrier signal that No. 8 mobile phones are launched by antenna array.
As shown in Figure 2, be the schematic diagram of the disclosed synchronized sampling of the embodiment of the present invention, external clock reference carries out precision clock distribution by clock module AD9510 chip, then exports 6 road clock sync signals to a 4 AD chip and two FPGA disposable plates.Because 6 road synchronizing clock signals are same source signal, be that the synchronized sampling of 8 road signals of 4 AD chips and Digital Down Convert that two FPGA carry out 8 road signals are processed and provided the foundation.Two FPGA are directly by synchronous protocol, notify the other side to sample and the operating state of Digital Down Convert, further guarantee synchronous.
The principle of the lower synchronous frequency conversion of monolithic FPGA disposable plates realization numeral is shown in Figure 3, and Fig. 3 is the schematic diagram that the disclosed monolithic FPGA of embodiment of the present invention disposable plates realizes synchronous frequency conversion under numeral, and the working method of multiple FPGA is also like this.The Hardware I P core of employing based on FPGA carries out the conversion system of multiple signals, because being adopts hardware to carry out synchronous frequency conversion to multiple signals.Can overcome the poor problem of asynchronous and real-time that software frequency conversion brings.The data of ADC sampling successively carry out forming I/Q data after mixing, cic filter, CIFR filter, PFIR filter, then by delivering to DSP after the packing of I/Q data, carry out subsequent treatment.
The dsp processor using in the present invention is provided with by the outer of FPGA module controls: 4 AD chip settings of totally 8 passages, the setting of clock distribution chip, the GPIO that FPGA outside connects (32bit output) and GPIO(2bit input), the control line of 2 passage serial port chip, the page control line of NOR FLASH, the control to FPGA internal register.Inner being and exporting FIFO of being connected with DSP of FPGA, communicating by letter between FPGA and DSP, the sheet of use EMIFA interface select 1 and sheet select 2.Output data through FPGA Digital Down Convert are I/Q data, the signed number of each 16bit, and I/Q is one group, forms altogether the data of 32bit so that DSP access; Every FPGA controls 4 passages, and FPGA only has inside 1 FIFO, and the data polling of 8 passages deposits in FIFO so that DSP reads.
Fig. 4 is the controller drawing of the disclosed synchronous processing of the embodiment of the present invention, as shown in Figure 4, after dsp processor power supply, first carry out system initialization, each configuration register is set each functional module of DSP is moved by designing requirement, main configuration pin is multiplexing, PLL, PSC and EMIF.FPGA starts simultaneously and starts to control AD9251 and starts image data, the Hardware I P core that carrier signal process AD sampling enters FPGA carries out Digital Down Convert, baseband I/Q data after frequency conversion are carried out the fifo buffer of FPGA, when the data volume in FIFO reaches preseting length, and output interrupt signal.Because the general GPIO pin of interrupt signal line for this reason and DSP is connected, the EDMA3 controller of DSP inside can detect this GPIO and interrupt affairs, and produce a transmission request, according to the parameter of setting, data are transferred to the SDRAM memory of DSP module from the output FIFO in FPGA.After completing this EDMA transmission request, trigger an EDMA and interrupt, in interrupt service routine, detect data length in SDRAM.Between two FPGA, use synchronous protocol to notify the other side operating state.Finally, when the data length of sdram memory storage reaches the length of setting, trigger coding and synchronized timestamp function and carry out synchronizing signal processing, the signal after processing can be read by the synchronous CPCI interface of host computer.
Embodiment bis-
On the basis of embodiment mono-, the embodiment of the present application also provides a kind of multiple signals synchronization processing method, as shown in Figure 5, and the schematic flow sheet of a kind of multiple signals synchronization processing method providing for the embodiment of the present application.
The method is applied to, in mobile phone phase difference location, comprising:
Step S1: export and distribute multichannel homology clock signal.
Multichannel is specially the 6 same source signals in tunnel with source signal, exports rear and distributes, and as synchronizing signal, indicates the synchronous acquisition of carrier signal and processing.
Step S2: the multichannel carrier signal receiving is converted to multichannel intermediate-freuqncy signal;
Be specially the 8 tunnel carrier signals that receive are converted to 8 tunnel intermediate-freuqncy signals.
Step S3: according to homology clock signal, multichannel intermediate-freuqncy signal is carried out to synchronized sampling, do the lower synchronous frequency conversion processing of numeral and obtain I/Q data;
Step S4: I/Q data are encoded and added synchronized timestamp;
Step S5: utilize the synchronized timestamp of multichannel data to extract the data that need, carry out the position coordinates that phase difference analysis obtains mobile phone.
From above technical scheme, this multiple signals synchronization processing method that the embodiment of the present application provides, can be by the multi-path synchronous clock signal of synchronised clock module output be distributed to respectively to AD module and FPGA module as same source signal, thereby realized, multichannel intermediate-freuqncy signal that multichannel carrier signal that AD module receives external receiver converts to is carried out synchronized sampling and FPGA module is carried out synchronous frequency conversion processing under numeral to multichannel intermediate-freuqncy signal, data after DSP processing module is processed synchronous frequency conversion are encoded and add synchronized timestamp, by CPCI interface, multipath synchronous data is transferred to again to the host computer of system outside, by host computer, utilize the synchronized timestamp of multichannel data to extract the data that need, carry out phase difference analysis and obtain the position coordinates of mobile phone.The present invention compared with prior art, has guaranteed the synchronous acquisition to multichannel carrier signal, has realized the synchronous frequency conversion of multichannel carrier signal under numeral and has processed, thereby reached the object of mobile phone being carried out to phase difference location.
Also it should be noted that, in this article, relational terms such as the first and second grades is only used for an entity or operation to separate with another entity or operating space, and not necessarily requires or imply and between these entities or operation, have the relation of any this reality or sequentially.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thereby the process, method, article or the equipment that make to comprise a series of key elements not only comprise those key elements, but also comprise other key elements of clearly not listing, or be also included as the intrinsic key element of this process, method, article or equipment.The in the situation that of more restrictions not, the key element being limited by statement " comprising ... ", and be not precluded within process, method, article or the equipment that comprises described key element and also have other identical element.
The software module that the method for describing in conjunction with embodiment disclosed herein or the step of algorithm can directly use hardware, processor to carry out, or the combination of the two is implemented.Software module can be placed in the storage medium of any other form known in random asccess memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or technical field.
Above-mentioned explanation to the disclosed embodiments, makes professional and technical personnel in the field can realize or use the present invention.To the multiple modification of these embodiment, will be apparent for those skilled in the art, General Principle as defined herein can, in the situation that not departing from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention will can not be restricted to these embodiment shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (10)
1. a multiple signals System of Synchronous Processing, is characterized in that, this system applies, in mobile phone phase difference navigation system, comprising: synchronised clock module, FPGA module, DSP processing module, AD module, external digital receiver and CPCI interface;
Described synchronised clock module is used for the clock signal of output multi-channel homology, and the clock signal of described multichannel homology is distributed to respectively to described FPGA module and AD module;
Described external digital receiver is sent to described AD module for the multichannel carrier signal receiving is converted to multichannel intermediate-freuqncy signal;
Described FPGA module is used for according to the clock signal of described homology, control described AD module described multichannel intermediate-freuqncy signal is carried out to synchronized sampling, data after synchronized sampling are done to the lower synchronous frequency conversion processing of numeral and obtain I/Q data, and described I/Q data are sent to described DSP processing module;
The I/Q data that described DSP processing module sends for receiving FPGA module, and the I/Q data that receive are encoded and added synchronized timestamp;
Described CPCI interface, for multipath synchronous data being transferred to the host computer of system outside, utilizes the synchronized timestamp of multichannel data to extract the data that need by host computer, carries out the position coordinates that phase difference analysis obtains mobile phone.
2. system according to claim 1, is characterized in that, the clock signal of the multichannel homology of described synchronised clock module output is specially the clock signal of 6 tunnel homologies.
3. system according to claim 1, described synchronised clock module specifically comprises crystal oscillator and clock distribution chip;
Described crystal oscillator is used for providing clock signal, and drives clock distribution chip operation;
Described clock distribution chip is used for according to the clock signal of the driver output multichannel homology of crystal oscillator, and the clock signal of described multichannel homology is distributed to respectively to described FPGA module and AD module.
4. system according to claim 1, is characterized in that, described FPGA module comprises 2 FPGA disposable plates;
Wherein, between described 2 FPGA disposable plates, specifically by synchronizing signal, undertaken synchronously.
5. system according to claim 1, is characterized in that, describedly the multichannel carrier signal receiving is converted to multichannel intermediate-freuqncy signal is specially the 8 tunnel carrier signals that receive are converted to 8 tunnel intermediate-freuqncy signals.
6. system according to claim 5, is characterized in that, described AD module specifically comprises 4 AD chips, and described each AD chip gathers 2 tunnel intermediate-freuqncy signals.
7. system according to claim 1, is characterized in that, describedly data after synchronized sampling are done to the lower synchronous frequency conversion of numeral processes and is specially:
Data after sampling are sent to described FPGA module, and described FPGA module is utilized IP stone to realize synchronous frequency conversion under the numeral of multiple signals and is processed.
8. a multiple signals synchronization processing method, is characterized in that, the method is applied to, in mobile phone phase difference location, comprising:
Output multi-channel homology clock signal is also distributed described multichannel homology clock signal;
The multichannel carrier signal receiving is converted to multichannel intermediate-freuqncy signal;
According to described homology clock signal, described multichannel intermediate-freuqncy signal is carried out to synchronized sampling, the data after synchronized sampling are done to the lower synchronous frequency conversion processing of numeral and obtain I/Q data;
Described I/Q data are encoded and added synchronized timestamp;
Utilize the synchronized timestamp of multichannel data to extract the data that need, carry out the position coordinates that phase difference analysis obtains mobile phone.
9. method according to claim 8, is characterized in that, described multichannel homology clock signal is specially the clock signal of 6 tunnel homologies.
10. method according to claim 8, is characterized in that, describedly the multichannel carrier signal receiving is converted to multichannel intermediate-freuqncy signal is specially the 8 tunnel carrier signals that receive are converted to 8 tunnel intermediate-freuqncy signals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310577430.5A CN103560805B (en) | 2013-11-18 | 2013-11-18 | A kind of multiple signals System of Synchronous Processing and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310577430.5A CN103560805B (en) | 2013-11-18 | 2013-11-18 | A kind of multiple signals System of Synchronous Processing and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103560805A true CN103560805A (en) | 2014-02-05 |
| CN103560805B CN103560805B (en) | 2016-02-03 |
Family
ID=50014981
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310577430.5A Active CN103560805B (en) | 2013-11-18 | 2013-11-18 | A kind of multiple signals System of Synchronous Processing and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103560805B (en) |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104467852A (en) * | 2014-11-24 | 2015-03-25 | 中国电子科技集团公司第二十九研究所 | Multi-channel AD synchronization method based on clock phase shifting technology |
| CN104931780A (en) * | 2015-05-20 | 2015-09-23 | 梧州学院 | Synchronous sampling, converting and acquiring device for power harmonic 16-channel signal input |
| CN105162542A (en) * | 2015-07-16 | 2015-12-16 | 中国电子科技集团公司第四十一研究所 | Distributed multichannel high-speed synchronous clock circuit and distributed multichannel high-speed synchronous clock generating method |
| CN105471776A (en) * | 2015-11-26 | 2016-04-06 | 京信通信系统（广州）有限公司 | Signal transmission method and device |
| CN106130943A (en) * | 2016-06-02 | 2016-11-16 | 上海交通大学 | A kind of continuous variable quantum key distribution system collecting method and system |
| CN107369339A (en) * | 2017-08-29 | 2017-11-21 | 中国民用航空总局第二研究所 | ADS B downlink datas link analysis checking system based on CPCI frameworks |
| CN107404623A (en) * | 2017-07-10 | 2017-11-28 | 中国民用航空总局第二研究所 | The remote receiver and method of multipoint location system based on CPCI frameworks |
| CN107733546A (en) * | 2017-11-07 | 2018-02-23 | 武汉华讯国蓉科技有限公司 | A kind of time information synchronization system and method |
| CN111125978A (en) * | 2019-12-31 | 2020-05-08 | 国微集团(深圳)有限公司 | Simulation data processing method and system |
| CN111459009A (en) * | 2020-04-21 | 2020-07-28 | 哈尔滨工业大学 | Random error estimation system and estimation method for synchronization of multiple digital electronic devices |
| CN112698363A (en) * | 2020-12-29 | 2021-04-23 | 成都国星通信有限公司 | High-precision data acquisition method and acquisition circuit for Beidou anti-interference antenna |
| CN113839767A (en) * | 2021-09-13 | 2021-12-24 | 许昌许继软件技术有限公司 | Multi-chip FPGA system and timestamp synchronization method thereof |
| CN114285454A (en) * | 2021-11-26 | 2022-04-05 | 广东省大湾区集成电路与系统应用研究院 | Broadband signal acquisition and processing system |
| CN114812673A (en) * | 2022-04-02 | 2022-07-29 | 北京卫星环境工程研究所 | Multi-parameter multi-module optical fiber data synchronous testing method |
| CN115664628A (en) * | 2022-10-24 | 2023-01-31 | 中国电子科技集团公司第二十九研究所 | Multi-channel digital synchronous frequency conversion method and system |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6301311B1 (en) * | 1999-02-10 | 2001-10-09 | Anritsu Company | Non-coherent, non-data-aided pseudo-noise synchronization and carrier synchronization for QPSK or OQPSK modulated CDMA system |
| CN101587498A (en) * | 2009-06-24 | 2009-11-25 | 北京理工大学 | Dual-mode signal acquiring board |
| CN102185629A (en) * | 2011-04-28 | 2011-09-14 | 上海交通大学 | Accurate synchronized device of BOC (binary offset carrier) signals and synchronized method thereof |
| JP2012165208A (en) * | 2011-02-07 | 2012-08-30 | Nec Engineering Ltd | Spread spectrum signal synchronization receiver |
| CN203164412U (en) * | 2013-04-01 | 2013-08-28 | 武汉中软通科技有限公司 | Direction positioning system based on multi-antenna synchronous acquisition of wireless signals |
-
2013
- 2013-11-18 CN CN201310577430.5A patent/CN103560805B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6301311B1 (en) * | 1999-02-10 | 2001-10-09 | Anritsu Company | Non-coherent, non-data-aided pseudo-noise synchronization and carrier synchronization for QPSK or OQPSK modulated CDMA system |
| CN101587498A (en) * | 2009-06-24 | 2009-11-25 | 北京理工大学 | Dual-mode signal acquiring board |
| JP2012165208A (en) * | 2011-02-07 | 2012-08-30 | Nec Engineering Ltd | Spread spectrum signal synchronization receiver |
| CN102185629A (en) * | 2011-04-28 | 2011-09-14 | 上海交通大学 | Accurate synchronized device of BOC (binary offset carrier) signals and synchronized method thereof |
| CN203164412U (en) * | 2013-04-01 | 2013-08-28 | 武汉中软通科技有限公司 | Direction positioning system based on multi-antenna synchronous acquisition of wireless signals |
Cited By (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104467852A (en) * | 2014-11-24 | 2015-03-25 | 中国电子科技集团公司第二十九研究所 | Multi-channel AD synchronization method based on clock phase shifting technology |
| CN104467852B (en) * | 2014-11-24 | 2017-11-03 | 中国电子科技集团公司第二十九研究所 | A kind of multi-channel A/D synchronous method based on clock phase shift technology |
| CN104931780B (en) * | 2015-05-20 | 2017-08-25 | 梧州学院 | A kind of channel signal of electric harmonic 16 inputs synchronized sampling conversion and acquisition device |
| CN104931780A (en) * | 2015-05-20 | 2015-09-23 | 梧州学院 | Synchronous sampling, converting and acquiring device for power harmonic 16-channel signal input |
| CN105162542A (en) * | 2015-07-16 | 2015-12-16 | 中国电子科技集团公司第四十一研究所 | Distributed multichannel high-speed synchronous clock circuit and distributed multichannel high-speed synchronous clock generating method |
| CN105471776B (en) * | 2015-11-26 | 2019-04-16 | 京信通信系统（中国）有限公司 | A kind of method for transmitting signals and device |
| CN105471776A (en) * | 2015-11-26 | 2016-04-06 | 京信通信系统（广州）有限公司 | Signal transmission method and device |
| CN106130943A (en) * | 2016-06-02 | 2016-11-16 | 上海交通大学 | A kind of continuous variable quantum key distribution system collecting method and system |
| CN107404623A (en) * | 2017-07-10 | 2017-11-28 | 中国民用航空总局第二研究所 | The remote receiver and method of multipoint location system based on CPCI frameworks |
| CN107404623B (en) * | 2017-07-10 | 2020-06-23 | 中国民用航空总局第二研究所 | Remote receiver and method of multipoint positioning system based on CPCI architecture |
| CN107369339A (en) * | 2017-08-29 | 2017-11-21 | 中国民用航空总局第二研究所 | ADS B downlink datas link analysis checking system based on CPCI frameworks |
| CN107733546B (en) * | 2017-11-07 | 2023-11-10 | 武汉华讯国蓉科技有限公司 | Time information synchronization system and method |
| CN107733546A (en) * | 2017-11-07 | 2018-02-23 | 武汉华讯国蓉科技有限公司 | A kind of time information synchronization system and method |
| CN111125978A (en) * | 2019-12-31 | 2020-05-08 | 国微集团(深圳)有限公司 | Simulation data processing method and system |
| CN111459009A (en) * | 2020-04-21 | 2020-07-28 | 哈尔滨工业大学 | Random error estimation system and estimation method for synchronization of multiple digital electronic devices |
| CN111459009B (en) * | 2020-04-21 | 2021-08-17 | 哈尔滨工业大学 | Random error estimation system and estimation method for synchronization of multiple digital electronic devices |
| CN112698363A (en) * | 2020-12-29 | 2021-04-23 | 成都国星通信有限公司 | High-precision data acquisition method and acquisition circuit for Beidou anti-interference antenna |
| CN112698363B (en) * | 2020-12-29 | 2024-04-16 | 成都国星通信有限公司 | High-precision data acquisition method and acquisition circuit for Beidou anti-interference antenna |
| CN113839767A (en) * | 2021-09-13 | 2021-12-24 | 许昌许继软件技术有限公司 | Multi-chip FPGA system and timestamp synchronization method thereof |
| CN114285454A (en) * | 2021-11-26 | 2022-04-05 | 广东省大湾区集成电路与系统应用研究院 | Broadband signal acquisition and processing system |
| CN114812673A (en) * | 2022-04-02 | 2022-07-29 | 北京卫星环境工程研究所 | Multi-parameter multi-module optical fiber data synchronous testing method |
| CN114812673B (en) * | 2022-04-02 | 2023-11-10 | 北京卫星环境工程研究所 | Multi-parameter multi-module optical fiber data synchronous test method |
| CN115664628A (en) * | 2022-10-24 | 2023-01-31 | 中国电子科技集团公司第二十九研究所 | Multi-channel digital synchronous frequency conversion method and system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103560805B (en) | 2016-02-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103560805B (en) | A kind of multiple signals System of Synchronous Processing and method | |
| US9426749B2 (en) | Method and apparatus for Bluetooth-based Wi-Fi synchronization | |
| RU2015126332A (en) | A terminal supporting multiple modes and a handover method for such a terminal | |
| CN103209431B (en) | Wireless Multi-Channel data collector | |
| CN204178360U (en) | A kind of multiplexed signal sampling treatment circuit | |
| CN109104260B (en) | The synchronous method of plate card type multichannel data acquisition system | |
| CN103593487A (en) | Signal acquisition processing board | |
| CN100391171C (en) | Installation and system for testing data in baseband protocol in third generation mobile communication system | |
| CN204046839U (en) | A kind of heterogeneous polynuclear high speed radio transmission equipment | |
| CN205787098U (en) | A kind of distributed external illuminators-based radar multi-channel data acquisition unit | |
| CN103379670A (en) | Multi-mode terminal | |
| CN102567272B (en) | Method for improving working frequency of SPI (Serial Peripheral Interface) circuit | |
| CN203590225U (en) | Ultra long distance bluetooth communication module | |
| CN103944601A (en) | PCIE (peripheral component interface express) interface based software radio frequency transmitter-receiver and method | |
| CN110855996A (en) | Image coding and decoding and network transmission method and device based on FPGA | |
| CN107247252A (en) | Produce the device of multichannel coherent analog signal | |
| CN102571317A (en) | Data synchronization method and system based on PCI bus in software radio system | |
| CN203482410U (en) | 4G multi-frequency multi-mode mobile communication module | |
| CN114025426A (en) | Indoor positioning system combining Bluetooth AOA and RSSI | |
| CN203071918U (en) | Software radio frequency card supporting intelligent antenna | |
| JP3126594U (en) | PCI-Express multi-mode expansion card and communication device including the expansion card | |
| CN206894677U (en) | A kind of display screen route board with WIFI | |
| CN102999465B (en) | High-speed digital signal integrated processing device for wireless communication | |
| CN202033737U (en) | FPGA-based high-speed data acquisition system | |
| CN206627619U (en) | A kind of multiband minimizes external radiation source radar system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20210401 Address after: 621000 No.98 Youxian East Road, Youxian District, Mianyang City, Sichuan Province Patentee after: MIANYANG WEIBO ELECTRONIC Co.,Ltd. Patentee after: China Ordnance Equipment Group Automation Research Institute Co.,Ltd. Address before: 621000 No.98 Youxian East Road, Youxian District, Mianyang City, Sichuan Province Patentee before: MIANYANG WEIBO ELECTRONIC Co.,Ltd. Patentee before: SICHUAN MIANYANG SOUTHWEST AUTOMATION INSTITUTE |
|
| TR01 | Transfer of patent right |