CN103560805B - A kind of multiple signals System of Synchronous Processing and method - Google Patents
A kind of multiple signals System of Synchronous Processing and method Download PDFInfo
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Abstract
The invention discloses a kind of multiple signals System of Synchronous Processing and method, this system is applied in mobile phone phase difference navigation system, A/D module and FPGA module is distributed to respectively as homologous signal by multi-path synchronous clock signal synchronised clock module exported, thus achieve A/D module and synchronized sampling is carried out to the multichannel intermediate-freuqncy signal that the multichannel carrier signal that external receiver receives converts to and FPGA module carries out synchronous frequency conversion process under numeral to multichannel intermediate-freuqncy signal, data after synchronous frequency conversion process carry out encoding and adding synchronized timestamp by DSP processing module, by CPCI interface, multipath synchronous data is transferred to the host computer of its exterior again, the synchronized timestamp of multichannel data is utilized to extract the data of needs by host computer, carry out the position coordinates that phase difference analysis obtains mobile phone.This system ensure that the synchronous acquisition to multichannel carrier signal, achieve the synchronous frequency conversion process of multichannel carrier signal under numeral, thus reach phase difference location is carried out to mobile phone.
Description
Technical field
The present invention relates to digital signal and direction-finding station technical field, in particular, relate to a kind of multiple signals System of Synchronous Processing and method.
Background technology
The origin of radio-location technology can be traced back at the beginning of last century, and the digital cellular mobile communication systems starting at the military requirement of World War II and the end of the eighties to promote have promoted the development of this technology in military and civilian field respectively.Mobile phone phase difference navigation system is a kind of amplitude and phase characteristic of the AD HOC multipath carrier signal adopting receiver antenna array detection mobile phone terminal to produce, extract multi-path jamming proper phase difference, then the method that the phase difference of multipath carrier signal positions mobile phone is utilized, in systems in which, analyze owing to needing the phase place of multichannel multipath carrier signal, therefore the temporal correlation of multichannel carrier signal must be ensured, at this, need to apply FPGA(FieldProgrammableGateArray, field programmable gate array) array processing board realizes to signal process.
In prior art, FPGA disposable plates comprises a power module, four FPGA process submodules, FPGA transceiver module, an interconnect chip set module and a FPGA load-on module, FPGA process submodule and FPGA transceiver module adopt full mutual contact mode to be connected, the interconnected bandwidth of every two intermodules is up to 1.6B/s, this disposable plates realizes external multiple high-speed interface by pci bus, RapidIO bus, and having carried the DDRSDRAM that capacity is 4GB, memory bandwidth is up to 10688MB/s.Although the problem of embedded system to disposal ability, memory capacity and interface bandwidth high request can be met simultaneously, but it can not ensure the synchronous acquisition of multichannel carrier signal source, can not ensure the synchronous frequency conversion of multichannel carrier signal under numeral, can not realize carrying out phase difference location to mobile phone.
Based on the shortcoming that above-mentioned prior art exists, how a kind of multiple signals synchronization processing method and device are provided, ensure the synchronous acquisition of multichannel carrier signal source, multichannel carrier signal is realized synchronous frequency conversion under numeral, thus can realize carrying out phase difference location to mobile phone, be those skilled in the art's urgent problems.
Summary of the invention
In view of this, the invention provides a kind of multiple signals System of Synchronous Processing and method, solve FPGA disposable plates of the prior art can not ensure the synchronous acquisition of multichannel carrier signal source and can not realize multichannel carrier signal these technical problems of synchronous frequency conversion under numeral, thus achieve the object of mobile phone being carried out to phase difference location.
For achieving the above object, the invention provides following technical scheme:
A kind of multiple signals System of Synchronous Processing, this system is applied in mobile phone phase difference navigation system, comprising: synchronised clock module, FPGA module, DSP processing module, A/D module, external digital receiver and CPCI interface;
Described synchronised clock module is used for the clock signal of output multi-channel homology, and the clock signal of described multichannel homology is distributed to described FPGA module and A/D module respectively;
Described external digital receiver is used for that the multichannel carrier signal received is converted to multichannel intermediate-freuqncy signal and is sent to described A/D module;
Described FPGA module is used for the clock signal according to homology, control described A/D module and synchronized sampling is carried out to described multichannel intermediate-freuqncy signal, data after synchronized sampling are done the lower synchronous frequency conversion process of numeral and obtain I/Q data, and described I/Q data are sent to described DSP processing module;
Described DSP processing module receives the I/Q data that FPGA module sends, and the I/Q data received is carried out encoding and adding synchronized timestamp;
Described CPCI interface is used for host computer multipath synchronous data being transferred to its exterior, utilizes the synchronized timestamp of multichannel data to extract the data of needs, carry out the position coordinates that phase difference analysis obtains mobile phone by host computer.
Preferably, the clock signal of the multichannel homology of described synchronised clock module output is specially the clock signal of 6 tunnel homologies.
Preferably, described synchronised clock module specifically comprises crystal oscillator and clock distribution chip;
Described crystal oscillator is used for providing clock signal, and drives clock distribution chip operation;
Described clock distribution chip is used for the clock signal according to the driver output multichannel homology of crystal oscillator, and the clock signal of described multichannel homology is distributed to described FPGA module and A/D module respectively.
Preferably, described FPGA module comprises 2 FPGA disposable plates;
Wherein, carry out synchronously especially by synchronizing signal between described 2 FPGA disposable plates.
Preferably, the described multichannel intermediate-freuqncy signal that is converted to by the multichannel carrier signal received is specially the 8 tunnel carrier signals received is converted to 8 tunnel intermediate-freuqncy signals.
Preferably, described A/D module specifically comprises 4 A/D chip, and described each A/D chip gathers 2 tunnel intermediate-freuqncy signals.
Preferably, described numeral of data after synchronized sampling being done descends synchronous frequency conversion process to be specially:
Data after sampling are sent to described FPGA module, and described FPGA module utilizes IP stone to realize synchronous frequency conversion process under the numeral of multiple signals.
A kind of multiple signals synchronization processing method, the method is applied in mobile phone phase difference location, comprising:
Described multichannel homology clock signal is also distributed by output multi-channel homology clock signal;
The multichannel carrier signal received is converted to multichannel intermediate-freuqncy signal;
According to homology clock signal, synchronized sampling and preliminary treatment are carried out to described multichannel intermediate-freuqncy signal, the data after synchronized sampling are done the lower synchronous frequency conversion process of numeral and obtain I/Q data;
Described I/Q data are carried out encoding and adding synchronized timestamp;
Utilize the synchronized timestamp of multichannel data to extract the data of needs, carry out the position coordinates that phase difference analysis obtains mobile phone.
Preferably, described multichannel homology clock signal is specially the clock signal of 6 tunnel homologies.
Preferably, the described multichannel intermediate-freuqncy signal that is converted to by the multichannel carrier signal received is specially the 8 tunnel carrier signals received is converted to 8 tunnel intermediate-freuqncy signals.
Known via above-mentioned technical scheme, compared with prior art, the invention discloses a kind of multiple signals System of Synchronous Processing and method, A/D module and FPGA module can be distributed to respectively as homologous signal by multi-path synchronous clock signal synchronised clock module exported, thus achieve A/D module and synchronized sampling is carried out to the multichannel intermediate-freuqncy signal that the multichannel carrier signal that external receiver receives converts to and FPGA module carries out synchronous frequency conversion process under numeral to multichannel intermediate-freuqncy signal, data after synchronous frequency conversion process carry out encoding and adding synchronized timestamp by DSP processing module, by CPCI interface, multipath synchronous data is transferred to the host computer of its exterior again, the synchronized timestamp of multichannel data is utilized to extract the data of needs by host computer, carry out the position coordinates that phase difference analysis obtains mobile phone.The present invention compared with prior art, ensure that the synchronous acquisition to multichannel carrier signal, achieves the synchronous frequency conversion process of multichannel carrier signal under numeral, thus reaches the object of mobile phone being carried out to phase difference location.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only embodiments of the invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to the accompanying drawing provided.
The block diagram of Fig. 1 a kind of multiple signals System of Synchronous Processing disclosed in the embodiment of the present invention;
The schematic diagram of Fig. 2 synchronized sampling disclosed in the embodiment of the present invention;
Fig. 3 monolithic FPGA disposable plates disclosed in the embodiment of the present invention realizes the schematic diagram of the lower synchronous frequency conversion of numeral;
Fig. 4 is the controller drawing of the disclosed synchronous process of the embodiment of the present invention;
The flow chart of Fig. 5 a kind of multiple signals synchronization processing method disclosed in the embodiment of the present invention;
Embodiment
Embodiment one
In order to realize the synchronous acquisition to multichannel carrier signal, by multichannel carrier signal synchronous frequency conversion under numeral, thus reach and can carry out phase difference location to mobile phone, the present embodiment is following content openly, the block diagram of Fig. 1 a kind of multiple signals System of Synchronous Processing disclosed in the embodiment of the present invention, with reference to shown in Fig. 1, described in the multiple signals System of Synchronous Processing be applied in mobile phone phase difference navigation system comprise: synchronised clock module 101, FPGA module 102, DSP processing module 103, A/D module 104, external digital receiver 105 and CPCI interface 106;
The clock signal of multichannel homology for the clock signal of output multi-channel homology, and is distributed to FPGA module 102 and A/D module 104 by synchronised clock module 101 respectively;
Concrete, synchronised clock module 101 specifically comprises crystal oscillator and clock distribution chip two parts, and crystal oscillator is 52.1MHz crystal oscillator OSC, and clock distribution chip is specially precision clock and divides distribution chip AD9510, FPGA module specifically comprises two panels FPGA disposable plates, and A/D module specifically comprises 4 A/D chip.Synchronised clock module 101 is driven by the crystal oscillator OSC of 52.1MHz, and the clock signal of dividing distribution chip AD9510 to export 6 tunnel homologies by precision clock is sent to 4 A/D chip and two panels FPGA disposable plates.
External digital receiver 105 is for introducing multichannel intermediate-freuqncy signal to A/D module 104;
Concrete, the carrier signal of 8 passages of ch1 to ch8 introduced by external digital receiver 105 with RF cable, and carrier signal is converted to high-frequency signal and is sent to A/D module 104, each A/D chip in A/D module 104 is responsible for collection 2 tunnel intermediate-freuqncy signal respectively, simultaneously, external digital receiver 105 also has serial communication passage with A/D module 104, for carrying out the transmission of signal.
FPGA module 102 is for the clock signal according to homology, control A/D module 104 pairs of multichannel intermediate-freuqncy signals and carry out synchronized sampling, data after synchronized sampling are done the lower synchronous frequency conversion process of numeral and obtain I/Q (In-phase/Quadrature inphase quadrature) data, and I/Q data are sent to DSP processing module 103;
Concrete, the two panels FPGA disposable plates in FPGA module 102, directly by synchronous protocol, notifies that the other side samples and the operating state of Digital Down Convert, ensures the synchronous of process further.Every sheet FPGA disposable plates is responsible for the synchronized sampling that control two A/D chip carry out 4 tunnel intermediate-freuqncy signals respectively, and the data after sampling are sent in FPGA module, utilize IP stone to realize synchronous frequency conversion under the numeral of multiple signals, the I/Q data obtained after synchronous frequency conversion are sent to DSP processing module 103;
Undertaken synchronously by synchronizing signal between two panels FPGA disposable plates in the present invention, carry out synchronized sampling and Digital Down Convert to 8 tunnel carrier signals of external receiver, the maximum sample rate of single channel is 80Mbps.
The I/Q data that DSP processing module 103 sends for receiving FPGA module 102, and the I/Q data received are carried out encoding and adding synchronized timestamp;
Dsp processor in the present invention is used for coding and the synchronized timestamp mark of I/Q data, expand the work of RS232 Interface Controller external receiver, the IO of 32bit is used to control the work of the aerial array of external receiver, put on display the storage Flash of startup NORFLASH and 8MB of 2MB simultaneously, and the DDRSDRM of 128M.
CPCI interface 106, for multipath synchronous data being transferred to the host computer of its exterior, utilizes the synchronized timestamp of multichannel data to extract the data of needs by host computer, carries out the position coordinates that phase difference analysis obtains mobile phone.
What the dsp processor used in the present invention adopted is high performance fixed-point DSP processor, its clock frequency can reach 1GHz, highest point reason ability is 4800MIPS, it has 2 extended menory interfaces (EMIF), one is 64bit(EMIFA), one is 16bit(EMIFA), can with the seamless link of asynchronous (SRAM, EPROM)/synchronous memories (SDRAM, SBSRAM, ZBTSRAM, FIFO), maximum addressable scope is 1280MB; There is the direct memory access controller (EDMA) of expansion, 64 independently DMA passages can be provided, in sheet, also have the universal input/output interface (GPIO) of 16 pins.
AD sampling module in the present invention adopts 4 chip AD9251, supports 80Msps sampling, 14bit, supporting signal input amplitude 0-1.5V, AC coupled.
Clock module in the present invention uses AD9510 to be that a precision clock divides distribution chip, and it has the differential clocks input of 2 road 1.6GHz, 8 road clocks export and PLL core on sheet.Wherein, comprise the independently 1.2GHzLVPECL clock output of 4 tunnels, other 4 tunnels independently clock export and can be arranged to LVDS or CMOS: when being arranged to LVDS output, frequency can reach 800MHz; When being arranged to CMOS output, frequency can reach 250MHz.Meanwhile, this chip also controls the phase delay between output clock by SPI serial programming, and shake and phase noise extremely low.
By 2 EMIF interface: EMIFA and EMIFB of DSP module in the present invention, the interface of expansion comprises memory interface, sdram interface, control interface.EMIFA interface-clock-frequency can reach 100MHz, and EMIFA interface chip selects 0 for control SDRAM, size 128MByte, data bit width 32bit; Sheet selects 1 for the read-write of FPGA1, size 16Byte, data bit width 32bit; Sheet selects 2 for the read-write of FPGA2, size 16Byte, data bit width 32bit.The clock frequency of EMIFB interface can reach 133MHz, and sheet selects 0 for storing the read-write of NORFLASH, size 8MByte, data bit width 16bit; Sheet selects 1 for starting the read-write of NORFLASH, size 2MByte, data bit width 8bit; Sheet selects 2 for the read-write of serial ports 0, size 16Byte, data bit width 8bit; Sheet selects 3 for the read-write of serial ports 1, size 16Byte, data bit width 8bit.
Dsp processor in the present invention is used for coding and the synchronized timestamp mark of I/Q data, expands RS232 Interface Controller operation of receiver, uses the IO of 32bit to control the work of 8 road aerial arrays of external receiver.
The present invention uses two panels FPGA to gather 4 road signals respectively, overcomes when carrying out multiple signals process by monolithic FPGA, when port number too much causes the isometric layout of system PCB signal puzzled, and the problem that antijamming capability is not strong.
Receiver of the present invention can collect by antenna array the carrier signal that 8 road handset emissions go out.
As shown in Figure 2, the schematic diagram of synchronized sampling disclosed in the embodiment of the present invention, external clock reference carries out precision clock distribution by clock module AD9510 chip, then exports 6 road clock sync signals to 4 A/D chip and two panels FPGA disposable plates.Because 6 road synchronizing clock signals are homologous signal, be that the Digital Down Convert process that the synchronized sampling of 8 road signals of 4 A/D chip and two panels FPGA carry out 8 road signals provides the foundation.Two panels FPGA, directly by synchronous protocol, notifies that the other side samples and the operating state of Digital Down Convert, ensures synchronous further.
The principle that monolithic FPGA disposable plates realizes the lower synchronous frequency conversion of numeral is shown in Figure 3, and Fig. 3 monolithic FPGA disposable plates disclosed in the embodiment of the present invention realizes the schematic diagram of the lower synchronous frequency conversion of numeral, and the working method of multiple FPGA is also like this.Adopt the conversion system carrying out multiple signals based on the Hardware I P core of FPGA, owing to being adopt hardware to carry out synchronous frequency conversion to multiple signals.The problem of the asynchronous and poor real that software frequency conversion brings can be overcome.The data that ADC samples form I/Q data after successively carrying out mixing, cic filter, CIFR filter, PFIR filter, deliver to DSP and carry out subsequent treatment after then I/Q data being packed.
What the dsp processor used in the present invention was controlled by FPGA module is provided with outward: the A/D chip of 4 totally 8 passages is arranged, the setting of clock distribution chip, the GPIO (32bit output) that FPGA outside connects and GPIO(2bit input), the control line of 2 passage serial port chip, the page control line of NORFLASH, to the control of FPGA internal register.What be connected with DSP in FPGA inside is the communication of output between FIFO, FPGA and DSP, the sheet of use EMIFA interface select 1 and sheet select 2.Through the signed number that the output data of FPGA Digital Down Convert are I/Q data, each 16bit, I/Q is one group, and the data of composition 32bit are so that DSP access altogether; Every sheet FPGA controls 4 passages, and FPGA only has inside 1 FIFO, the data polling of 8 passages stored in FIFO so that DSP reads.
Fig. 4 is the controller drawing of the disclosed synchronous process of the embodiment of the present invention, as shown in Figure 4, after dsp processor is powered, first carry out system initialization, arranging each configuration register makes each functional module of DSP run by designing requirement, and main configuration pin is multiplexing, PLL, PSC and EMIF.FPGA starts simultaneously and starts control AD9251 and starts image data, the Hardware I P core that carrier signal enters FPGA through AD sampling carries out Digital Down Convert, baseband I after frequency conversion/Q data carry out the fifo buffer of FPGA, when the data volume in FIFO reaches preseting length, export interrupt signal.Because interrupt signal line is connected with the general GPIO pin of DSP for this reason, the EDMA3 controller of DSP inside can detect that this GPIO interrupts affairs, and produce a transmission request, according to the parameter set, data are transferred to the SDRAM memory of DSP module from the output FIFO in FPGA.After completing this EDMA and transmitting request, trigger an EDMA interrupt, in interrupt service routine, detect data length in SDRAM.Synchronous protocol is used to notify the other side's operating state between two panels FPGA.Finally, when the data length of sdram memory storage reaches the length of setting, triggering coding and synchronized timestamp function carry out synchronizing signal process, and the signal after process can be read by the synchronous CPCI interface of host computer.
Embodiment two
On the basis of embodiment one, the embodiment of the present application additionally provides a kind of multiple signals synchronization processing method, as shown in Figure 5, is the schematic flow sheet of a kind of multiple signals synchronization processing method that the embodiment of the present application provides.
The method is applied in mobile phone phase difference location, comprising:
Step S1: export and distribute multichannel homology clock signal.
Multichannel homologous signal is specially 6 road homologous signal, exports rear and distributes, as synchronizing signal instruction to the synchronous acquisition of carrier signal and process.
Step S2: the multichannel carrier signal received is converted to multichannel intermediate-freuqncy signal;
Be specially and the 8 tunnel carrier signals received are converted to 8 tunnel intermediate-freuqncy signals.
Step S3: carry out synchronized sampling to multichannel intermediate-freuqncy signal according to homology clock signal, does the lower synchronous frequency conversion process of numeral and obtains I/Q data;
Step S4: I/Q data are carried out encoding and adding synchronized timestamp;
Step S5: utilize the synchronized timestamp of multichannel data to extract the data of needs, carries out the position coordinates that phase difference analysis obtains mobile phone.
From above technical scheme, this multiple signals synchronization processing method that the embodiment of the present application provides, A/D module and FPGA module can be distributed to respectively as homologous signal by multi-path synchronous clock signal synchronised clock module exported, thus achieve A/D module and synchronized sampling is carried out to the multichannel intermediate-freuqncy signal that the multichannel carrier signal that external receiver receives converts to and FPGA module carries out synchronous frequency conversion process under numeral to multichannel intermediate-freuqncy signal, data after synchronous frequency conversion process carry out encoding and adding synchronized timestamp by DSP processing module, by CPCI interface, multipath synchronous data is transferred to the host computer of its exterior again, the synchronized timestamp of multichannel data is utilized to extract the data of needs by host computer, carry out the position coordinates that phase difference analysis obtains mobile phone.The present invention compared with prior art, ensure that the synchronous acquisition to multichannel carrier signal, achieves the synchronous frequency conversion process of multichannel carrier signal under numeral, thus reaches the object of mobile phone being carried out to phase difference location.
Also it should be noted that, in this article, the such as relational terms of first and second grades and so on is only used for an entity or operation to separate with another entity or operating space, and not necessarily requires or imply the relation that there is any this reality between these entities or operation or sequentially.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thus make to comprise the process of a series of key element, method, article or equipment and not only comprise those key elements, but also comprise other key elements clearly do not listed, or also comprise by the intrinsic key element of this process, method, article or equipment.When not more restrictions, the key element limited by statement " comprising ... ", and be not precluded within process, method, article or the equipment comprising described key element and also there is other identical element.
The software module that the method described in conjunction with embodiment disclosed herein or the step of algorithm can directly use hardware, processor to perform, or the combination of the two is implemented.Software module can be placed in the storage medium of other form any known in random asccess memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or technical field.
To the above-mentioned explanation of the disclosed embodiments, professional and technical personnel in the field are realized or uses the present invention.To be apparent for those skilled in the art to the multiple amendment of these embodiments, General Principle as defined herein can without departing from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention can not be restricted to these embodiments shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (9)
1. a multiple signals System of Synchronous Processing, is characterized in that, this system is applied in mobile phone phase difference navigation system, comprising: synchronised clock module, FPGA module, DSP processing module, A/D module, external digital receiver and CPCI interface;
Described synchronised clock module is used for the clock signal of output multi-channel homology, and the clock signal of described multichannel homology is distributed to described FPGA module and A/D module respectively;
Described external digital receiver is used for that the multichannel carrier signal received is converted to multichannel intermediate-freuqncy signal and is sent to described A/D module;
Described FPGA module is used for the clock signal according to described homology, control described A/D module and synchronized sampling is carried out to described multichannel intermediate-freuqncy signal, data after synchronized sampling are done the lower synchronous frequency conversion process of numeral and obtain I/Q data, and described I/Q data are sent to described DSP processing module, under described numeral, synchronous frequency conversion is treated to the data after to described synchronized sampling and successively forms I/Q data through mixing, cic filter, CIFR filter and PFIR filter process;
The I/Q data that described DSP processing module sends for receiving FPGA module, and the I/Q data received are carried out encoding and adding synchronized timestamp;
Described CPCI interface is used for host computer multipath synchronous data being transferred to its exterior, utilizes the synchronized timestamp of multichannel data to extract the data of needs, carry out the position coordinates that phase difference analysis obtains mobile phone by host computer;
Wherein, described FPGA module comprises 2 FPGA disposable plates, carries out synchronously between described 2 FPGA disposable plates especially by the clock signal of described multichannel homology.
2. system according to claim 1, is characterized in that, the clock signal of the multichannel homology that described synchronised clock module exports is specially the clock signal of 6 tunnel homologies.
3. system according to claim 1, described synchronised clock module specifically comprises crystal oscillator and clock distribution chip;
Described crystal oscillator is used for providing clock signal, and drives clock distribution chip operation;
Described clock distribution chip is used for the clock signal according to the driver output multichannel homology of crystal oscillator, and the clock signal of described multichannel homology is distributed to described FPGA module and A/D module respectively.
4. system according to claim 1, is characterized in that, the described multichannel intermediate-freuqncy signal that is converted to by the multichannel carrier signal received is specially the 8 tunnel carrier signals received are converted to 8 tunnel intermediate-freuqncy signals.
5. system according to claim 4, is characterized in that, described A/D module specifically comprises 4 A/D chip, and described each A/D chip gathers 2 tunnel intermediate-freuqncy signals.
6. system according to claim 1, is characterized in that, described numeral of data after synchronized sampling being done descends synchronous frequency conversion process to be specially:
Data after sampling are sent to described FPGA module, and described FPGA module utilizes IP stone to realize synchronous frequency conversion process under the numeral of multiple signals.
7. a multiple signals synchronization processing method, is characterized in that, the method is applied in mobile phone phase difference location, comprising:
Described multichannel homology clock signal is also distributed by output multi-channel homology clock signal;
The multichannel carrier signal received is converted to multichannel intermediate-freuqncy signal;
According to described homology clock signal, synchronized sampling is carried out to described multichannel intermediate-freuqncy signal, data after synchronized sampling are done the lower synchronous frequency conversion process of numeral and obtain I/Q data, under described numeral, synchronous frequency conversion is treated to the data after to described synchronized sampling and successively forms I/Q data through mixing, cic filter, CIFR filter and PFIR filter process;
Described I/Q data are carried out encoding and adding synchronized timestamp;
Utilize the synchronized timestamp of multichannel data to extract the data of needs, carry out the position coordinates that phase difference analysis obtains mobile phone;
Wherein, FPGA module comprises 2 FPGA disposable plates, carries out synchronously between described 2 FPGA disposable plates especially by described multichannel homology clock signal.
8. method according to claim 7, is characterized in that, described multichannel homology clock signal is specially the clock signal of 6 tunnel homologies.
9. method according to claim 7, is characterized in that, the described multichannel intermediate-freuqncy signal that is converted to by the multichannel carrier signal received is specially the 8 tunnel carrier signals received are converted to 8 tunnel intermediate-freuqncy signals.
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| CN115664628A (en) * | 2022-10-24 | 2023-01-31 | 中国电子科技集团公司第二十九研究所 | Multi-channel digital synchronous frequency conversion method and system |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6301311B1 (en) * | 1999-02-10 | 2001-10-09 | Anritsu Company | Non-coherent, non-data-aided pseudo-noise synchronization and carrier synchronization for QPSK or OQPSK modulated CDMA system |
| CN101587498A (en) * | 2009-06-24 | 2009-11-25 | 北京理工大学 | Dual-mode signal acquiring board |
| CN102185629A (en) * | 2011-04-28 | 2011-09-14 | 上海交通大学 | Accurate synchronized device of BOC (binary offset carrier) signals and synchronized method thereof |
| JP2012165208A (en) * | 2011-02-07 | 2012-08-30 | Nec Engineering Ltd | Spread spectrum signal synchronization receiver |
| CN203164412U (en) * | 2013-04-01 | 2013-08-28 | 武汉中软通科技有限公司 | Direction positioning system based on multi-antenna synchronous acquisition of wireless signals |
-
2013
- 2013-11-18 CN CN201310577430.5A patent/CN103560805B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6301311B1 (en) * | 1999-02-10 | 2001-10-09 | Anritsu Company | Non-coherent, non-data-aided pseudo-noise synchronization and carrier synchronization for QPSK or OQPSK modulated CDMA system |
| CN101587498A (en) * | 2009-06-24 | 2009-11-25 | 北京理工大学 | Dual-mode signal acquiring board |
| JP2012165208A (en) * | 2011-02-07 | 2012-08-30 | Nec Engineering Ltd | Spread spectrum signal synchronization receiver |
| CN102185629A (en) * | 2011-04-28 | 2011-09-14 | 上海交通大学 | Accurate synchronized device of BOC (binary offset carrier) signals and synchronized method thereof |
| CN203164412U (en) * | 2013-04-01 | 2013-08-28 | 武汉中软通科技有限公司 | Direction positioning system based on multi-antenna synchronous acquisition of wireless signals |
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