CN202033737U - FPGA-based high-speed data acquisition system - Google Patents
FPGA-based high-speed data acquisition system Download PDFInfo
- Publication number
- CN202033737U CN202033737U CN 201020699992 CN201020699992U CN202033737U CN 202033737 U CN202033737 U CN 202033737U CN 201020699992 CN201020699992 CN 201020699992 CN 201020699992 U CN201020699992 U CN 201020699992U CN 202033737 U CN202033737 U CN 202033737U
- Authority
- CN
- China
- Prior art keywords
- fpga
- module
- sampling
- speed
- converter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
The utility model discloses a FPGA-based high-speed data acquisition system, which comprises a differential amplification unit for receiving analog signals, an A/D conversion unit connected with the differential amplification unit, an FPGA processing unit connected with the A/D conversion unit and a microprocessor connected with the FPGA processing unit. The microprocessor is connected with a host computer via a communication interface. The FPGA-based high-speed data acquisition system is high in sampling speed, high in precision, large in storage capacity and fast in uploading speed. The parallel alternately real-time sampling is adopted as the sampling mode for the system. One signal is parallel alternately sampled by two A/D converters with the sampling speed thereof to be 125 MSPS respectively, so that the sampling speed is 250 MSPS. The sampling precision can reach 12 bits and the acquisition point number is 1-25 K. The system has a hardware accumulation function and the accumulation number is 1-250 K. The bandwidth is 200 MHz. A USB 2.0 full-speed communication can also realized by the system and the signal input range is 2 Vp-p. The system can be widely applied to the field of multipath signal acquisition with higher requirements for the speed, accuracy and storage capacity of data acquisition.
Description
Technical field
The utility model relates to a kind of data acquisition system (DAS) of 250MSPS sampling rate, especially relates to a kind of high-speed data acquistion system based on FPGA.
Background technology
Traditional data acquisition system (DAS) adopts single-chip microcomputer or DSP as main control module usually, by the work of its control ADC, storer and other peripheral circuits.In actual engineering now, the performance demands such as speed, precision, memory space and environmental suitability of data being gathered along with system are more and more higher, traditional data acquisition system (DAS) can not satisfy the needs of practical application, and the drawback of existence is also more and more obvious.
The patent No. is that the utility model patent of ZL 200820095724.9 discloses a kind of multi-path data acquiring system, comprise selector switch, amplifier, analog-to-digital conversion module and central processing unit, described amplifier is connected between selector switch and the analog-to-digital conversion module, and described central processing unit links to each other with amplifier; The multichannel output signal of described selector switch receiving sensor and under the control of central processing unit timesharing multiple signals delivered to amplifier amplify, the multiple signals after described amplifier will amplify are delivered to analog-to-digital conversion module and are carried out analog to digital conversion.There is following major defect in the multi-path data acquiring system that possesses said structure:
1) system can not realize parallel alternately real-time sampling, and sampling rate is low;
2) system does not have the hardware accumulation function, and signal to noise ratio (S/N ratio) is low, sampling precision is low, system stability is poor;
3) data upload speed is slow.
Along with FPGA (Field Programmable Gate Array, field programmable gate array) appearance and development of technologies thereof, because of its clock frequency height, little, the whole steering logic of internal delay time superior characteristics such as finish by hardware, use novel fpga chip to carry out design of Data Acquisition System, become a kind of trend.
Summary of the invention
The purpose of this utility model overcomes deficiency of the prior art exactly, provides a kind of sampling rate height, sampling precision height, data upload speed is fast, system stability good, can realize the high-speed data acquistion system based on FPGA that multidiameter delay is gathered in real time.
For solving the problems of the prior art, the utility model has adopted following technical scheme: comprise the difference amplifying unit that receives simulating signal, the A/D converting unit that is connected with described difference amplifying unit, the FPGA processing unit that is connected with described A/D converting unit, with the microprocessor that described FPGA processing unit is connected, described microprocessor is connected with host computer by communication interface.
Further, described difference amplifying unit comprises two differential amplifiers at least, is respectively first differential amplifier and second differential amplifier.
Further, described A/D converting unit comprises two A/D converters at least, is respectively first A/D converter that is connected with described first differential amplifier and second A/D converter that is connected with described second differential amplifier.
Further, described FPGA processing unit comprise at least to described first A/D converter provide sampled clock signal the first sampling clock module, to provide the second sampling clock module of sampled clock signal, the clock phase difference output of described first sampling clock module and the described second sampling clock module to described second A/D converter be 180 degree.
Further, described FPGA processing unit also comprises the sampled data receiver module that is connected with described A/D converting unit, the accumulation process assembly that is connected with described sampled data receiver module, the dual port RAM assembly that is connected with described accumulation process assembly, also comprise the command reception and the processing module that are connected with described microprocessor, parameter configuration module and the data upload module that is connected with processing module with described command reception respectively, described accumulation process assembly also respectively with described command reception and processing module, described parameter configuration module is connected, described dual port RAM assembly, described data upload module is connected successively with described microprocessor.
Further, described FPGA processing unit also comprises the data conversion storage module, the external SRAM of described data conversion storage module and be arranged on described dual port RAM assembly and described data upload module between, described data conversion storage module also is connected with processing module with described command reception.
Further, described FPGA processing unit also comprises respectively selects module and internal trigger signal generator module with the trigger pip that described command reception is connected with processing module, described trigger pip selects module to be connected with the outer triggering signal generation device with described internal trigger signal generator module respectively, and described trigger pip selects module also to be connected with described accumulation process assembly.
Further, described sampled data receiver module comprise at least the sampled data that is used for receiving described first A/D converter the first sampled data receiver module, be used for receiving the second sampled data receiver module of the sampled data of described second A/D converter.
Further, described accumulation process assembly comprises first accumulation process module that is connected with the described first sampled data receiver module and the second accumulation process module that is connected with the described second sampled data receiver module at least.
Further, described dual port RAM assembly comprises first dual port RAM that is connected with the described first accumulation process module and second dual port RAM that is connected with the described second accumulation process module at least.
Further, the sampling rate of the sampling rate of described first A/D converter and described second A/D converter is 125MSPS.
Further, described communication interface is a USB interface.
The utility model based on the advantage of the high-speed data acquistion system of FPGA is:
1) system is provided with the FPGA processing unit, because of its clock frequency height, internal delay time are little, has improved the speed and the precision of data processing greatly;
2) two parallel alternating sampling one road signals of A/D converter that sampling rate is 125MSPS are realized the 250MSPS sampling rate;
3) in the FPGA processing unit accumulation process assembly is set, can improves signal to noise ratio (S/N ratio), the elimination noise of system;
4) the external SRAM of FPGA processing unit, in establish the data conversion storage module, not only enlarged system memory capacity, improved the ease for use of system, and do not influence system to real-time signal acquisition work when making system carry out data upload;
5) trigger pip is set in the FPGA processing unit and selects module, can support inside and outside synchronous triggering;
6) can increase the dirigibility of system design, and make system have good expandability by upper layer software (applications) design instruction;
7) system adopts USB interface to upload data, makes system have higher last transfer rate than traditional serial ports, and supports hot plug, the convenient use.
In a word, the utility model has the sampling rate height based on the high-speed data acquistion system of FPGA, the precision height, memory space is big, characteristics such as uploading speed is fast, sample mode is parallel alternately real-time sampling, utilize two sampling rates to be parallel alternating sampling one road signal of the A/D converter of 125MSPS, realize the 250MSPS sampling rate, sampling precision can reach 12bits, it is 1～25K that collection is counted, has the hardware accumulation function, accumulative frequency is 1～250K, and bandwidth 200MHz supports USB2.0 communication at full speed, signal input range 2Vp-p can be widely used in the speed that data are gathered, precision, the multiplexed signal sampling field that memory space is had relatively high expectations.
Description of drawings
Fig. 1 is the structural representation block diagram of the utility model based on the high-speed data acquistion system embodiment one of FPGA.
Fig. 2 is the structural representation block diagram of FPGA processing unit among Fig. 1.
Fig. 3 is the structural representation block diagram of the utility model based on the high-speed data acquistion system embodiment two of FPGA.
Fig. 4 is the structural representation block diagram of FPGA processing unit among Fig. 3.
Fig. 5 is the workflow diagram of the utility model based on the high-speed data acquistion system embodiment two of FPGA.
Embodiment
The utility model is described in more detail below in conjunction with accompanying drawing.
Fig. 1 is the structural representation block diagram of the utility model based on the high-speed data acquistion system embodiment one of FPGA.
As shown in Figure 1, the utility model comprises the difference amplifying unit 1, A/D converting unit 2, FPGA processing unit 3 and the microprocessor 4 that are connected successively based on the high-speed data acquistion system of FPGA, and microprocessor 4 is connected with host computer 6 by USB interface 5.
As shown in Figure 1, difference amplifying unit 1 comprises 4 identical differential amplifiers, is respectively first differential amplifier 11, second differential amplifier 12, the 3rd differential amplifier 13 and the 4th differential amplifier 14; A/D converting unit 2 comprises that 4 sampling rates are the A/D converter of 125MSPS, is respectively first A/D converter 21 that is connected with first differential amplifier 12, second A/D converter 22 that is connected with second differential amplifier 12, the 3rd A/D converter 23 that is connected with the 3rd differential amplifier 13 and the 4th A/D converter 24 that is connected with the 4th differential amplifier 14.
In the present embodiment, difference amplifying unit 1 and A/D converting unit 2 are formed the simulating signal of four tunnel signal gathering unit acquired signal passages one and signalling channel two, specifically be assigned as, first differential amplifier 11 and first A/D converter 21 are formed first via signal gathering unit; Second differential amplifier 12 and second A/D converter 22 are formed the second tunnel signal gathering unit; The 3rd differential amplifier 13 and the 3rd A/D converter 23 are formed the Third Road signal gathering unit; The 4th differential amplifier 14 and the 4th A/D converter 24 are formed the four tunnel signal gathering unit; Wherein, the simulating signal of the first via signal gathering unit and the second tunnel signal gathering unit acquired signal passage one, the simulating signal of Third Road signal gathering unit and the four tunnel signal gathering unit acquired signal passage two.
In the present embodiment, difference amplifying unit 1 is used for the single-ended simulating signal of received signal passage one and signalling channel two, and become differential analog signal to output to A/D converting unit 2 the single-ended analog signal conversion, and can improve the signal to noise ratio (S/N ratio) of system, strengthen inhibition ability to common-mode signal.
In the present embodiment, A/D converting unit 2 changes into the digital signal that FPGA processing unit 3 is discerned with the differential analog signal that receives, and digital signal sent to FPGA processing unit 3 with 12 bit parallels, cmos compatible mode, simultaneously, A/D converting unit 2 sends the sampled data clock signal to FPGA processing unit 3.
Fig. 2 is that the utility model among Fig. 1 is based on the structural representation block diagram of FPGA processing unit 3 among the high-speed data acquistion system embodiment one of FPGA.
As shown in Figure 2, be provided with in the FPGA processing unit 3 to first A/D converter 21 provide sampled clock signal the first sampling clock module 311, provide the second sampling clock module 312 of sampled clock signal to second A/D converter 22, the 3rd sampling clock module 313 of sampled clock signal is provided for the 3rd A/D converter 23, the 4th sampling clock module 314 of sampled clock signal is provided to the 4th A/D converter 24.
In the present embodiment, the clock phase difference output of the first sampling clock module 311 and the second sampling clock module 312 is 180 degree, therefore, first A/D converter 21 and second A/D converter 22 are under the effect of the differential clocks of the first sampling clock module 311 and the second sampling clock module 312, the differential analog signal of parallel alternating sampling first differential amplifier 11 or 12 outputs of second differential amplifier, the realization system is to the 250MSPS sampling rate of signalling channel one; Equally, the clock phase difference output of the 3rd sampling clock module 313 and the 4th sampling clock module 314 also is 180 degree, therefore, the 3rd A/D converter 23 and the 4th A/D converter 24 are under the effect of the differential clocks of the 3rd sampling clock module 313 and the 4th sampling clock module 314, the differential analog signal of parallel alternating sampling the 3rd differential amplifier 13 or 14 outputs of the 4th differential amplifier, the realization system is to the 250MSPS sampling rate of signalling channel two.
As shown in Figure 2, also be provided with sampled data receiver module 32, accumulation process assembly 33, dual port RAM assembly 34, command reception and processing module 35, parameter configuration module 36 and data upload module 37 in the FPGA processing unit 3, also be provided with internal trigger signal generator module 38 and trigger pip and select module 39.
As shown in Figure 2, sampled data receiver module 32 comprises: be used for receiving the sampled data of first A/D converter 21 the first sampled data receiver module 321, be used for receiving the second sampled data connection module 322 of the sampled data of second A/D converter 22, be used for receiving the sampled data of the 3rd A/D converter 23 the 3rd sampled data receiver module 323, be used for receiving the 4th sampled data connection module 324 of the sampled data of the 4th A/D converter 24.
As shown in Figure 2, accumulation process assembly 33 comprises: the sampled data that the sampled data that the sampled data that the sampled data that the first sampled data receiver module 321 is received carries out the first accumulation process module 331 of accumulation process, receive the second sampled data receiver module 322 carries out the second accumulation process module 332 of accumulation process, receive the 3rd sampled data receiver module 323 carries out the 3rd accumulation process module 333 of accumulation process, receive the 4th sampled data receiver module 324 is carried out the 4th accumulation process module 334 of accumulation process.
As shown in Figure 2, dual port RAM assembly 34 comprises: first dual port RAM 341 is used for storing the result data that adds up in real time of the first accumulation process module 331; Second dual port RAM 342 is used for storing the result data that adds up in real time of the second accumulation process module 332; The 3rd dual port RAM 343 is used for storing the result data that adds up in real time of the 3rd accumulation process module 333; The 4th dual port RAM 344 is used for storing the result data that adds up in real time of the 4th accumulation process module 334.
In the present embodiment, command reception is connected with microprocessor 4 with processing module 35, be used for receiving the command information that host computer 6 that microprocessor 4 resolves is sent, send it to parameter configuration module 36 and/or data upload module 37 and/or accumulation process assembly 33 and/or internal trigger signal generator module 38 and/or trigger pip according to command content simultaneously and select module 39.
In the present embodiment, parameter configuration module 36 is carried out for example parameter configuration such as accumulative frequency, sampling number according to the parameter configuration instruction.
In the present embodiment, data upload module 37 uploads to host computer 6 with the data that are stored in the dual port RAM assembly 34 by microprocessor 4 and USB interface 5 according to the data upload instruction.
In the present embodiment, internal trigger signal generator module 38 produces frequency according to the internal trigger signal, sends the internal trigger signal and selects module 39 to trigger pip.
In the present embodiment, trigger pip selects module 39 according to the trigger pip selection instruction, the internal trigger signal that selective reception is produced by internal trigger signal generator module 38 or receive the outer triggering signal that is sent by the outer triggering signal generation device.
In the present embodiment, microprocessor 4 receives the also steering order of analyzing and processing host computer 6, and instruction is sent to the command reception and the processing module 35 of FPGA processing unit 3, receive the data that the data upload module 37 of FPGA processing unit 3 is uploaded simultaneously, and data are uploaded to host computer 6 by USB interface 5.
In the present embodiment, USB interface 5 can be uploaded sampled data at full speed as the communication interface of system and host computer 6.
In the present embodiment, host computer 6 sends the controlling of sampling instruction and receives sampled data.
Fig. 3 is the structural representation block diagram of the utility model based on the high-speed data acquistion system embodiment two of FPGA.Except following description, other parts that the system of Fig. 3 and Fig. 1 forms are identical.
As shown in Figure 3, the utility model also comprises SRAM7 based on the high-speed data acquistion system of FPGA, and SRAM7 is external memory storage and is connected with FPGA processing unit 3.
Fig. 4 is that the utility model among Fig. 3 is based on the structural representation block diagram of FPGA processing unit 3 among the high-speed data acquistion system embodiment two of FPGA.Except following description, other parts of the composition of Fig. 4 and Fig. 2 are identical.
As shown in Figure 4, also be provided with data conversion storage module 310 in the FPGA processing unit 3, data conversion storage module 310 is connected with processing module 35 with SRAM7 and command reception with dual port RAM assembly 34 respectively, according to instruction, in external memory storage SRAM7, data upload module 37 uploads to host computer 6 with the data among the SRAM7 by microprocessor 4 and USB interface 5 to data conversion storage module 310 again with the sampling accumulation result data conversion storage of dual port RAM assembly 34 storage.
In the present embodiment, the setting of SRAM7 and data conversion storage module 310, not only enlarged system memory capacity, improved the ease for use of system, and do not influence system to real-time signal acquisition work when making system carry out data upload.
Fig. 5 is the workflow diagram of the utility model based on the high-speed data acquistion system embodiment two of FPGA.
Below by Fig. 5 the utility model is carried out detailed description based on the course of work of the high-speed data acquistion system of FPGA.
Step S101, power-up initializing.
Step S102, system set up with host computer 6 and communicate by letter, and receive the command information that host computer 6 sends.
System sets up with host computer 6 by USB interface 5 and communicates by letter, and host computer 6 sends command information, and command reception and processing module 35 are resolved and sent in 5 pairs of instructions of microprocessor.
Step S103, parameter configuration module 36 receives the configuration parameter instruction and carries out parameter configuration, comprises parameter configuration such as accumulative frequency, sampling number.
Step S104, trigger pip selects module 39 according to the trigger pip selection instruction, internal trigger signal or reception outer triggering signal that selective reception is produced by internal trigger signal generator module 38.
Step S105, collecting work begins, and sampled data receiver module 32 receives sampled data when the clock signal that A/D converting unit 2 output sampled datas can be exported.
Step S106, each the accumulation process module in the accumulation process assembly 33 is carried out accumulation process to the sampled data that each sampled data receiver module receives, and obtains the accumulation result data;
Step S107 judges whether to reach the accumulative frequency of regulation, if, stop to add up, execution in step S108, otherwise, continue execution in step S106.
Step S108, each the accumulation process module in the accumulation process assembly 33 is temporarily stored in the accumulation result data among the step S106 in each corresponding in the dual port RAM assembly 34 dual port RAM.
Step S109, data conversion storage module 310 is according to instruction, with the accumulation result data conversion storage in each dual port RAM in external memory storage SRAM7.
Step S110, data upload module 37 uploads to host computer 6 with the data among the SRAM7 by microprocessor 4 and USB interface 5 according to the data upload instruction.
Step S111 judges whether to gather again, if, execution in step S105, otherwise this gathers end.
In a word, what embodiment of the present utility model announced is its preferred implementation, but is not limited to this.Those of ordinary skill in the art understands spirit of the present utility model very easily according to the foregoing description, and makes different amplifications and variation, but only otherwise break away from spirit of the present utility model, all within protection domain of the present utility model.
Claims (6)
1. high-speed data acquistion system based on FPGA, it is characterized in that: comprise the difference amplifying unit that receives simulating signal, the A/D converting unit that is connected with described difference amplifying unit, the FPGA processing unit that is connected with described A/D converting unit, with the microprocessor that described FPGA processing unit is connected, described microprocessor is connected with host computer by communication interface.
2. the high-speed data acquistion system based on FPGA according to claim 1 is characterized in that: described difference amplifying unit comprises two differential amplifiers at least, is respectively first differential amplifier and second differential amplifier.
3. the high-speed data acquistion system based on FPGA according to claim 2, it is characterized in that: described A/D converting unit comprises two A/D converters at least, is respectively first A/D converter that is connected with described first differential amplifier and second A/D converter that is connected with described second differential amplifier.
4. the high-speed data acquistion system based on FPGA according to claim 3, it is characterized in that: described FPGA processing unit comprise at least to described first A/D converter provide sampled clock signal the first sampling clock module, to provide the second sampling clock module of sampled clock signal, the clock phase difference output of described first sampling clock module and the described second sampling clock module to described second A/D converter be 180 degree.
5. according to claim 3 or 4 described high-speed data acquistion systems based on FPGA, it is characterized in that: the sampling rate of the sampling rate of described first A/D converter and described second A/D converter is 125MSPS.
6. the high-speed data acquistion system based on FPGA according to claim 1 is characterized in that: described communication interface is a USB interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201020699992 CN202033737U (en) | 2010-12-31 | 2010-12-31 | FPGA-based high-speed data acquisition system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201020699992 CN202033737U (en) | 2010-12-31 | 2010-12-31 | FPGA-based high-speed data acquisition system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202033737U true CN202033737U (en) | 2011-11-09 |
Family
ID=44896026
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201020699992 Expired - Fee Related CN202033737U (en) | 2010-12-31 | 2010-12-31 | FPGA-based high-speed data acquisition system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202033737U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102176142A (en) * | 2010-12-31 | 2011-09-07 | 威海北洋电气集团股份有限公司 | FPGA (Field Programmable Gate Array)-based high-speed data acquisition system |
| CN105044447A (en) * | 2015-08-27 | 2015-11-11 | 许继集团有限公司 | Double AD real-time monitoring acquisition circuit |
| CN114153772A (en) * | 2020-09-08 | 2022-03-08 | 珠海全志科技股份有限公司 | Method and device for determining data sampling point |
-
2010
- 2010-12-31 CN CN 201020699992 patent/CN202033737U/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102176142A (en) * | 2010-12-31 | 2011-09-07 | 威海北洋电气集团股份有限公司 | FPGA (Field Programmable Gate Array)-based high-speed data acquisition system |
| CN102176142B (en) * | 2010-12-31 | 2016-03-30 | 威海北洋光电信息技术股份公司 | Based on the high-speed data acquistion system of FPGA |
| CN105044447A (en) * | 2015-08-27 | 2015-11-11 | 许继集团有限公司 | Double AD real-time monitoring acquisition circuit |
| CN105044447B (en) * | 2015-08-27 | 2018-05-11 | 许继集团有限公司 | Double AD monitor Acquisition Circuit in real time |
| CN114153772A (en) * | 2020-09-08 | 2022-03-08 | 珠海全志科技股份有限公司 | Method and device for determining data sampling point |
| CN114153772B (en) * | 2020-09-08 | 2024-04-12 | 珠海全志科技股份有限公司 | Method and device for determining data sampling points |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102176142B (en) | Based on the high-speed data acquistion system of FPGA | |
| CN105577197A (en) | High-speed data collection system for radio telescope | |
| CN202033737U (en) | FPGA-based high-speed data acquisition system | |
| CN103033807B (en) | Portable ultrasonic imaging system receiving front-end device | |
| CN111614357B (en) | Ultra-multichannel embedded high-speed signal acquisition and processing system and method | |
| CN116841932B (en) | Flexibly-connectable portable high-speed data access equipment and working method thereof | |
| CN106354063A (en) | High-speed four-channel signal acquisition board | |
| CN102540146B (en) | Configurable digital correlator for complete polarization microwave radiometer system | |
| CN104931780A (en) | Synchronous sampling, converting and acquiring device for power harmonic 16-channel signal input | |
| CN206892623U (en) | Sonar underwater multichannel data acquisition module | |
| CN103972909A (en) | TSC (thyristor switched capacitor) system and RS485 communication method thereof based on FPGA (Field Programmable Gate Array) | |
| CN201966896U (en) | Wireless wideband multi-channel signal processing board | |
| CN206178390U (en) | High -speed four -channel signal acquisition board | |
| CN103067240A (en) | Switching circuit of four-channel serial bus and four-channel controller area network (CAN) bus | |
| CN210924247U (en) | Real-time processor for multi-path photoelectric sensor acquisition | |
| CN113659989B (en) | Advanced setting high-speed successive approximation type analog-to-digital converter | |
| CN104121828A (en) | Speed-grading and impact signal flexible collecting method | |
| CN201293939Y (en) | High-speed data acquisition system | |
| CN105607520A (en) | Remote measurement acquisition control device for general extensible spacecraft | |
| CN206745358U (en) | A kind of nuclear magnetic resonance digit receiver | |
| CN204695063U (en) | A kind of High Speed Data Acquisition Circuit | |
| CN205427839U (en) | Computer USB interface data collection system | |
| CN202940800U (en) | High-orbit remote-sensing satellite-demodulation signal processing platform | |
| CN208537944U (en) | A kind of CPCI intermediate frequency collector | |
| CN102723977B (en) | Shortwave eight-channel adaptive array signal processor based on CPCI (Compact Peripheral Component Interconnect) bus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20111109 Termination date: 20151231 |
|
| EXPY | Termination of patent right or utility model |