CN201966896U - Wireless wideband multi-channel signal processing board - Google Patents

Abstract

The utility model relates to a wireless and digital signal processing field, in particular to a wireless wideband multi-channel signal processing board. A large-scale programmable logic controlling component FPGA (field programmable gate array) is adopted in the wireless wideband multi-channel signal processing board to form a plurality of digital down converters, and wide band signals are divided into a plurality of narrow band signals to be processed simultaneously, thereby guaranteeing that an input of intermediate frequency signals and an output of baseband signals can be realized in continuous data flow mode. The real-time data storage can be realized through a cache FIFO (first inlet first outlet) and a cache SDRAM (synchronous dynamic random access memory), and simultaneously, a high-speed DSP (digital signal processor) is operated and transplanted so that a CPU (central processing unit) source cannot be occupied excessively, and the system processing performance can be guaranteed to improve greatly. Therefore, the wireless wideband multi-channel signal processing board not only greatly improves processing speed, but also is stronger in processing capacity, larger in storage capacity and more flexible in connector, and has expandability.

Description

A kind of radio broadband multi channel signals disposable plates

Technical field

The utility model relates to radio and digital processing field, is specifically related to a kind of radio broadband multi channel signals disposable plates that is applied to the monitoring of radio spacing wave, spectrum management, radar information, communication base station and other signal processing.

Background technology

In the radio spacing wave monitoring because the bandwidth of spacing wave in 1.5～3000Mhz (or wideer) scope, therefore need be down-converted to the RF radiofrequency signal intermediate frequency reprocessing.Consider dynamic range and intermediate-frequency bandwidth broad (as more than 10Mhz), the rate requirement of general analog to digital converter-ADC is greater than 40Msps, and sampling resolution is more than 12bit.Data volume after the sampling is very big like this, and all-purpose computer can not be handled in real time, need carry out Digital Down Convert with the reduction data flow to sampled data, and extract one or more baseband signals.The subject matter of integrated circuit board comprises at present:

1, can only handle the signal of 1 passage in real time,, need time-division processing, can not handle a plurality of signals simultaneously when midband internal memory during at a plurality of signal.

2, most high-speed collection card all are the data flow after the big capacity synchronous DRAM-SDRAM of preparation stores ADC, transfer to computer CPU and handle by PCI (external equipment interconnect standard) bus again.Because the speed data stream after the ADC sampling can not be handled data continuously greater than the pci bus frequency; Dispose big capacity internal memory as capture card, can too much take cpu resource.

3, interface is dumb, and control is complicated.

The utility model content

In order to address the above problem, the purpose of this utility model is to provide a kind of processing speed radio broadband multi channel signals disposable plates faster.

To achieve these goals, the technical scheme that the utility model adopted is as follows:

A kind of radio broadband multi channel signals disposable plates comprises the high speed analog converter, and the SMA radio-frequency joint that is connected with the analog input end of described high speed analog converter; This radio broadband multi channel signals disposable plates also comprises:

Scale programmable logic device, be configured with multi-path digital down-conversion passage in described scale programmable logic device, the multi-path digital down converter address of described scale programmable logic device is connected with the digital output end of described high speed analog converter respectively with data/address bus;

The high speed FIFO buffer, the address mouth of described high speed FIFO buffer is connected with data port with the address mouth of described scale programmable logic device respectively with data port;

The high-speed floating point digital signal processor, the data input pin of described high-speed floating point digital signal processor is connected with the data output end of the digital output end of described scale programmable logic device and described high speed FIFO buffer;

The high-speed synchronous dynamic random access memory, the address mouth of described high-speed synchronous dynamic random access memory is connected with data port with the address mouth of described high-speed floating point digital signal processor respectively with data port; And

Pci bus interface connects described scale programmable logic device and external computer turnover bus communication.

FIFO: first in first out, PCI-external equipment interconnect standard.SMA is the abbreviation of Sub-Miniature-A.

Described radio broadband multi channel signals disposable plates also is connected with the peripheral expansion interface on described high-speed floating point digital signal processor, described peripheral expansion interface comprises high-speed synchronous serial line interface and twin wire serial bus interface.

Described radio broadband multi channel signals disposable plates, described high speed analog converter is: the high speed analog converter of 14 bit resolutions and 100MSps sample rate.Wherein: MSps promptly is: the per second analog to digital converter is adopted and is counted.

Described radio broadband multi channel signals disposable plates, described pci bus interface are PCI 2.0 bus interface.

Described radio broadband multi channel signals disposable plates also is connected with a high-speed synchronous serial line interface (SPI) on the multichannel buffer serial port (MCBSP) of described high-speed floating point digital signal processor.Can extend as the spi bus use by the MCBSP interface, can conveniently control the external equipment of SPI interface.

The utility model at first adopts extensive programmable logic controller (PLC) spare FPGA to construct multi-path digital down-conversion passage, broadband signal is divided into a plurality of narrow band signals handles simultaneously, guarantee that intermediate-freuqncy signal input and baseband signal output can realize by continuous-data stream mode.Next comes the real-time storage data by high-speed cache FIFO and SDRAM, simultaneously computing is transplanted the high-speed dsp chip and carries out, and exceeds to take computer CPU resource, guarantees that the system handles performance significantly improves.A plurality of interfaces have been expanded by DSP and FPGA at last.

Therefore, the utility model not only processing speed is greatly improved, and disposal ability is stronger, memory capacity is bigger, interface is flexible more, have extensibility.

Description of drawings

Accompanying drawing described herein is used to provide further understanding of the present utility model, constitutes the application's a part, does not constitute to improper qualification of the present utility model, in the accompanying drawings:

Fig. 1 is the utility model theory structure block diagram;

Fig. 2 is a FPGA structure multichannel DDC theory diagram of the present utility model.

Among the figure:

1, SMA radio-frequency joint 2, high-speed ADC

3, extensive programable logic device FPGA 4, high speed FIFO buffer

5, high speed SDRAM 6, peripheral expansion interface

7, high-speed floating point DSP 8, pci bus interface

Embodiment

Describe the utility model in detail below in conjunction with specific embodiment, be used for explaining the utility model in this illustrative examples of the present utility model and explanation, but not as to qualification of the present utility model.

As shown in Figure 1, present embodiment discloses a kind of radio broadband multi channel signals disposable plates, comprise SMA radio-frequency joint 1, high-speed ADC 2, extensive programable logic device FPGA 3, high speed FIFO buffer 4, high speed SDRAM 5, peripheral expansion interface 6, high-speed floating point DSP 7, pci bus interface 8, SMA radio-frequency joint 1 is connected with the analog input end of high-speed ADC 2, the multi-path digital down converter address of scale programmable logic device FPGA 3 is connected with the digital output end of high-speed ADC 2 respectively with data/address bus, the address mouth of high speed FIFO buffer 4 is connected with data port with the address mouth of the scale programmable logic device FPGA of institute 3 respectively with data port, the digital output end of the data input pin of high-speed floating point DSP 7 and scale programmable logic device FPGA 3, and the data output end of high speed FIFO buffer 4 connects, the address mouth of high speed SDRAM 5 is connected with data port with the address mouth of high-speed floating point DSP 7 respectively with data port, peripheral expansion interface 6 is connected on the high-speed floating point DSP 7, peripheral expansion interface 6 comprises high-speed synchronous serial line interface-MCBSP interface, and twin wire serial bus interface-SPI interface, pci bus interface 8 connects extensive programable logic device FPGA 3 and external computer turnover bus communication.

In this example, high-speed ADC is selected for use: ADC6645, FPGA selects for use: EP2S35, the high speed FIFO buffer is selected for use: IDT72V285L10, high-speed floating point DSP selects for use: TMS320C6713, SDRAM selects for use: MT48LC32M16A2TG.

Wherein, high-speed floating point DSP TMS320C6713HPI host interface is connected with the service bridge chip PCI2040 of TI company, and the HPI bus of TMS320C6713 is converted to 32 pci buss.Simultaneously the two-way MCBSP of TMS320C6713 and 1 road I2C interface extend to the expansion interface of signal-processing board by the 6-J6 socket, and the MCBSP interface can be used as spi bus and uses.

The utility model is finished the multichannel logical channel by the logical DDC passage of FPGA structure multi-path digital down-conversion, can handle multiple signals in real time; The Combination Design of high performance float-point DSP digital signal processor DSP and FIFO has solved the continuous data of broadband signal and has handled and too much taken the computer CPU problem of resource, and the data flow of every way word down-conversion is exported provides the high speed FIFO buffer memory; Comprise PCI, SPI and I2C by DSP and FPGA expansion interface, can be used to control external equipment and transfer of data.PCI 2.0 bus communications are adopted in disposable plates and compunication.

The utility model front end adopts 14 bit resolutions and 100MSps sample rate high-speed ADC, can realize the collection of broadband signal.Support maximum 50MHz bandwidth, the analog signal input of the highest 200MHz.Analog signal bandwidth after the sampling can be provided with between 0～50Mhz, after the multichannel DDC passage of FPGA structure is handled, can reduce data sampling rate according to the D multiple, and multiplexer channel can be provided, and each passage is separate.Can realize simultaneously the synchronous extraction of multichannel road narrow band signal, selected narrow band signal can be downconverted to base band, obtain baseband signal and export in I/Q data flow mode.Because the data output rating after extracting reduces, the data space of the follow-up DSP of system and the requirement of processing speed are all reduced greatly.

If the bandwidth after DDC handles still can not meet the demands, can further reduce data flow by follow-up high-speed floating point DSP, and finish such as Digital Signal Processing such as FFT, carrier wave recovery, digital demodulation and digital filterings.The data cache FIFO that plate carries can provide buffer memory to the output of the data flow after every way word down-conversion, realizes the real-time processing of multi channel signals.For storage and the transmission that guarantees mass data, dispose the SDRAM of 64M byte.Design PCI simultaneously and adopt the service bridge chip that the HPI bus of DSP is converted to 32 pci buss, guarantee the high speed data transfer of integrated circuit board and computer.Integrated circuit board is also expanded external interface SPI and I2C bus interface, so that can control other external equipment.

Fig. 2 is described as follows for the know-why of FGPA structure multichannel DDC passage.For Fig. 2, the unit impulse response of establishing the FIR filter is h (n), after the mixing is so:

$y\left(n\right)\cos \left({\mathrm{\ω}}_{0}n\right)+j\·y\left(n\right)\sin \left({\mathrm{\ω}}_{0}n\right)=y\left(n\right)e^{j{\mathrm{\ω}}_{0}n}$

First via signal representation after the mixing and filtering is:

$y_1\left(n\right)=y\left(n\right)e^{j{\mathrm{\ω}}_{0}n}*h\left(n\right)$

Final result is:

$y_1\left(m\right)=[y\left(n\right)e^{j{\mathrm{\ω}}_{0}n}*h\left(n\right)]\·\underset{n}{\mathrm{\Σ}}\mathrm{\δ}(n-\mathrm{mD})$

Extracting bandwidth from wideband input signal y (n) is B, and centre frequency is ω ₀One section echo signal, this signal is designated as s1 (n).S1 (n) can be expressed as:

In the formula, a (n),

Be respectively the range weight and the phase component of signal, ω ₀Be signal carrier frequency or centre frequency.Be expressed as with quadrature component:

s1(n)＝I(n)cos(ω ₀n)-Q(n)sin(ω ₀n)；

Wherein,

Be called the in-phase component and the quadrature component of signal, because carrier frequency ω ₀Do not contain information, so the information of echo signal s (n) is present among I (n), the Q (n) fully.

y ₁(n) be exactly to be real part with I (n), the complex signal that Q (n) forms for imaginary part.Y just ₁(n) can be expressed as:

y ₁(n)＝I(n)+iQ(n)

With y ₁(n) carry out the first via signal y that D doubly extracts ₁(m) can be expressed as:

$y_1\left(m\right)=[I\left(n\right)+\mathrm{iQ}\left(n\right)]\·\underset{n}{\mathrm{\Σ}}\mathrm{\δ}(n-\mathrm{mD})=I1\left(m\right)+\mathrm{iQ}1\left(m\right).$

Multiple difference according to D doubly extracts can obtain broadband or narrow band signal.In like manner, can obtain signal I2 (m)/Q2 (m), I3 (m)/Q3 (m), I4 (m)/Q4 (m) after the extraction on other several roads according to above-mentioned principle.This is the process of four tunnel signalling channels, as long as the capacity of FPGA is enough big, can obtain more passage.

More than technical scheme that the utility model embodiment is provided be described in detail, used specific case herein principle and the execution mode of the utility model embodiment are set forth, the explanation of above embodiment only is applicable to the principle that helps to understand the utility model embodiment; Simultaneously, for one of ordinary skill in the art, according to the utility model embodiment, the part that on embodiment and range of application, all can change, in sum, this description should not be construed as restriction of the present utility model.

Claims (5)

1. a radio broadband multi channel signals disposable plates comprises the high speed analog converter, and the SMA radio-frequency joint that is connected with the analog input end of described high speed analog converter, it is characterized in that:

This radio broadband multi channel signals disposable plates also comprises:

Scale programmable logic device, be configured with multi-path digital down-conversion passage in described scale programmable logic device, the multi-path digital down converter address of described scale programmable logic device is connected with the digital output end of described high speed analog converter respectively with data/address bus;

The high speed FIFO buffer, the address mouth of described high speed FIFO buffer is connected with data port with the address mouth of described scale programmable logic device respectively with data port;

The high-speed floating point digital signal processor, the data input pin of described high-speed floating point digital signal processor is connected with the data output end of the digital output end of described scale programmable logic device and described high speed FIFO buffer;

The high-speed synchronous dynamic random access memory, the address mouth of described high-speed synchronous dynamic random access memory is connected with data port with the address mouth of described high-speed floating point digital signal processor respectively with data port; And

Pci bus interface connects described scale programmable logic device and external computer turnover bus communication.

2. radio according to claim 1 broadband multi channel signals disposable plates is characterized in that:

Also be connected with the peripheral expansion interface on described high-speed floating point digital signal processor, described peripheral expansion interface comprises high-speed synchronous serial line interface and twin wire serial bus interface.

3. radio according to claim 1 broadband multi channel signals disposable plates is characterized in that:

Described high speed analog converter is: the high speed analog converter of 14 bit resolutions and 100MSps sample rate.

4. radio according to claim 1 broadband multi channel signals disposable plates is characterized in that:

Described pci bus interface is PCI 2.0 bus interface.

5. radio according to claim 1 broadband multi channel signals disposable plates is characterized in that:

On the multichannel buffer serial port of described high-speed floating point digital signal processor, also be connected with a high-speed synchronous serial line interface.

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